* [Intel-gfx] [PATCH 1/2] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt
@ 2020-01-31 8:15 Chris Wilson
2020-01-31 8:15 ` [Intel-gfx] [PATCH 2/2] drm/i915/selftests: Also wait for the scratch buffer to be bound Chris Wilson
` (5 more replies)
0 siblings, 6 replies; 10+ messages in thread
From: Chris Wilson @ 2020-01-31 8:15 UTC (permalink / raw)
To: intel-gfx
In the rare cases where we are using the global GGTT for execution in
the selftests, we have marked them with PIN_USER knowing that they will
be bound as PIN_GLOBAL as well. However, we need to catch the extra flag
in deciding to use the async worker for such binds as well.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 3b23b431bd56..9e8c2e189aef 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -846,7 +846,8 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
IS_CHERRYVIEW(i915) /* fails with concurrent use/update */) {
ggtt->vm.insert_entries = bxt_vtd_ggtt_insert_entries__BKL;
ggtt->vm.insert_page = bxt_vtd_ggtt_insert_page__BKL;
- ggtt->vm.bind_async_flags = I915_VMA_GLOBAL_BIND;
+ ggtt->vm.bind_async_flags =
+ I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND;
}
ggtt->invalidate = gen8_ggtt_invalidate;
--
2.25.0
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^ permalink raw reply related [flat|nested] 10+ messages in thread* [Intel-gfx] [PATCH 2/2] drm/i915/selftests: Also wait for the scratch buffer to be bound 2020-01-31 8:15 [Intel-gfx] [PATCH 1/2] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt Chris Wilson @ 2020-01-31 8:15 ` Chris Wilson 2020-01-31 11:17 ` [Intel-gfx] [PATCH] " Chris Wilson 2020-01-31 14:26 ` Chris Wilson 2020-01-31 10:18 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt Patchwork ` (4 subsequent siblings) 5 siblings, 2 replies; 10+ messages in thread From: Chris Wilson @ 2020-01-31 8:15 UTC (permalink / raw) To: intel-gfx Since PIN_GLOBAL is no longer guaranteed to be synchronous, we must no forget to include a wait-for-vma prior to execution. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/selftest_workarounds.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c index ac1921854cbf..5ed323254ee1 100644 --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c @@ -583,6 +583,15 @@ static int check_dirty_whitelist(struct intel_context *ce) if (err) goto err_request; + i915_vma_lock(scratch); + err = i915_request_await_object(rq, scratch->obj, true); + if (err == 0) + err = i915_vma_move_to_active(scratch, rq, + EXEC_OBJECT_WRITE); + i915_vma_unlock(scratch); + if (err) + goto err_request; + err = engine->emit_bb_start(rq, batch->node.start, PAGE_SIZE, 0); -- 2.25.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/selftests: Also wait for the scratch buffer to be bound 2020-01-31 8:15 ` [Intel-gfx] [PATCH 2/2] drm/i915/selftests: Also wait for the scratch buffer to be bound Chris Wilson @ 2020-01-31 11:17 ` Chris Wilson 2020-01-31 14:26 ` Chris Wilson 1 sibling, 0 replies; 10+ messages in thread From: Chris Wilson @ 2020-01-31 11:17 UTC (permalink / raw) To: intel-gfx Since PIN_GLOBAL is no longer guaranteed to be synchronous, we must no forget to include a wait-for-vma prior to execution. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 ++++++++++ drivers/gpu/drm/i915/gt/selftest_workarounds.c | 9 +++++++++ 2 files changed, 19 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 5a7db279f702..8d7c3191137c 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1612,6 +1612,16 @@ static int engine_wa_list_verify(struct intel_context *ce, goto err_vma; } + i915_vma_lock(vma); + err = i915_request_await_object(rq, vma->obj, true); + if (err == 0) + err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); + i915_vma_unlock(vma); + if (err) { + i915_request_add(rq); + goto err_vma; + } + err = wa_list_srm(rq, wal, vma); if (err) goto err_vma; diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c index ac1921854cbf..5ed323254ee1 100644 --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c @@ -583,6 +583,15 @@ static int check_dirty_whitelist(struct intel_context *ce) if (err) goto err_request; + i915_vma_lock(scratch); + err = i915_request_await_object(rq, scratch->obj, true); + if (err == 0) + err = i915_vma_move_to_active(scratch, rq, + EXEC_OBJECT_WRITE); + i915_vma_unlock(scratch); + if (err) + goto err_request; + err = engine->emit_bb_start(rq, batch->node.start, PAGE_SIZE, 0); -- 2.25.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/selftests: Also wait for the scratch buffer to be bound 2020-01-31 8:15 ` [Intel-gfx] [PATCH 2/2] drm/i915/selftests: Also wait for the scratch buffer to be bound Chris Wilson 2020-01-31 11:17 ` [Intel-gfx] [PATCH] " Chris Wilson @ 2020-01-31 14:26 ` Chris Wilson 2020-01-31 15:03 ` Mika Kuoppala 1 sibling, 1 reply; 10+ messages in thread From: Chris Wilson @ 2020-01-31 14:26 UTC (permalink / raw) To: intel-gfx Since PIN_GLOBAL is no longer guaranteed to be synchronous, we must no forget to include a wait-for-vma prior to execution. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 ++++++ drivers/gpu/drm/i915/gt/selftest_lrc.c | 33 +++++++++++++++++++ .../gpu/drm/i915/gt/selftest_workarounds.c | 9 +++++ 3 files changed, 52 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 5a7db279f702..8d7c3191137c 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1612,6 +1612,16 @@ static int engine_wa_list_verify(struct intel_context *ce, goto err_vma; } + i915_vma_lock(vma); + err = i915_request_await_object(rq, vma->obj, true); + if (err == 0) + err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); + i915_vma_unlock(vma); + if (err) { + i915_request_add(rq); + goto err_vma; + } + err = wa_list_srm(rq, wal, vma); if (err) goto err_vma; diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index f5214a374fb7..0efb46665667 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -734,6 +734,10 @@ static int live_timeslice_preempt(void *arg) if (err) goto err_map; + err = i915_vma_sync(vma); + if (err) + goto err_pin; + for_each_prime_number_from(count, 1, 16) { struct intel_engine_cs *engine; enum intel_engine_id id; @@ -827,6 +831,10 @@ static int live_timeslice_queue(void *arg) if (err) goto err_map; + err = i915_vma_sync(vma); + if (err) + goto err_unpin; + for_each_engine(engine, gt, id) { struct i915_sched_attr attr = { .priority = I915_USER_PRIORITY(I915_PRIORITY_MAX), @@ -913,6 +921,7 @@ static int live_timeslice_queue(void *arg) break; } +err_unpin: i915_vma_unpin(vma); err_map: i915_gem_object_unpin_map(obj); @@ -971,6 +980,10 @@ static int live_busywait_preempt(void *arg) if (err) goto err_map; + err = i915_vma_sync(vma); + if (err) + goto err_vma; + for_each_engine(engine, gt, id) { struct i915_request *lo, *hi; struct igt_live_test t; @@ -3204,6 +3217,10 @@ static int preserved_virtual_engine(struct intel_gt *gt, if (IS_ERR(scratch)) return PTR_ERR(scratch); + err = i915_vma_sync(scratch); + if (err) + goto out_scratch; + ve = intel_execlists_create_virtual(siblings, nsibling); if (IS_ERR(ve)) { err = PTR_ERR(ve); @@ -4030,8 +4047,16 @@ static int __live_lrc_state(struct intel_engine_cs *engine, *cs++ = i915_ggtt_offset(scratch) + RING_TAIL_IDX * sizeof(u32); *cs++ = 0; + i915_vma_lock(scratch); + err = i915_request_await_object(rq, scratch->obj, true); + if (!err) + err = i915_vma_move_to_active(scratch, rq, EXEC_OBJECT_WRITE); + i915_vma_unlock(scratch); + i915_request_get(rq); i915_request_add(rq); + if (err) + goto err_rq; intel_engine_flush_submission(engine); expected[RING_TAIL_IDX] = ce->ring->tail; @@ -4166,8 +4191,16 @@ static int __live_gpr_clear(struct intel_engine_cs *engine, *cs++ = 0; } + i915_vma_lock(scratch); + err = i915_request_await_object(rq, scratch->obj, true); + if (!err) + err = i915_vma_move_to_active(scratch, rq, EXEC_OBJECT_WRITE); + i915_vma_unlock(scratch); + i915_request_get(rq); i915_request_add(rq); + if (err) + goto err_rq; if (i915_request_wait(rq, 0, HZ / 5) < 0) { err = -ETIME; diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c index ac1921854cbf..5ed323254ee1 100644 --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c @@ -583,6 +583,15 @@ static int check_dirty_whitelist(struct intel_context *ce) if (err) goto err_request; + i915_vma_lock(scratch); + err = i915_request_await_object(rq, scratch->obj, true); + if (err == 0) + err = i915_vma_move_to_active(scratch, rq, + EXEC_OBJECT_WRITE); + i915_vma_unlock(scratch); + if (err) + goto err_request; + err = engine->emit_bb_start(rq, batch->node.start, PAGE_SIZE, 0); -- 2.25.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/selftests: Also wait for the scratch buffer to be bound 2020-01-31 14:26 ` Chris Wilson @ 2020-01-31 15:03 ` Mika Kuoppala 0 siblings, 0 replies; 10+ messages in thread From: Mika Kuoppala @ 2020-01-31 15:03 UTC (permalink / raw) To: Chris Wilson, intel-gfx Chris Wilson <chris@chris-wilson.co.uk> writes: > Since PIN_GLOBAL is no longer guaranteed to be synchronous, we must no > forget to include a wait-for-vma prior to execution. Dunno if we got em all, we soon know. Cried for helper but lets move first, Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 ++++++ > drivers/gpu/drm/i915/gt/selftest_lrc.c | 33 +++++++++++++++++++ > .../gpu/drm/i915/gt/selftest_workarounds.c | 9 +++++ > 3 files changed, 52 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 5a7db279f702..8d7c3191137c 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -1612,6 +1612,16 @@ static int engine_wa_list_verify(struct intel_context *ce, > goto err_vma; > } > > + i915_vma_lock(vma); > + err = i915_request_await_object(rq, vma->obj, true); > + if (err == 0) > + err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); > + i915_vma_unlock(vma); > + if (err) { > + i915_request_add(rq); > + goto err_vma; > + } > + > err = wa_list_srm(rq, wal, vma); > if (err) > goto err_vma; > diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c > index f5214a374fb7..0efb46665667 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c > +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c > @@ -734,6 +734,10 @@ static int live_timeslice_preempt(void *arg) > if (err) > goto err_map; > > + err = i915_vma_sync(vma); > + if (err) > + goto err_pin; > + > for_each_prime_number_from(count, 1, 16) { > struct intel_engine_cs *engine; > enum intel_engine_id id; > @@ -827,6 +831,10 @@ static int live_timeslice_queue(void *arg) > if (err) > goto err_map; > > + err = i915_vma_sync(vma); > + if (err) > + goto err_unpin; > + > for_each_engine(engine, gt, id) { > struct i915_sched_attr attr = { > .priority = I915_USER_PRIORITY(I915_PRIORITY_MAX), > @@ -913,6 +921,7 @@ static int live_timeslice_queue(void *arg) > break; > } > > +err_unpin: > i915_vma_unpin(vma); > err_map: > i915_gem_object_unpin_map(obj); > @@ -971,6 +980,10 @@ static int live_busywait_preempt(void *arg) > if (err) > goto err_map; > > + err = i915_vma_sync(vma); > + if (err) > + goto err_vma; > + > for_each_engine(engine, gt, id) { > struct i915_request *lo, *hi; > struct igt_live_test t; > @@ -3204,6 +3217,10 @@ static int preserved_virtual_engine(struct intel_gt *gt, > if (IS_ERR(scratch)) > return PTR_ERR(scratch); > > + err = i915_vma_sync(scratch); > + if (err) > + goto out_scratch; > + > ve = intel_execlists_create_virtual(siblings, nsibling); > if (IS_ERR(ve)) { > err = PTR_ERR(ve); > @@ -4030,8 +4047,16 @@ static int __live_lrc_state(struct intel_engine_cs *engine, > *cs++ = i915_ggtt_offset(scratch) + RING_TAIL_IDX * sizeof(u32); > *cs++ = 0; > > + i915_vma_lock(scratch); > + err = i915_request_await_object(rq, scratch->obj, true); > + if (!err) > + err = i915_vma_move_to_active(scratch, rq, EXEC_OBJECT_WRITE); > + i915_vma_unlock(scratch); > + > i915_request_get(rq); > i915_request_add(rq); > + if (err) > + goto err_rq; > > intel_engine_flush_submission(engine); > expected[RING_TAIL_IDX] = ce->ring->tail; > @@ -4166,8 +4191,16 @@ static int __live_gpr_clear(struct intel_engine_cs *engine, > *cs++ = 0; > } > > + i915_vma_lock(scratch); > + err = i915_request_await_object(rq, scratch->obj, true); > + if (!err) > + err = i915_vma_move_to_active(scratch, rq, EXEC_OBJECT_WRITE); > + i915_vma_unlock(scratch); > + > i915_request_get(rq); > i915_request_add(rq); > + if (err) > + goto err_rq; > > if (i915_request_wait(rq, 0, HZ / 5) < 0) { > err = -ETIME; > diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c > index ac1921854cbf..5ed323254ee1 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c > @@ -583,6 +583,15 @@ static int check_dirty_whitelist(struct intel_context *ce) > if (err) > goto err_request; > > + i915_vma_lock(scratch); > + err = i915_request_await_object(rq, scratch->obj, true); > + if (err == 0) > + err = i915_vma_move_to_active(scratch, rq, > + EXEC_OBJECT_WRITE); > + i915_vma_unlock(scratch); > + if (err) > + goto err_request; > + > err = engine->emit_bb_start(rq, > batch->node.start, PAGE_SIZE, > 0); > -- > 2.25.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt 2020-01-31 8:15 [Intel-gfx] [PATCH 1/2] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt Chris Wilson 2020-01-31 8:15 ` [Intel-gfx] [PATCH 2/2] drm/i915/selftests: Also wait for the scratch buffer to be bound Chris Wilson @ 2020-01-31 10:18 ` Patchwork 2020-01-31 14:23 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt (rev2) Patchwork ` (3 subsequent siblings) 5 siblings, 0 replies; 10+ messages in thread From: Patchwork @ 2020-01-31 10:18 UTC (permalink / raw) To: Chris Wilson; +Cc: intel-gfx == Series Details == Series: series starting with [1/2] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt URL : https://patchwork.freedesktop.org/series/72809/ State : warning == Summary == $ dim checkpatch origin/drm-tip 363fa0343c9f drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt -:24: ERROR:CODE_INDENT: code indent should use tabs where possible #24: FILE: drivers/gpu/drm/i915/gt/intel_ggtt.c:850: +^I^I ^II915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND;$ -:24: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #24: FILE: drivers/gpu/drm/i915/gt/intel_ggtt.c:850: +^I^I ^II915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND;$ total: 1 errors, 1 warnings, 0 checks, 9 lines checked 50461f875990 drm/i915/selftests: Also wait for the scratch buffer to be bound _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt (rev2) 2020-01-31 8:15 [Intel-gfx] [PATCH 1/2] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt Chris Wilson 2020-01-31 8:15 ` [Intel-gfx] [PATCH 2/2] drm/i915/selftests: Also wait for the scratch buffer to be bound Chris Wilson 2020-01-31 10:18 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt Patchwork @ 2020-01-31 14:23 ` Patchwork 2020-01-31 14:37 ` [Intel-gfx] [PATCH 1/2] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt Mika Kuoppala ` (2 subsequent siblings) 5 siblings, 0 replies; 10+ messages in thread From: Patchwork @ 2020-01-31 14:23 UTC (permalink / raw) To: Chris Wilson; +Cc: intel-gfx == Series Details == Series: series starting with [1/2] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt (rev2) URL : https://patchwork.freedesktop.org/series/72809/ State : warning == Summary == $ dim checkpatch origin/drm-tip bb9f5c3f2305 drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt -:24: ERROR:CODE_INDENT: code indent should use tabs where possible #24: FILE: drivers/gpu/drm/i915/gt/intel_ggtt.c:850: +^I^I ^II915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND;$ -:24: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #24: FILE: drivers/gpu/drm/i915/gt/intel_ggtt.c:850: +^I^I ^II915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND;$ total: 1 errors, 1 warnings, 0 checks, 9 lines checked 0221737f0592 drm/i915/selftests: Also wait for the scratch buffer to be bound _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt 2020-01-31 8:15 [Intel-gfx] [PATCH 1/2] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt Chris Wilson ` (2 preceding siblings ...) 2020-01-31 14:23 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt (rev2) Patchwork @ 2020-01-31 14:37 ` Mika Kuoppala 2020-01-31 14:52 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt (rev2) Patchwork 2020-01-31 19:38 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/2] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt (rev3) Patchwork 5 siblings, 0 replies; 10+ messages in thread From: Mika Kuoppala @ 2020-01-31 14:37 UTC (permalink / raw) To: Chris Wilson, intel-gfx Chris Wilson <chris@chris-wilson.co.uk> writes: > In the rare cases where we are using the global GGTT for execution in > the selftests, we have marked them with PIN_USER knowing that they will > be bound as PIN_GLOBAL as well. However, we need to catch the extra flag > in deciding to use the async worker for such binds as well. > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> > --- > drivers/gpu/drm/i915/gt/intel_ggtt.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c > index 3b23b431bd56..9e8c2e189aef 100644 > --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c > @@ -846,7 +846,8 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt) > IS_CHERRYVIEW(i915) /* fails with concurrent use/update */) { > ggtt->vm.insert_entries = bxt_vtd_ggtt_insert_entries__BKL; > ggtt->vm.insert_page = bxt_vtd_ggtt_insert_page__BKL; > - ggtt->vm.bind_async_flags = I915_VMA_GLOBAL_BIND; > + ggtt->vm.bind_async_flags = > + I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND; > } > > ggtt->invalidate = gen8_ggtt_invalidate; > -- > 2.25.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt (rev2) 2020-01-31 8:15 [Intel-gfx] [PATCH 1/2] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt Chris Wilson ` (3 preceding siblings ...) 2020-01-31 14:37 ` [Intel-gfx] [PATCH 1/2] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt Mika Kuoppala @ 2020-01-31 14:52 ` Patchwork 2020-01-31 19:38 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/2] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt (rev3) Patchwork 5 siblings, 0 replies; 10+ messages in thread From: Patchwork @ 2020-01-31 14:52 UTC (permalink / raw) To: Chris Wilson; +Cc: intel-gfx == Series Details == Series: series starting with [1/2] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt (rev2) URL : https://patchwork.freedesktop.org/series/72809/ State : success == Summary == CI Bug Log - changes from CI_DRM_7850 -> Patchwork_16354 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16354/index.html Known issues ------------ Here are the changes found in Patchwork_16354 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_selftest@live_blt: - fi-hsw-4770r: [PASS][1] -> [DMESG-FAIL][2] ([i915#725]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/fi-hsw-4770r/igt@i915_selftest@live_blt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16354/fi-hsw-4770r/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_gem_contexts: - fi-cfl-8700k: [PASS][3] -> [INCOMPLETE][4] ([i915#424]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16354/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html #### Possible fixes #### * igt@gem_close_race@basic-threads: - fi-byt-n2820: [TIMEOUT][5] ([fdo#112271] / [i915#1084] / [i915#816]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/fi-byt-n2820/igt@gem_close_race@basic-threads.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16354/fi-byt-n2820/igt@gem_close_race@basic-threads.html * igt@gem_exec_store@basic-all: - fi-apl-guc: [TIMEOUT][7] ([fdo#112271]) -> [PASS][8] +8 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/fi-apl-guc/igt@gem_exec_store@basic-all.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16354/fi-apl-guc/igt@gem_exec_store@basic-all.html * igt@gem_tiled_fence_blits@basic: - fi-apl-guc: [SKIP][9] ([fdo#109271]) -> [PASS][10] +47 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/fi-apl-guc/igt@gem_tiled_fence_blits@basic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16354/fi-apl-guc/igt@gem_tiled_fence_blits@basic.html * igt@kms_addfb_basic@bad-pitch-32: - fi-tgl-y: [DMESG-WARN][11] ([CI#94] / [i915#402]) -> [PASS][12] +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/fi-tgl-y/igt@kms_addfb_basic@bad-pitch-32.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16354/fi-tgl-y/igt@kms_addfb_basic@bad-pitch-32.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][13] ([fdo#111407]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16354/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407 [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271 [i915#1084]: https://gitlab.freedesktop.org/drm/intel/issues/1084 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 [i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816 Participating hosts (43 -> 39) ------------------------------ Additional (7): fi-bsw-n3050 fi-byt-j1900 fi-skl-6770hq fi-snb-2520m fi-whl-u fi-elk-e7500 fi-kbl-r Missing (11): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-hsw-peppy fi-glk-dsi fi-byt-squawks fi-bsw-cyan fi-cfl-8109u fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_7850 -> Patchwork_16354 CI-20190529: 20190529 CI_DRM_7850: ae66f2257648ce52c51298506977baa32873c9d5 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5407: a9d69f51dadbcbc53527671f87572d05c3370cba @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16354: 0221737f059279a78c56ee70b14fe8747947f100 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 0221737f0592 drm/i915/selftests: Also wait for the scratch buffer to be bound bb9f5c3f2305 drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16354/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/2] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt (rev3) 2020-01-31 8:15 [Intel-gfx] [PATCH 1/2] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt Chris Wilson ` (4 preceding siblings ...) 2020-01-31 14:52 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt (rev2) Patchwork @ 2020-01-31 19:38 ` Patchwork 5 siblings, 0 replies; 10+ messages in thread From: Patchwork @ 2020-01-31 19:38 UTC (permalink / raw) To: Chris Wilson; +Cc: intel-gfx == Series Details == Series: series starting with [1/2] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt (rev3) URL : https://patchwork.freedesktop.org/series/72809/ State : failure == Summary == Applying: drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt .git/rebase-apply/patch:15: space before tab in indent. I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND; warning: 1 line adds whitespace errors. Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/gt/intel_ggtt.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/gt/intel_ggtt.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/gt/intel_ggtt.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0001 drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2020-01-31 19:38 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2020-01-31 8:15 [Intel-gfx] [PATCH 1/2] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt Chris Wilson 2020-01-31 8:15 ` [Intel-gfx] [PATCH 2/2] drm/i915/selftests: Also wait for the scratch buffer to be bound Chris Wilson 2020-01-31 11:17 ` [Intel-gfx] [PATCH] " Chris Wilson 2020-01-31 14:26 ` Chris Wilson 2020-01-31 15:03 ` Mika Kuoppala 2020-01-31 10:18 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt Patchwork 2020-01-31 14:23 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt (rev2) Patchwork 2020-01-31 14:37 ` [Intel-gfx] [PATCH 1/2] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt Mika Kuoppala 2020-01-31 14:52 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt (rev2) Patchwork 2020-01-31 19:38 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/2] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt (rev3) Patchwork
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