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* [v2][PATCH 0/3] adding gamma state checker for CHV and i965
@ 2019-09-09 12:01 Swati Sharma
  2019-09-09 12:01 ` [v2][PATCH 1/3] drm/i915/display: Add gamma precision function for CHV Swati Sharma
                   ` (6 more replies)
  0 siblings, 7 replies; 9+ messages in thread
From: Swati Sharma @ 2019-09-09 12:01 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula, daniel.vetter, ankit.k.nautiyal

In this patch series, added state checker to validate gamma lut values
for cherryview and i965 platforms. It's extension of the
patch series https://patchwork.freedesktop.org/patch/328246/?series=58039
which enabled the basic infrastructure and state checker for 
few legacy platforms.

v2: Added last index rgb lut value from PIPEGCMAX to h/w blob [Jani]

Swati Sharma (3):
  drm/i915/display: Add gamma precision function for CHV
  drm/i915/display: Extract i965_read_luts()
  drm/i915/display: Extract chv_read_luts()

 drivers/gpu/drm/i915/display/intel_color.c | 118 +++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/i915_reg.h            |   7 ++
 2 files changed, 119 insertions(+), 6 deletions(-)

-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 9+ messages in thread
* [v2][PATCH 1/3] drm/i915/display: Add gamma precision function for CHV
  2019-09-09 12:01 [v2][PATCH 0/3] adding gamma state checker for CHV and i965 Swati Sharma
@ 2019-09-09 12:01 ` Swati Sharma
  2019-09-09 12:01 ` [v2][PATCH 2/3] drm/i915/display: Extract i965_read_luts() Swati Sharma
                   ` (5 subsequent siblings)
  6 siblings, 0 replies; 9+ messages in thread
From: Swati Sharma @ 2019-09-09 12:01 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula, daniel.vetter, ankit.k.nautiyal

intel_color_get_gamma_bit_precision() is extended for
cherryview by adding chv_gamma_precision(), i965 will use existing
i9xx_gamma_precision() func only.

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 25 +++++++++++++++++++------
 1 file changed, 19 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 6d641e1..4d9a568 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1400,6 +1400,14 @@ static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)
 	}
 }
 
+static int chv_gamma_precision(const struct intel_crtc_state *crtc_state)
+{
+	if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
+		return 10;
+	else
+		return i9xx_gamma_precision(crtc_state);
+}
+
 static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
 {
 	switch (crtc_state->gamma_mode) {
@@ -1421,12 +1429,17 @@ int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_stat
 	if (!crtc_state->gamma_enable)
 		return 0;
 
-	if (HAS_GMCH(dev_priv) && !IS_CHERRYVIEW(dev_priv))
-		return i9xx_gamma_precision(crtc_state);
-	else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
-		return glk_gamma_precision(crtc_state);
-	else if (IS_IRONLAKE(dev_priv))
-		return ilk_gamma_precision(crtc_state);
+	if (HAS_GMCH(dev_priv)) {
+		if (IS_CHERRYVIEW(dev_priv))
+			return chv_gamma_precision(crtc_state);
+		else
+			return i9xx_gamma_precision(crtc_state);
+	} else {
+		if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
+			return glk_gamma_precision(crtc_state);
+		else if (IS_IRONLAKE(dev_priv))
+			return ilk_gamma_precision(crtc_state);
+	}
 
 	return 0;
 }
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 9+ messages in thread
* [v2][PATCH 2/3] drm/i915/display: Extract i965_read_luts()
  2019-09-09 12:01 [v2][PATCH 0/3] adding gamma state checker for CHV and i965 Swati Sharma
  2019-09-09 12:01 ` [v2][PATCH 1/3] drm/i915/display: Add gamma precision function for CHV Swati Sharma
@ 2019-09-09 12:01 ` Swati Sharma
  2019-09-09 12:01 ` [v2][PATCH 3/3] drm/i915/display: Extract chv_read_luts() Swati Sharma
                   ` (4 subsequent siblings)
  6 siblings, 0 replies; 9+ messages in thread
From: Swati Sharma @ 2019-09-09 12:01 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula, daniel.vetter, ankit.k.nautiyal

For i965, add hw read out to create hw blob of gamma
lut values.

Review comments from old series:
https://patchwork.freedesktop.org/series/58039/

v4:  -No need to initialize *blob [Jani]
     -Removed right shifts [Jani]
     -Dropped dev local var [Jani]
v5:  -Returned blob instead of assigning it internally
      within the function [Ville]
     -Renamed i965_get_color_config() to i965_read_lut() [Ville]
     -Renamed i965_get_gamma_config_10p6() to i965_read_gamma_lut_10p6()
      [Ville]
v9:  -Typo and 80 character limit [Uma]
     -Made read func para as const [Ville, Uma]
     -Renamed i965_read_gamma_lut_10p6() to i965_read_lut_10p6() [Ville, Uma]
v10: -Swapped ldw and udw while creating hw blob [Jani]
     -Added last index rgb lut value from PIPEGCMAX to h/w blob [Jani]

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 50 ++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h            |  4 +++
 2 files changed, 54 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 4d9a568..765f858 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1570,6 +1570,55 @@ static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
 }
 
 static struct drm_property_blob *
+i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+	enum pipe pipe = crtc->pipe;
+	struct drm_property_blob *blob;
+	struct drm_color_lut *blob_data;
+	u32 i, val1, val2;
+
+	blob = drm_property_create_blob(&dev_priv->drm,
+					sizeof(struct drm_color_lut) * lut_size,
+					NULL);
+	if (IS_ERR(blob))
+		return NULL;
+
+	blob_data = blob->data;
+
+	for (i = 0; i < lut_size - 1; i++) {
+		val1 = I915_READ(PALETTE(pipe, 2 * i + 0));
+		val2 = I915_READ(PALETTE(pipe, 2 * i + 1));
+
+		blob_data[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val2) << 8 |
+						 REG_FIELD_GET(PALETTE_RED_MASK, val1);
+		blob_data[i].green = REG_FIELD_GET(PALETTE_GREEN_MASK, val2) << 8 |
+						   REG_FIELD_GET(PALETTE_GREEN_MASK, val1);
+		blob_data[i].blue = REG_FIELD_GET(PALETTE_BLUE_MASK, val2) << 8 |
+						  REG_FIELD_GET(PALETTE_BLUE_MASK, val1);
+	}
+
+	blob_data[i].red = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
+					 I915_READ(PIPEGCMAX(pipe, 0)));
+	blob_data[i].green = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
+					   I915_READ(PIPEGCMAX(pipe, 1)));
+	blob_data[i].blue = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
+					  I915_READ(PIPEGCMAX(pipe, 2)));
+
+	return blob;
+}
+
+static void i965_read_luts(struct intel_crtc_state *crtc_state)
+{
+	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
+		crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
+	else
+		crtc_state->base.gamma_lut = i965_read_lut_10p6(crtc_state);
+}
+
+static struct drm_property_blob *
 ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
@@ -1672,6 +1721,7 @@ void intel_color_init(struct intel_crtc *crtc)
 			dev_priv->display.color_check = i9xx_color_check;
 			dev_priv->display.color_commit = i9xx_color_commit;
 			dev_priv->display.load_luts = i965_load_luts;
+			dev_priv->display.read_luts = i965_read_luts;
 		} else {
 			dev_priv->display.color_check = i9xx_color_check;
 			dev_priv->display.color_commit = i9xx_color_commit;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 45ed96d..5ac8a4d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3558,6 +3558,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define _PALETTE_A		0xa000
 #define _PALETTE_B		0xa800
 #define _CHV_PALETTE_C		0xc000
+#define PALETTE_RED_MASK        REG_GENMASK(23, 16)
+#define PALETTE_GREEN_MASK      REG_GENMASK(15, 8)
+#define PALETTE_BLUE_MASK       REG_GENMASK(7, 0)
 #define PALETTE(pipe, i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
 				      _PICK((pipe), _PALETTE_A,		\
 					    _PALETTE_B, _CHV_PALETTE_C) + \
@@ -5760,6 +5763,7 @@ enum {
 
 #define  _PIPEAGCMAX           0x70010
 #define  _PIPEBGCMAX           0x71010
+#define PIPEGCMAX_RGB_MASK     REG_GENMASK(15, 0)
 #define PIPEGCMAX(pipe, i)     _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4)
 
 #define _PIPE_MISC_A			0x70030
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 9+ messages in thread
* [v2][PATCH 3/3] drm/i915/display: Extract chv_read_luts()
  2019-09-09 12:01 [v2][PATCH 0/3] adding gamma state checker for CHV and i965 Swati Sharma
  2019-09-09 12:01 ` [v2][PATCH 1/3] drm/i915/display: Add gamma precision function for CHV Swati Sharma
  2019-09-09 12:01 ` [v2][PATCH 2/3] drm/i915/display: Extract i965_read_luts() Swati Sharma
@ 2019-09-09 12:01 ` Swati Sharma
  2019-09-09 17:55 ` ✗ Fi.CI.CHECKPATCH: warning for adding gamma state checker for CHV and i965 (rev2) Patchwork
                   ` (3 subsequent siblings)
  6 siblings, 0 replies; 9+ messages in thread
From: Swati Sharma @ 2019-09-09 12:01 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula, daniel.vetter, ankit.k.nautiyal

For cherryview, add hw read out to create hw blob of gamma
lut values.

Review comments from previous series:
https://patchwork.freedesktop.org/patch/328252

v4: -No need to initialize *blob [Jani]
    -Removed right shifts [Jani]
    -Dropped dev local var [Jani]
v5: -Returned blob instead of assigning it internally within the
     function [Ville]
    -Renamed function cherryview_get_color_config() to chv_read_luts()
    -Renamed cherryview_get_gamma_config() to chv_read_cgm_gamma_lut()
     [Ville]
v9: -80 character limit [Uma]
    -Made read func para as const [Ville, Uma]
    -Renamed chv_read_cgm_gamma_lut() to chv_read_cgm_gamma_lut()
     [Ville, Uma]

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 43 ++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h            |  3 +++
 2 files changed, 46 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 765f858..318308d 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1619,6 +1619,48 @@ static void i965_read_luts(struct intel_crtc_state *crtc_state)
 }
 
 static struct drm_property_blob *
+chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+	enum pipe pipe = crtc->pipe;
+	struct drm_property_blob *blob;
+	struct drm_color_lut *blob_data;
+	u32 i, val;
+
+	blob = drm_property_create_blob(&dev_priv->drm,
+					sizeof(struct drm_color_lut) * lut_size,
+					NULL);
+	if (IS_ERR(blob))
+		return NULL;
+
+	blob_data = blob->data;
+
+	for (i = 0; i < lut_size; i++) {
+		val = I915_READ(CGM_PIPE_GAMMA(pipe, i, 0));
+		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
+							  CGM_PIPE_GAMMA_GREEN_MASK, val), 10);
+		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
+							 CGM_PIPE_GAMMA_BLUE_MASK, val), 10);
+
+		val = I915_READ(CGM_PIPE_GAMMA(pipe, i, 1));
+		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
+							CGM_PIPE_GAMMA_RED_MASK, val), 10);
+	}
+
+	return blob;
+}
+
+static void chv_read_luts(struct intel_crtc_state *crtc_state)
+{
+	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
+		crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
+	else
+		crtc_state->base.gamma_lut = chv_read_cgm_lut(crtc_state);
+}
+
+static struct drm_property_blob *
 ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
@@ -1717,6 +1759,7 @@ void intel_color_init(struct intel_crtc *crtc)
 			dev_priv->display.color_check = chv_color_check;
 			dev_priv->display.color_commit = i9xx_color_commit;
 			dev_priv->display.load_luts = chv_load_luts;
+			dev_priv->display.read_luts = chv_read_luts;
 		} else if (INTEL_GEN(dev_priv) >= 4) {
 			dev_priv->display.color_check = i9xx_color_check;
 			dev_priv->display.color_commit = i9xx_color_commit;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5ac8a4d..0241c9d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10410,6 +10410,9 @@ enum skl_power_gate {
 #define   CGM_PIPE_MODE_GAMMA	(1 << 2)
 #define   CGM_PIPE_MODE_CSC	(1 << 1)
 #define   CGM_PIPE_MODE_DEGAMMA	(1 << 0)
+#define   CGM_PIPE_GAMMA_RED_MASK   REG_GENMASK(9, 0)
+#define   CGM_PIPE_GAMMA_GREEN_MASK REG_GENMASK(25, 16)
+#define   CGM_PIPE_GAMMA_BLUE_MASK  REG_GENMASK(9, 0)
 
 #define _CGM_PIPE_B_CSC_COEFF01	(VLV_DISPLAY_BASE + 0x69900)
 #define _CGM_PIPE_B_CSC_COEFF23	(VLV_DISPLAY_BASE + 0x69904)
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 9+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for adding gamma state checker for CHV and i965 (rev2)
  2019-09-09 12:01 [v2][PATCH 0/3] adding gamma state checker for CHV and i965 Swati Sharma
                   ` (2 preceding siblings ...)
  2019-09-09 12:01 ` [v2][PATCH 3/3] drm/i915/display: Extract chv_read_luts() Swati Sharma
@ 2019-09-09 17:55 ` Patchwork
  2019-09-09 18:19 ` ✓ Fi.CI.BAT: success " Patchwork
                   ` (2 subsequent siblings)
  6 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2019-09-09 17:55 UTC (permalink / raw)
  To: Sharma, Swati2; +Cc: intel-gfx

== Series Details ==

Series: adding gamma state checker for CHV and i965 (rev2)
URL   : https://patchwork.freedesktop.org/series/66297/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
d02e018c92fe drm/i915/display: Add gamma precision function for CHV
73751624de48 drm/i915/display: Extract i965_read_luts()
-:22: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#22: 
     -Renamed i965_read_gamma_lut_10p6() to i965_read_lut_10p6() [Ville, Uma]

total: 0 errors, 1 warnings, 0 checks, 78 lines checked
1eeae34e288a drm/i915/display: Extract chv_read_luts()
-:57: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#57: FILE: drivers/gpu/drm/i915/display/intel_color.c:1642:
+		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:59: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#59: FILE: drivers/gpu/drm/i915/display/intel_color.c:1644:
+		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(

-:63: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#63: FILE: drivers/gpu/drm/i915/display/intel_color.c:1648:
+		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(

total: 0 errors, 0 warnings, 3 checks, 64 lines checked

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 9+ messages in thread
* ✓ Fi.CI.BAT: success for adding gamma state checker for CHV and i965 (rev2)
  2019-09-09 12:01 [v2][PATCH 0/3] adding gamma state checker for CHV and i965 Swati Sharma
                   ` (3 preceding siblings ...)
  2019-09-09 17:55 ` ✗ Fi.CI.CHECKPATCH: warning for adding gamma state checker for CHV and i965 (rev2) Patchwork
@ 2019-09-09 18:19 ` Patchwork
  2019-09-10  1:53 ` ✓ Fi.CI.IGT: " Patchwork
  2019-09-10 10:27 ` [v2][PATCH 0/3] adding gamma state checker for CHV and i965 Jani Nikula
  6 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2019-09-09 18:19 UTC (permalink / raw)
  To: Sharma, Swati2; +Cc: intel-gfx

== Series Details ==

Series: adding gamma state checker for CHV and i965 (rev2)
URL   : https://patchwork.freedesktop.org/series/66297/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6854 -> Patchwork_14328
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14328/

Known issues
------------

  Here are the changes found in Patchwork_14328 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_create@basic-files:
    - fi-bxt-dsi:         [PASS][1] -> [INCOMPLETE][2] ([fdo#103927])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6854/fi-bxt-dsi/igt@gem_ctx_create@basic-files.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14328/fi-bxt-dsi/igt@gem_ctx_create@basic-files.html

  * igt@i915_selftest@live_workarounds:
    - fi-bsw-kefka:       [PASS][3] -> [DMESG-WARN][4] ([fdo#111373])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6854/fi-bsw-kefka/igt@i915_selftest@live_workarounds.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14328/fi-bsw-kefka/igt@i915_selftest@live_workarounds.html

  
#### Possible fixes ####

  * igt@gem_ctx_switch@legacy-render:
    - fi-icl-u2:          [INCOMPLETE][5] ([fdo#107713] / [fdo#111381]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6854/fi-icl-u2/igt@gem_ctx_switch@legacy-render.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14328/fi-icl-u2/igt@gem_ctx_switch@legacy-render.html

  
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#111373]: https://bugs.freedesktop.org/show_bug.cgi?id=111373
  [fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381


Participating hosts (51 -> 46)
------------------------------

  Additional (3): fi-icl-dsi fi-cfl-guc fi-icl-u3 
  Missing    (8): fi-ilk-m540 fi-hsw-4200u fi-skl-6770hq fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6854 -> Patchwork_14328

  CI-20190529: 20190529
  CI_DRM_6854: 5a70800ed2837e2d35a331e2cfd43a55df58c4fc @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5176: 0102dcf4e2e8b357b59173fe1ff78069148080c6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14328: 1eeae34e288a81976191a8c4b6bd0f877ddcb1f1 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

1eeae34e288a drm/i915/display: Extract chv_read_luts()
73751624de48 drm/i915/display: Extract i965_read_luts()
d02e018c92fe drm/i915/display: Add gamma precision function for CHV

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14328/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 9+ messages in thread
* ✓ Fi.CI.IGT: success for adding gamma state checker for CHV and i965 (rev2)
  2019-09-09 12:01 [v2][PATCH 0/3] adding gamma state checker for CHV and i965 Swati Sharma
                   ` (4 preceding siblings ...)
  2019-09-09 18:19 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-09-10  1:53 ` Patchwork
  2019-09-10 10:27 ` [v2][PATCH 0/3] adding gamma state checker for CHV and i965 Jani Nikula
  6 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2019-09-10  1:53 UTC (permalink / raw)
  To: Sharma, Swati2; +Cc: intel-gfx

== Series Details ==

Series: adding gamma state checker for CHV and i965 (rev2)
URL   : https://patchwork.freedesktop.org/series/66297/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6854_full -> Patchwork_14328_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_14328_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_eio@in-flight-contexts-10ms:
    - shard-skl:          [PASS][1] -> [DMESG-WARN][2] ([fdo#106107])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6854/shard-skl1/igt@gem_eio@in-flight-contexts-10ms.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14328/shard-skl2/igt@gem_eio@in-flight-contexts-10ms.html

  * igt@gem_exec_schedule@deep-bsd:
    - shard-iclb:         [PASS][3] -> [SKIP][4] ([fdo#111325]) +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6854/shard-iclb6/igt@gem_exec_schedule@deep-bsd.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14328/shard-iclb2/igt@gem_exec_schedule@deep-bsd.html

  * igt@gem_exec_schedule@preempt-queue-chain-bsd2:
    - shard-iclb:         [PASS][5] -> [SKIP][6] ([fdo#109276]) +11 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6854/shard-iclb4/igt@gem_exec_schedule@preempt-queue-chain-bsd2.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14328/shard-iclb3/igt@gem_exec_schedule@preempt-queue-chain-bsd2.html

  * igt@gem_softpin@noreloc-s3:
    - shard-skl:          [PASS][7] -> [INCOMPLETE][8] ([fdo#104108])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6854/shard-skl10/igt@gem_softpin@noreloc-s3.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14328/shard-skl9/igt@gem_softpin@noreloc-s3.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-apl:          [PASS][9] -> [DMESG-WARN][10] ([fdo#108566]) +2 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6854/shard-apl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14328/shard-apl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_cursor_legacy@all-pipes-forked-bo:
    - shard-iclb:         [PASS][11] -> [INCOMPLETE][12] ([fdo#107713])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6854/shard-iclb2/igt@kms_cursor_legacy@all-pipes-forked-bo.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14328/shard-iclb7/igt@kms_cursor_legacy@all-pipes-forked-bo.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite:
    - shard-iclb:         [PASS][13] -> [FAIL][14] ([fdo#103167]) +2 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6854/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14328/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][15] -> [FAIL][16] ([fdo#108145] / [fdo#110403])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6854/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14328/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_psr@no_drrs:
    - shard-iclb:         [PASS][17] -> [FAIL][18] ([fdo#108341])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6854/shard-iclb7/igt@kms_psr@no_drrs.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14328/shard-iclb1/igt@kms_psr@no_drrs.html

  * igt@kms_psr@psr2_sprite_plane_move:
    - shard-iclb:         [PASS][19] -> [SKIP][20] ([fdo#109441])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6854/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14328/shard-iclb7/igt@kms_psr@psr2_sprite_plane_move.html

  
#### Possible fixes ####

  * igt@gem_exec_async@concurrent-writes-bsd:
    - shard-iclb:         [SKIP][21] ([fdo#111325]) -> [PASS][22] +2 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6854/shard-iclb4/igt@gem_exec_async@concurrent-writes-bsd.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14328/shard-iclb3/igt@gem_exec_async@concurrent-writes-bsd.html

  * igt@gem_exec_balancer@smoke:
    - shard-iclb:         [SKIP][23] ([fdo#110854]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6854/shard-iclb6/igt@gem_exec_balancer@smoke.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14328/shard-iclb2/igt@gem_exec_balancer@smoke.html

  * igt@gem_exec_schedule@preempt-contexts-bsd2:
    - shard-iclb:         [SKIP][25] ([fdo#109276]) -> [PASS][26] +6 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6854/shard-iclb8/igt@gem_exec_schedule@preempt-contexts-bsd2.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14328/shard-iclb2/igt@gem_exec_schedule@preempt-contexts-bsd2.html

  * igt@gem_fence_thrash@bo-write-verify-threaded-x:
    - shard-apl:          [INCOMPLETE][27] ([fdo#103927]) -> [PASS][28] +1 similar issue
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6854/shard-apl4/igt@gem_fence_thrash@bo-write-verify-threaded-x.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14328/shard-apl7/igt@gem_fence_thrash@bo-write-verify-threaded-x.html

  * igt@i915_suspend@sysfs-reader:
    - shard-apl:          [DMESG-WARN][29] ([fdo#108566]) -> [PASS][30] +5 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6854/shard-apl8/igt@i915_suspend@sysfs-reader.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14328/shard-apl8/igt@i915_suspend@sysfs-reader.html

  * igt@kms_cursor_crc@pipe-c-cursor-256x85-offscreen:
    - shard-iclb:         [INCOMPLETE][31] ([fdo#107713]) -> [PASS][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6854/shard-iclb7/igt@kms_cursor_crc@pipe-c-cursor-256x85-offscreen.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14328/shard-iclb3/igt@kms_cursor_crc@pipe-c-cursor-256x85-offscreen.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-skl:          [FAIL][33] ([fdo#105363]) -> [PASS][34] +1 similar issue
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6854/shard-skl6/igt@kms_flip@flip-vs-expired-vblank.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14328/shard-skl10/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-snb:          [INCOMPLETE][35] ([fdo#105411]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6854/shard-snb1/igt@kms_flip@flip-vs-suspend-interruptible.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14328/shard-snb6/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
    - shard-iclb:         [FAIL][37] ([fdo#103167]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6854/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14328/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff:
    - shard-skl:          [FAIL][39] ([fdo#103167]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6854/shard-skl1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14328/shard-skl6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
    - shard-kbl:          [INCOMPLETE][41] ([fdo#103665]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6854/shard-kbl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14328/shard-kbl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html

  * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
    - shard-skl:          [FAIL][43] ([fdo#108145]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6854/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14328/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html

  * igt@kms_psr@psr2_basic:
    - shard-iclb:         [SKIP][45] ([fdo#109441]) -> [PASS][46] +1 similar issue
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6854/shard-iclb8/igt@kms_psr@psr2_basic.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14328/shard-iclb2/igt@kms_psr@psr2_basic.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-90:
    - shard-iclb:         [INCOMPLETE][47] ([fdo#107713] / [fdo#110026] / [fdo#110040 ]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6854/shard-iclb1/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14328/shard-iclb7/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html

  * igt@kms_setmode@basic:
    - shard-apl:          [FAIL][49] ([fdo#99912]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6854/shard-apl8/igt@kms_setmode@basic.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14328/shard-apl4/igt@kms_setmode@basic.html

  * igt@perf@blocking:
    - shard-skl:          [FAIL][51] ([fdo#110728]) -> [PASS][52] +1 similar issue
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6854/shard-skl1/igt@perf@blocking.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14328/shard-skl4/igt@perf@blocking.html

  
#### Warnings ####

  * igt@gem_ctx_isolation@vcs1-nonpriv:
    - shard-iclb:         [FAIL][53] ([fdo#111329]) -> [SKIP][54] ([fdo#109276])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6854/shard-iclb4/igt@gem_ctx_isolation@vcs1-nonpriv.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14328/shard-iclb3/igt@gem_ctx_isolation@vcs1-nonpriv.html

  
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
  [fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#110026]: https://bugs.freedesktop.org/show_bug.cgi?id=110026
  [fdo#110040 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110040 
  [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
  [fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
  [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
  [fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
  [fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6854 -> Patchwork_14328

  CI-20190529: 20190529
  CI_DRM_6854: 5a70800ed2837e2d35a331e2cfd43a55df58c4fc @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5176: 0102dcf4e2e8b357b59173fe1ff78069148080c6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14328: 1eeae34e288a81976191a8c4b6bd0f877ddcb1f1 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14328/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 9+ messages in thread
* Re: [v2][PATCH 0/3] adding gamma state checker for CHV and i965
  2019-09-09 12:01 [v2][PATCH 0/3] adding gamma state checker for CHV and i965 Swati Sharma
                   ` (5 preceding siblings ...)
  2019-09-10  1:53 ` ✓ Fi.CI.IGT: " Patchwork
@ 2019-09-10 10:27 ` Jani Nikula
  2019-09-10 10:53   ` Sharma, Swati2
  6 siblings, 1 reply; 9+ messages in thread
From: Jani Nikula @ 2019-09-10 10:27 UTC (permalink / raw)
  To: Swati Sharma, intel-gfx; +Cc: daniel.vetter, ankit.k.nautiyal

On Mon, 09 Sep 2019, Swati Sharma <swati2.sharma@intel.com> wrote:
> In this patch series, added state checker to validate gamma lut values
> for cherryview and i965 platforms. It's extension of the
> patch series https://patchwork.freedesktop.org/patch/328246/?series=58039
> which enabled the basic infrastructure and state checker for 
> few legacy platforms.
>
> v2: Added last index rgb lut value from PIPEGCMAX to h/w blob [Jani]

Pushed, thanks for the patches.

BR,
Jani.


>
> Swati Sharma (3):
>   drm/i915/display: Add gamma precision function for CHV
>   drm/i915/display: Extract i965_read_luts()
>   drm/i915/display: Extract chv_read_luts()
>
>  drivers/gpu/drm/i915/display/intel_color.c | 118 +++++++++++++++++++++++++++--
>  drivers/gpu/drm/i915/i915_reg.h            |   7 ++
>  2 files changed, 119 insertions(+), 6 deletions(-)

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 9+ messages in thread
* Re: [v2][PATCH 0/3] adding gamma state checker for CHV and i965
  2019-09-10 10:27 ` [v2][PATCH 0/3] adding gamma state checker for CHV and i965 Jani Nikula
@ 2019-09-10 10:53   ` Sharma, Swati2
  0 siblings, 0 replies; 9+ messages in thread
From: Sharma, Swati2 @ 2019-09-10 10:53 UTC (permalink / raw)
  To: Jani Nikula, intel-gfx; +Cc: daniel.vetter, ankit.k.nautiyal

On 10-Sep-19 3:57 PM, Jani Nikula wrote:
> On Mon, 09 Sep 2019, Swati Sharma <swati2.sharma@intel.com> wrote:
>> In this patch series, added state checker to validate gamma lut values
>> for cherryview and i965 platforms. It's extension of the
>> patch series https://patchwork.freedesktop.org/patch/328246/?series=58039
>> which enabled the basic infrastructure and state checker for
>> few legacy platforms.
>>
>> v2: Added last index rgb lut value from PIPEGCMAX to h/w blob [Jani]
> 
> Pushed, thanks for the patches.

Thanks Jani!
> 
> BR,
> Jani.
> 
> 
>>
>> Swati Sharma (3):
>>    drm/i915/display: Add gamma precision function for CHV
>>    drm/i915/display: Extract i965_read_luts()
>>    drm/i915/display: Extract chv_read_luts()
>>
>>   drivers/gpu/drm/i915/display/intel_color.c | 118 +++++++++++++++++++++++++++--
>>   drivers/gpu/drm/i915/i915_reg.h            |   7 ++
>>   2 files changed, 119 insertions(+), 6 deletions(-)
> 


-- 
~Swati Sharma
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 9+ messages in thread
end of thread, other threads:[~2019-09-10 10:54 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-09-09 12:01 [v2][PATCH 0/3] adding gamma state checker for CHV and i965 Swati Sharma
2019-09-09 12:01 ` [v2][PATCH 1/3] drm/i915/display: Add gamma precision function for CHV Swati Sharma
2019-09-09 12:01 ` [v2][PATCH 2/3] drm/i915/display: Extract i965_read_luts() Swati Sharma
2019-09-09 12:01 ` [v2][PATCH 3/3] drm/i915/display: Extract chv_read_luts() Swati Sharma
2019-09-09 17:55 ` ✗ Fi.CI.CHECKPATCH: warning for adding gamma state checker for CHV and i965 (rev2) Patchwork
2019-09-09 18:19 ` ✓ Fi.CI.BAT: success " Patchwork
2019-09-10  1:53 ` ✓ Fi.CI.IGT: " Patchwork
2019-09-10 10:27 ` [v2][PATCH 0/3] adding gamma state checker for CHV and i965 Jani Nikula
2019-09-10 10:53   ` Sharma, Swati2

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