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From: Yoshinori Sato <ysato@users.sourceforge.jp>
To: "Alex Bennée" <alex.bennee@linaro.org>
Cc: qemu-devel@nongnu.org, peter.maydell@linaro.org,
	richard.henderson@linaro.org
Subject: Re: [Qemu-devel] [PATCH RFC v8 12/12] hw/registerfields.h: Add 8bit and 16bit register macros.
Date: Mon, 06 May 2019 01:07:38 +0900	[thread overview]
Message-ID: <87muk051h1.wl-ysato@users.sourceforge.jp> (raw)
In-Reply-To: <87muk34kym.fsf@zen.linaroharston>

On Sat, 04 May 2019 00:27:29 +0900,
Alex Bennée wrote:
> 
> 
> Yoshinori Sato <ysato@users.sourceforge.jp> writes:
> 
> > Some RX peripheral using 8bit and 16bit registers.
> > Added 8bit and 16bit APIs.
> 
> Doesn't this mean the build breaks at some point? Features used by other
> patches should be introduced first so the build remains bisectable.

Hmm, It changes only added new macros.
So don't broken this changes.

> >
> > Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> > ---
> >  include/hw/registerfields.h | 28 +++++++++++++++++++++++++++-
> >  1 file changed, 27 insertions(+), 1 deletion(-)
> >
> > diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h
> > index 2659a58737..51bfd0cf67 100644
> > --- a/include/hw/registerfields.h
> > +++ b/include/hw/registerfields.h
> > @@ -22,6 +22,14 @@
> >      enum { A_ ## reg = (addr) };                                          \
> >      enum { R_ ## reg = (addr) / 4 };
> >
> > +#define REG8(reg, addr)                                                  \
> > +    enum { A_ ## reg = (addr) };                                          \
> > +    enum { R_ ## reg = (addr) };
> > +
> > +#define REG16(reg, addr)                                                  \
> > +    enum { A_ ## reg = (addr) };                                          \
> > +    enum { R_ ## reg = (addr) / 2 };
> > +
> >  /* Define SHIFT, LENGTH and MASK constants for a field within a register */
> >
> >  /* This macro will define R_FOO_BAR_MASK, R_FOO_BAR_SHIFT and R_FOO_BAR_LENGTH
> > @@ -40,6 +48,8 @@
> >  #define FIELD_EX64(storage, reg, field)                                   \
> >      extract64((storage), R_ ## reg ## _ ## field ## _SHIFT,               \
> >                R_ ## reg ## _ ## field ## _LENGTH)
> > +#define FIELD_EX8  FIELD_EX32
> > +#define FIELD_EX16 FIELD_EX32
> 
> Hmm maybe we should be defining extract16/extract8 in bitops so things
> are a) properly types and b) bounds checked to catch errors.

I think so.
I will added extrat8 and extract16 in bitops.h.

> >
> >  /* Extract a field from an array of registers */
> >  #define ARRAY_FIELD_EX32(regs, reg, field)                                \
> > @@ -49,6 +59,22 @@
> >   * Assigning values larger then the target field will result in
> >   * compilation warnings.
> >   */
> > +#define FIELD_DP8(storage, reg, field, val) ({                            \
> > +    struct {                                                              \
> > +        unsigned int v:R_ ## reg ## _ ## field ## _LENGTH;                \
> > +    } v = { .v = val };                                                   \
> > +    uint8_t d;                                                            \
> > +    d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT,           \
> > +                  R_ ## reg ## _ ## field ## _LENGTH, v.v);               \
> > +    d; })
> > +#define FIELD_DP16(storage, reg, field, val) ({                           \
> > +    struct {                                                              \
> > +        unsigned int v:R_ ## reg ## _ ## field ## _LENGTH;                \
> > +    } v = { .v = val };                                                   \
> > +    uint16_t d;                                                           \
> > +    d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT,           \
> > +                  R_ ## reg ## _ ## field ## _LENGTH, v.v);               \
> > +    d; })
> >  #define FIELD_DP32(storage, reg, field, val) ({                           \
> >      struct {                                                              \
> >          unsigned int v:R_ ## reg ## _ ## field ## _LENGTH;                \
> > @@ -57,7 +83,7 @@
> >      d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT,           \
> >                    R_ ## reg ## _ ## field ## _LENGTH, v.v);               \
> >      d; })
> > -#define FIELD_DP64(storage, reg, field, val) ({                           \
> > +#define FIELD_DP64(storage, reg, field, val) ({                         \
> >      struct {                                                              \
> >          unsigned int v:R_ ## reg ## _ ## field ## _LENGTH;                \
> >      } v = { .v = val };                                                   \
> 
> 
> --
> Alex Bennée
> 

-- 
Yosinori Sato

WARNING: multiple messages have this Message-ID (diff)
From: Yoshinori Sato <ysato@users.sourceforge.jp>
To: "Alex Bennée" <alex.bennee@linaro.org>
Cc: peter.maydell@linaro.org, richard.henderson@linaro.org,
	qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH RFC v8 12/12] hw/registerfields.h: Add 8bit and 16bit register macros.
Date: Mon, 06 May 2019 01:07:38 +0900	[thread overview]
Message-ID: <87muk051h1.wl-ysato@users.sourceforge.jp> (raw)
Message-ID: <20190505160738.gYd70c751pRkseltaDAi2_77guxCamJXS5oiZFuHjhs@z> (raw)
In-Reply-To: <87muk34kym.fsf@zen.linaroharston>

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="UTF-8", Size: 4481 bytes --]

On Sat, 04 May 2019 00:27:29 +0900,
Alex Bennée wrote:
> 
> 
> Yoshinori Sato <ysato@users.sourceforge.jp> writes:
> 
> > Some RX peripheral using 8bit and 16bit registers.
> > Added 8bit and 16bit APIs.
> 
> Doesn't this mean the build breaks at some point? Features used by other
> patches should be introduced first so the build remains bisectable.

Hmm, It changes only added new macros.
So don't broken this changes.

> >
> > Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> > ---
> >  include/hw/registerfields.h | 28 +++++++++++++++++++++++++++-
> >  1 file changed, 27 insertions(+), 1 deletion(-)
> >
> > diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h
> > index 2659a58737..51bfd0cf67 100644
> > --- a/include/hw/registerfields.h
> > +++ b/include/hw/registerfields.h
> > @@ -22,6 +22,14 @@
> >      enum { A_ ## reg = (addr) };                                          \
> >      enum { R_ ## reg = (addr) / 4 };
> >
> > +#define REG8(reg, addr)                                                  \
> > +    enum { A_ ## reg = (addr) };                                          \
> > +    enum { R_ ## reg = (addr) };
> > +
> > +#define REG16(reg, addr)                                                  \
> > +    enum { A_ ## reg = (addr) };                                          \
> > +    enum { R_ ## reg = (addr) / 2 };
> > +
> >  /* Define SHIFT, LENGTH and MASK constants for a field within a register */
> >
> >  /* This macro will define R_FOO_BAR_MASK, R_FOO_BAR_SHIFT and R_FOO_BAR_LENGTH
> > @@ -40,6 +48,8 @@
> >  #define FIELD_EX64(storage, reg, field)                                   \
> >      extract64((storage), R_ ## reg ## _ ## field ## _SHIFT,               \
> >                R_ ## reg ## _ ## field ## _LENGTH)
> > +#define FIELD_EX8  FIELD_EX32
> > +#define FIELD_EX16 FIELD_EX32
> 
> Hmm maybe we should be defining extract16/extract8 in bitops so things
> are a) properly types and b) bounds checked to catch errors.

I think so.
I will added extrat8 and extract16 in bitops.h.

> >
> >  /* Extract a field from an array of registers */
> >  #define ARRAY_FIELD_EX32(regs, reg, field)                                \
> > @@ -49,6 +59,22 @@
> >   * Assigning values larger then the target field will result in
> >   * compilation warnings.
> >   */
> > +#define FIELD_DP8(storage, reg, field, val) ({                            \
> > +    struct {                                                              \
> > +        unsigned int v:R_ ## reg ## _ ## field ## _LENGTH;                \
> > +    } v = { .v = val };                                                   \
> > +    uint8_t d;                                                            \
> > +    d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT,           \
> > +                  R_ ## reg ## _ ## field ## _LENGTH, v.v);               \
> > +    d; })
> > +#define FIELD_DP16(storage, reg, field, val) ({                           \
> > +    struct {                                                              \
> > +        unsigned int v:R_ ## reg ## _ ## field ## _LENGTH;                \
> > +    } v = { .v = val };                                                   \
> > +    uint16_t d;                                                           \
> > +    d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT,           \
> > +                  R_ ## reg ## _ ## field ## _LENGTH, v.v);               \
> > +    d; })
> >  #define FIELD_DP32(storage, reg, field, val) ({                           \
> >      struct {                                                              \
> >          unsigned int v:R_ ## reg ## _ ## field ## _LENGTH;                \
> > @@ -57,7 +83,7 @@
> >      d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT,           \
> >                    R_ ## reg ## _ ## field ## _LENGTH, v.v);               \
> >      d; })
> > -#define FIELD_DP64(storage, reg, field, val) ({                           \
> > +#define FIELD_DP64(storage, reg, field, val) ({                         \
> >      struct {                                                              \
> >          unsigned int v:R_ ## reg ## _ ## field ## _LENGTH;                \
> >      } v = { .v = val };                                                   \
> 
> 
> --
> Alex Bennée
> 

-- 
Yosinori Sato


  parent reply	other threads:[~2019-05-05 16:07 UTC|newest]

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-02 14:33 [Qemu-devel] [PATCH RFC v8 00/12] Add RX archtecture support Yoshinori Sato
2019-05-02 14:33 ` Yoshinori Sato
2019-05-02 14:33 ` [Qemu-devel] [PATCH RFC v8 01/12] target/rx: TCG translation Yoshinori Sato
2019-05-02 14:33   ` Yoshinori Sato
2019-05-03 18:43   ` Richard Henderson
2019-05-05 16:07     ` Yoshinori Sato
2019-05-05 16:07       ` Yoshinori Sato
2019-05-02 14:33 ` [Qemu-devel] [PATCH RFC v8 02/12] target/rx: TCG helper Yoshinori Sato
2019-05-02 14:33   ` Yoshinori Sato
2019-05-02 14:34 ` [Qemu-devel] [PATCH RFC v8 03/12] target/rx: CPU definition Yoshinori Sato
2019-05-02 14:34   ` Yoshinori Sato
2019-05-03 15:45   ` Alex Bennée
2019-05-02 14:34 ` [Qemu-devel] [PATCH RFC v8 04/12] target/rx: RX disassembler Yoshinori Sato
2019-05-02 14:34   ` Yoshinori Sato
2019-05-03 15:54   ` Alex Bennée
2019-05-03 18:37   ` Richard Henderson
2019-05-02 14:34 ` [Qemu-devel] [PATCH RFC v8 05/12] target/rx: Miscellaneous files Yoshinori Sato
2019-05-02 14:34   ` Yoshinori Sato
2019-05-03 16:06   ` Alex Bennée
2019-05-05 16:06     ` Yoshinori Sato
2019-05-05 16:06       ` Yoshinori Sato
2019-05-02 14:34 ` [Qemu-devel] [PATCH RFC v8 06/12] hw/intc: RX62N interrupt controller (ICUa) Yoshinori Sato
2019-05-02 14:34   ` Yoshinori Sato
2019-05-03 15:01   ` Alex Bennée
2019-05-03 15:50   ` Alex Bennée
2019-05-02 14:34 ` [Qemu-devel] [PATCH RFC v8 07/12] hw/timer: RX62N internal timer modules Yoshinori Sato
2019-05-02 14:34   ` Yoshinori Sato
2019-05-03 15:20   ` Alex Bennée
2019-05-05 16:06     ` Yoshinori Sato
2019-05-05 16:06       ` Yoshinori Sato
2019-05-02 14:34 ` [Qemu-devel] [PATCH RFC v8 08/12] hw/char: RX62N serical communication interface (SCI) Yoshinori Sato
2019-05-02 14:34   ` Yoshinori Sato
2019-05-03 15:22   ` Alex Bennée
2019-05-05 16:07     ` Yoshinori Sato
2019-05-05 16:07       ` Yoshinori Sato
2019-05-02 14:34 ` [Qemu-devel] [PATCH RFC v8 09/12] hw/rx: RX Target hardware definition Yoshinori Sato
2019-05-02 14:34   ` Yoshinori Sato
2019-05-03 15:38   ` Alex Bennée
2019-05-05 16:07     ` Yoshinori Sato
2019-05-05 16:07       ` Yoshinori Sato
2019-05-02 14:34 ` [Qemu-devel] [PATCH RFC v8 10/12] Add rx-softmmu Yoshinori Sato
2019-05-02 14:34   ` Yoshinori Sato
2019-05-02 14:34 ` [Qemu-devel] [PATCH RFC v8 11/12] MAINTAINERS: Add RX Yoshinori Sato
2019-05-02 14:34   ` Yoshinori Sato
2019-05-02 14:34 ` [Qemu-devel] [PATCH RFC v8 12/12] hw/registerfields.h: Add 8bit and 16bit register macros Yoshinori Sato
2019-05-02 14:34   ` Yoshinori Sato
2019-05-03 15:27   ` Alex Bennée
2019-05-03 18:39     ` Richard Henderson
2019-05-05 21:18       ` Alex Bennée
2019-05-05 21:18         ` Alex Bennée
2019-05-05 16:07     ` Yoshinori Sato [this message]
2019-05-05 16:07       ` Yoshinori Sato
2019-05-03 16:11 ` [Qemu-devel] [PATCH RFC v8 00/12] Add RX archtecture support Alex Bennée
2019-05-05 16:07   ` Yoshinori Sato
2019-05-05 16:07     ` Yoshinori Sato

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