* [PATCH] drm/i915: Force RC6 restore after system resume and reset
@ 2016-08-24 9:27 Chris Wilson
2016-08-24 12:49 ` Mika Kuoppala
0 siblings, 1 reply; 2+ messages in thread
From: Chris Wilson @ 2016-08-24 9:27 UTC (permalink / raw)
To: intel-gfx; +Cc: Mika Kuoppala
In order for the RC6 autoenable worker to take any action, RC6 first
must be disabled. Upon resume or reset, the sw state may be stale and so
we require a forced restore.
Fixes: b7137e0cf1e5 ("drm/i915: Defer enabling rc6 til after we submit...")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5a7c0c2e57d8..fc9273215286 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1560,6 +1560,7 @@ static int i915_drm_resume(struct drm_device *dev)
int ret;
disable_rpm_wakeref_asserts(dev_priv);
+ intel_sanitize_gt_powersave(dev_priv);
ret = i915_ggtt_enable_hw(dev_priv);
if (ret)
@@ -1809,6 +1810,7 @@ int i915_reset(struct drm_i915_private *dev_priv)
* previous concerns that it doesn't respond well to some forms
* of re-init after reset.
*/
+ intel_sanitize_gt_powersave(dev_priv);
intel_autoenable_gt_powersave(dev_priv);
return 0;
--
2.9.3
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^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] drm/i915: Force RC6 restore after system resume and reset
2016-08-24 9:27 [PATCH] drm/i915: Force RC6 restore after system resume and reset Chris Wilson
@ 2016-08-24 12:49 ` Mika Kuoppala
0 siblings, 0 replies; 2+ messages in thread
From: Mika Kuoppala @ 2016-08-24 12:49 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
Chris Wilson <chris@chris-wilson.co.uk> writes:
> In order for the RC6 autoenable worker to take any action, RC6 first
> must be disabled. Upon resume or reset, the sw state may be stale and so
> we require a forced restore.
>
> Fixes: b7137e0cf1e5 ("drm/i915: Defer enabling rc6 til after we submit...")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Reading the code it stood out that we could get rid of sanitize
completely and always disable before calling autoenable gt powersave.
But lets not take too big steps,
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 5a7c0c2e57d8..fc9273215286 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1560,6 +1560,7 @@ static int i915_drm_resume(struct drm_device *dev)
> int ret;
>
> disable_rpm_wakeref_asserts(dev_priv);
> + intel_sanitize_gt_powersave(dev_priv);
>
> ret = i915_ggtt_enable_hw(dev_priv);
> if (ret)
> @@ -1809,6 +1810,7 @@ int i915_reset(struct drm_i915_private *dev_priv)
> * previous concerns that it doesn't respond well to some forms
> * of re-init after reset.
> */
> + intel_sanitize_gt_powersave(dev_priv);
> intel_autoenable_gt_powersave(dev_priv);
>
> return 0;
> --
> 2.9.3
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2016-08-24 12:49 ` Mika Kuoppala
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