[Intel-gfx] [PATCH 0/7] Update GGTT with MI_UPDATE_GTT on MTL

[Intel-gfx] [PATCH 0/7] Update GGTT with MI_UPDATE_GTT on MTL

[Nirmoy Das]

Implement a way to update GGTT using MI_UPDATE_GTT command 
when possible for MTL as a suggested work around for HW bugs,
Wa_13010847436 and Wa_14019519902.

v2: Fix lockdep warning related to GT wakeref vs 
    blitter engine wakeref.

v3: Rearrange patches/diffs to fix code mixups(Andi)

v4: fix ce leak(Oak)

Test-with: 20230914201809.1804-1-nirmoy.das@intel.com

Chris Wilson (1):
  drm/i915: Lift runtime-pm acquire callbacks out of intel_wakeref.mutex

Nirmoy Das (6):
  drm/i915: Create a kernel context for GGTT updates
  drm/i915: Implement for_each_sgt_daddr_next
  drm/i915: Parameterize binder context creation
  drm/i915: Implement GGTT update method with MI_UPDATE_GTT
  drm/i915: Toggle binder context ready status
  drm/i915: Enable GGTT updates with binder in MTL

 drivers/gpu/drm/i915/gt/intel_engine.h       |   2 +
 drivers/gpu/drm/i915/gt/intel_engine_cs.c    |  35 ++-
 drivers/gpu/drm/i915/gt/intel_engine_types.h |   3 +
 drivers/gpu/drm/i915/gt/intel_ggtt.c         | 235 +++++++++++++++++++
 drivers/gpu/drm/i915/gt/intel_gt.c           |  18 ++
 drivers/gpu/drm/i915/gt/intel_gt.h           |   2 +
 drivers/gpu/drm/i915/gt/intel_gtt.c          |   5 +
 drivers/gpu/drm/i915/gt/intel_gtt.h          |   5 +
 drivers/gpu/drm/i915/i915_driver.c           |   5 +
 drivers/gpu/drm/i915/i915_scatterlist.h      |  10 +
 drivers/gpu/drm/i915/intel_wakeref.c         |  43 ++--
 11 files changed, 340 insertions(+), 23 deletions(-)

-- 
2.41.0

[Intel-gfx] [PATCH 1/7] drm/i915: Lift runtime-pm acquire callbacks out of intel_wakeref.mutex

[Nirmoy Das]

From: Chris Wilson <chris.p.wilson@intel.com>

When runtime pm is first woken, it will synchronously call the
registered callbacks for the device. These callbacks
may pull in their own forest of locks, which we do not want to
conflate with the intel_wakeref.mutex. A second minor benefit to
reducing the coverage of the mutex, is that it will reduce
contention for frequent sleeps and wakes (such as when being used
for soft-rc6).

Signed-off-by: Chris Wilson <chris.p.wilson@intel.com>
Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_wakeref.c | 43 ++++++++++++++--------------
 1 file changed, 21 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_wakeref.c b/drivers/gpu/drm/i915/intel_wakeref.c
index 718f2f1b6174..af7b4cb5b4d7 100644
--- a/drivers/gpu/drm/i915/intel_wakeref.c
+++ b/drivers/gpu/drm/i915/intel_wakeref.c
@@ -10,21 +10,11 @@
 #include "intel_wakeref.h"
 #include "i915_drv.h"
 
-static void rpm_get(struct intel_wakeref *wf)
-{
-	wf->wakeref = intel_runtime_pm_get(&wf->i915->runtime_pm);
-}
-
-static void rpm_put(struct intel_wakeref *wf)
-{
-	intel_wakeref_t wakeref = fetch_and_zero(&wf->wakeref);
-
-	intel_runtime_pm_put(&wf->i915->runtime_pm, wakeref);
-	INTEL_WAKEREF_BUG_ON(!wakeref);
-}
-
 int __intel_wakeref_get_first(struct intel_wakeref *wf)
 {
+	intel_wakeref_t wakeref = intel_runtime_pm_get(&wf->i915->runtime_pm);
+	int err = 0;
+
 	/*
 	 * Treat get/put as different subclasses, as we may need to run
 	 * the put callback from under the shrinker and do not want to
@@ -32,41 +22,50 @@ int __intel_wakeref_get_first(struct intel_wakeref *wf)
 	 * upon acquiring the wakeref.
 	 */
 	mutex_lock_nested(&wf->mutex, SINGLE_DEPTH_NESTING);
-	if (!atomic_read(&wf->count)) {
-		int err;
 
-		rpm_get(wf);
+	if (likely(!atomic_read(&wf->count))) {
+		INTEL_WAKEREF_BUG_ON(wf->wakeref);
+		wf->wakeref = fetch_and_zero(&wakeref);
 
 		err = wf->ops->get(wf);
 		if (unlikely(err)) {
-			rpm_put(wf);
-			mutex_unlock(&wf->mutex);
-			return err;
+			wakeref = xchg(&wf->wakeref, 0);
+			wake_up_var(&wf->wakeref);
+			goto unlock;
 		}
 
 		smp_mb__before_atomic(); /* release wf->count */
 	}
 	atomic_inc(&wf->count);
+	INTEL_WAKEREF_BUG_ON(atomic_read(&wf->count) <= 0);
+
+unlock:
 	mutex_unlock(&wf->mutex);
+	if (unlikely(wakeref))
+		intel_runtime_pm_put(&wf->i915->runtime_pm, wakeref);
 
-	INTEL_WAKEREF_BUG_ON(atomic_read(&wf->count) <= 0);
-	return 0;
+	return err;
 }
 
 static void ____intel_wakeref_put_last(struct intel_wakeref *wf)
 {
+	intel_wakeref_t wakeref = 0;
+
 	INTEL_WAKEREF_BUG_ON(atomic_read(&wf->count) <= 0);
 	if (unlikely(!atomic_dec_and_test(&wf->count)))
 		goto unlock;
 
 	/* ops->put() must reschedule its own release on error/deferral */
 	if (likely(!wf->ops->put(wf))) {
-		rpm_put(wf);
+		INTEL_WAKEREF_BUG_ON(!wf->wakeref);
+		wakeref = xchg(&wf->wakeref, 0);
 		wake_up_var(&wf->wakeref);
 	}
 
 unlock:
 	mutex_unlock(&wf->mutex);
+	if (wakeref)
+		intel_runtime_pm_put(&wf->i915->runtime_pm, wakeref);
 }
 
 void __intel_wakeref_put_last(struct intel_wakeref *wf, unsigned long flags)
-- 
2.41.0

[Intel-gfx] [PATCH 2/7] drm/i915: Create a kernel context for GGTT updates

[Nirmoy Das]

Create a separate kernel context if a platform requires
GGTT updates using MI_UPDATE_GTT blitter command.

Subsequent patch will introduce methods to update
GGTT using this bind context and MI_UPDATE_GTT blitter
command.

Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine.h       |  2 ++
 drivers/gpu/drm/i915/gt/intel_engine_cs.c    | 35 +++++++++++++++++++-
 drivers/gpu/drm/i915/gt/intel_engine_types.h |  3 ++
 drivers/gpu/drm/i915/gt/intel_gt.c           | 18 ++++++++++
 drivers/gpu/drm/i915/gt/intel_gt.h           |  2 ++
 5 files changed, 59 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index b58c30ac8ef0..40269e4c1e31 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -170,6 +170,8 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
 #define I915_GEM_HWS_SEQNO		0x40
 #define I915_GEM_HWS_SEQNO_ADDR		(I915_GEM_HWS_SEQNO * sizeof(u32))
 #define I915_GEM_HWS_MIGRATE		(0x42 * sizeof(u32))
+#define I915_GEM_HWS_GGTT_BIND		0x46
+#define I915_GEM_HWS_GGTT_BIND_ADDR	(I915_GEM_HWS_GGTT_BIND * sizeof(u32))
 #define I915_GEM_HWS_PXP		0x60
 #define I915_GEM_HWS_PXP_ADDR		(I915_GEM_HWS_PXP * sizeof(u32))
 #define I915_GEM_HWS_GSC		0x62
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index dfb69fc977a0..18ae56ea012a 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1419,6 +1419,20 @@ void intel_engine_destroy_pinned_context(struct intel_context *ce)
 	intel_context_put(ce);
 }
 
+static struct intel_context *
+create_ggtt_bind_context(struct intel_engine_cs *engine)
+{
+	static struct lock_class_key kernel;
+
+	/*
+	 * MI_UPDATE_GTT can insert up to 512 PTE entries and there could be multiple
+	 * bind requets at a time so get a bigger ring.
+	 */
+	return intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_512K,
+						  I915_GEM_HWS_GGTT_BIND_ADDR,
+						  &kernel, "ggtt_bind_context");
+}
+
 static struct intel_context *
 create_kernel_context(struct intel_engine_cs *engine)
 {
@@ -1442,7 +1456,7 @@ create_kernel_context(struct intel_engine_cs *engine)
  */
 static int engine_init_common(struct intel_engine_cs *engine)
 {
-	struct intel_context *ce;
+	struct intel_context *ce, *bce = NULL;
 	int ret;
 
 	engine->set_default_submission(engine);
@@ -1458,6 +1472,19 @@ static int engine_init_common(struct intel_engine_cs *engine)
 	ce = create_kernel_context(engine);
 	if (IS_ERR(ce))
 		return PTR_ERR(ce);
+	/*
+	 * Create a separate pinned context for GGTT update with blitter engine
+	 * if a platform require such service. MI_UPDATE_GTT works on other
+	 * engines as well but BCS should be less busy engine so pick that for
+	 * GGTT updates.
+	 */
+	if (engine->id == BCS0) {
+		bce = create_ggtt_bind_context(engine);
+		if (IS_ERR(bce)) {
+			intel_engine_destroy_pinned_context(ce);
+			return PTR_ERR(bce);
+		}
+	}
 
 	ret = measure_breadcrumb_dw(ce);
 	if (ret < 0)
@@ -1465,11 +1492,14 @@ static int engine_init_common(struct intel_engine_cs *engine)
 
 	engine->emit_fini_breadcrumb_dw = ret;
 	engine->kernel_context = ce;
+	engine->bind_context = bce;
 
 	return 0;
 
 err_context:
 	intel_engine_destroy_pinned_context(ce);
+	if (bce)
+		intel_engine_destroy_pinned_context(ce);
 	return ret;
 }
 
@@ -1537,6 +1567,9 @@ void intel_engine_cleanup_common(struct intel_engine_cs *engine)
 
 	if (engine->kernel_context)
 		intel_engine_destroy_pinned_context(engine->kernel_context);
+	if (engine->bind_context)
+		intel_engine_destroy_pinned_context(engine->bind_context);
+
 
 	GEM_BUG_ON(!llist_empty(&engine->barrier_tasks));
 	cleanup_status_page(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index a7e677598004..a8f527fab0f0 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -416,6 +416,9 @@ struct intel_engine_cs {
 	struct llist_head barrier_tasks;
 
 	struct intel_context *kernel_context; /* pinned */
+	struct intel_context *bind_context; /* pinned, only for BCS0 */
+	/* mark the bind context's availability status */
+	bool bind_context_ready;
 
 	/**
 	 * pinned_contexts_list: List of pinned contexts. This list is only
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 449f0b7fc843..cd0ff1597db9 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -1019,3 +1019,21 @@ enum i915_map_type intel_gt_coherent_map_type(struct intel_gt *gt,
 	else
 		return I915_MAP_WC;
 }
+
+void intel_gt_bind_context_set_ready(struct intel_gt *gt, bool ready)
+{
+	struct intel_engine_cs *engine = gt->engine[BCS0];
+
+	if (engine && engine->bind_context)
+		engine->bind_context_ready = ready;
+}
+
+bool intel_gt_is_bind_context_ready(struct intel_gt *gt)
+{
+	struct intel_engine_cs *engine = gt->engine[BCS0];
+
+	if (engine)
+		return engine->bind_context_ready;
+
+	return false;
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index 239848bcb2a4..9e70e625cebc 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -180,4 +180,6 @@ enum i915_map_type intel_gt_coherent_map_type(struct intel_gt *gt,
 					      struct drm_i915_gem_object *obj,
 					      bool always_coherent);
 
+void intel_gt_bind_context_set_ready(struct intel_gt *gt, bool ready);
+bool intel_gt_is_bind_context_ready(struct intel_gt *gt);
 #endif /* __INTEL_GT_H__ */
-- 
2.41.0

Re: [Intel-gfx] [PATCH 2/7] drm/i915: Create a kernel context for GGTT updates

[Zeng, Oak]

Reviewed-by: Oak Zeng <oak.zeng@intel.com>

Thanks,
Oak

> -----Original Message-----
> From: Das, Nirmoy <nirmoy.das@intel.com>
> Sent: Friday, September 15, 2023 4:34 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Zeng, Oak <oak.zeng@intel.com>; chris.p.wilson@linux.intel.com; Piorkowski,
> Piotr <piotr.piorkowski@intel.com>; Shyti, Andi <andi.shyti@intel.com>; Mun,
> Gwan-gyeong <gwan-gyeong.mun@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>; Das, Nirmoy <nirmoy.das@intel.com>
> Subject: [PATCH 2/7] drm/i915: Create a kernel context for GGTT updates
> 
> Create a separate kernel context if a platform requires
> GGTT updates using MI_UPDATE_GTT blitter command.
> 
> Subsequent patch will introduce methods to update
> GGTT using this bind context and MI_UPDATE_GTT blitter
> command.
> 
> Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_engine.h       |  2 ++
>  drivers/gpu/drm/i915/gt/intel_engine_cs.c    | 35 +++++++++++++++++++-
>  drivers/gpu/drm/i915/gt/intel_engine_types.h |  3 ++
>  drivers/gpu/drm/i915/gt/intel_gt.c           | 18 ++++++++++
>  drivers/gpu/drm/i915/gt/intel_gt.h           |  2 ++
>  5 files changed, 59 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
> b/drivers/gpu/drm/i915/gt/intel_engine.h
> index b58c30ac8ef0..40269e4c1e31 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> @@ -170,6 +170,8 @@ intel_write_status_page(struct intel_engine_cs *engine,
> int reg, u32 value)
>  #define I915_GEM_HWS_SEQNO		0x40
>  #define I915_GEM_HWS_SEQNO_ADDR		(I915_GEM_HWS_SEQNO
> * sizeof(u32))
>  #define I915_GEM_HWS_MIGRATE		(0x42 * sizeof(u32))
> +#define I915_GEM_HWS_GGTT_BIND		0x46
> +#define I915_GEM_HWS_GGTT_BIND_ADDR	(I915_GEM_HWS_GGTT_BIND *
> sizeof(u32))
>  #define I915_GEM_HWS_PXP		0x60
>  #define I915_GEM_HWS_PXP_ADDR		(I915_GEM_HWS_PXP *
> sizeof(u32))
>  #define I915_GEM_HWS_GSC		0x62
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index dfb69fc977a0..18ae56ea012a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -1419,6 +1419,20 @@ void intel_engine_destroy_pinned_context(struct
> intel_context *ce)
>  	intel_context_put(ce);
>  }
> 
> +static struct intel_context *
> +create_ggtt_bind_context(struct intel_engine_cs *engine)
> +{
> +	static struct lock_class_key kernel;
> +
> +	/*
> +	 * MI_UPDATE_GTT can insert up to 512 PTE entries and there could be
> multiple
> +	 * bind requets at a time so get a bigger ring.
> +	 */
> +	return intel_engine_create_pinned_context(engine, engine->gt->vm,
> SZ_512K,
> +
> I915_GEM_HWS_GGTT_BIND_ADDR,
> +						  &kernel, "ggtt_bind_context");
> +}
> +
>  static struct intel_context *
>  create_kernel_context(struct intel_engine_cs *engine)
>  {
> @@ -1442,7 +1456,7 @@ create_kernel_context(struct intel_engine_cs *engine)
>   */
>  static int engine_init_common(struct intel_engine_cs *engine)
>  {
> -	struct intel_context *ce;
> +	struct intel_context *ce, *bce = NULL;
>  	int ret;
> 
>  	engine->set_default_submission(engine);
> @@ -1458,6 +1472,19 @@ static int engine_init_common(struct intel_engine_cs
> *engine)
>  	ce = create_kernel_context(engine);
>  	if (IS_ERR(ce))
>  		return PTR_ERR(ce);
> +	/*
> +	 * Create a separate pinned context for GGTT update with blitter engine
> +	 * if a platform require such service. MI_UPDATE_GTT works on other
> +	 * engines as well but BCS should be less busy engine so pick that for
> +	 * GGTT updates.
> +	 */
> +	if (engine->id == BCS0) {
> +		bce = create_ggtt_bind_context(engine);
> +		if (IS_ERR(bce)) {
> +			intel_engine_destroy_pinned_context(ce);
> +			return PTR_ERR(bce);
> +		}
> +	}
> 
>  	ret = measure_breadcrumb_dw(ce);
>  	if (ret < 0)
> @@ -1465,11 +1492,14 @@ static int engine_init_common(struct intel_engine_cs
> *engine)
> 
>  	engine->emit_fini_breadcrumb_dw = ret;
>  	engine->kernel_context = ce;
> +	engine->bind_context = bce;
> 
>  	return 0;
> 
>  err_context:
>  	intel_engine_destroy_pinned_context(ce);
> +	if (bce)
> +		intel_engine_destroy_pinned_context(ce);
>  	return ret;
>  }
> 
> @@ -1537,6 +1567,9 @@ void intel_engine_cleanup_common(struct
> intel_engine_cs *engine)
> 
>  	if (engine->kernel_context)
>  		intel_engine_destroy_pinned_context(engine->kernel_context);
> +	if (engine->bind_context)
> +		intel_engine_destroy_pinned_context(engine->bind_context);
> +
> 
>  	GEM_BUG_ON(!llist_empty(&engine->barrier_tasks));
>  	cleanup_status_page(engine);
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index a7e677598004..a8f527fab0f0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -416,6 +416,9 @@ struct intel_engine_cs {
>  	struct llist_head barrier_tasks;
> 
>  	struct intel_context *kernel_context; /* pinned */
> +	struct intel_context *bind_context; /* pinned, only for BCS0 */
> +	/* mark the bind context's availability status */
> +	bool bind_context_ready;
> 
>  	/**
>  	 * pinned_contexts_list: List of pinned contexts. This list is only
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
> b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 449f0b7fc843..cd0ff1597db9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -1019,3 +1019,21 @@ enum i915_map_type
> intel_gt_coherent_map_type(struct intel_gt *gt,
>  	else
>  		return I915_MAP_WC;
>  }
> +
> +void intel_gt_bind_context_set_ready(struct intel_gt *gt, bool ready)
> +{
> +	struct intel_engine_cs *engine = gt->engine[BCS0];
> +
> +	if (engine && engine->bind_context)
> +		engine->bind_context_ready = ready;
> +}
> +
> +bool intel_gt_is_bind_context_ready(struct intel_gt *gt)
> +{
> +	struct intel_engine_cs *engine = gt->engine[BCS0];
> +
> +	if (engine)
> +		return engine->bind_context_ready;
> +
> +	return false;
> +}
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
> b/drivers/gpu/drm/i915/gt/intel_gt.h
> index 239848bcb2a4..9e70e625cebc 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
> @@ -180,4 +180,6 @@ enum i915_map_type
> intel_gt_coherent_map_type(struct intel_gt *gt,
>  					      struct drm_i915_gem_object *obj,
>  					      bool always_coherent);
> 
> +void intel_gt_bind_context_set_ready(struct intel_gt *gt, bool ready);
> +bool intel_gt_is_bind_context_ready(struct intel_gt *gt);
>  #endif /* __INTEL_GT_H__ */
> --
> 2.41.0

[Intel-gfx] [PATCH 3/7] drm/i915: Implement for_each_sgt_daddr_next

[Nirmoy Das]

Implement a way to iterate over sgt with pre-initialized
sgt_iter state.

Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
Reviewed-by: Oak Zeng <oak.zeng@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gtt.h     |  3 +++
 drivers/gpu/drm/i915/i915_scatterlist.h | 10 ++++++++++
 2 files changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
index 346ec8ec2edd..41e530d0a4e9 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -171,6 +171,9 @@ struct intel_gt;
 #define for_each_sgt_daddr(__dp, __iter, __sgt) \
 	__for_each_sgt_daddr(__dp, __iter, __sgt, I915_GTT_PAGE_SIZE)
 
+#define for_each_sgt_daddr_next(__dp, __iter) \
+	__for_each_daddr_next(__dp, __iter, I915_GTT_PAGE_SIZE)
+
 struct i915_page_table {
 	struct drm_i915_gem_object *base;
 	union {
diff --git a/drivers/gpu/drm/i915/i915_scatterlist.h b/drivers/gpu/drm/i915/i915_scatterlist.h
index 5a10c1a31183..6cf8a298849f 100644
--- a/drivers/gpu/drm/i915/i915_scatterlist.h
+++ b/drivers/gpu/drm/i915/i915_scatterlist.h
@@ -91,6 +91,16 @@ static inline struct scatterlist *__sg_next(struct scatterlist *sg)
 	     ((__dp) = (__iter).dma + (__iter).curr), (__iter).sgp;	\
 	     (((__iter).curr += (__step)) >= (__iter).max) ?		\
 	     (__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0)
+/**
+ * __for_each_daddr_next - iterates over the device addresses with pre-initialized iterator.
+ * @__dp:	Device address (output)
+ * @__iter:	'struct sgt_iter' (iterator state, external)
+ * @__step:	step size
+ */
+#define __for_each_daddr_next(__dp, __iter, __step)                  \
+	for (; ((__dp) = (__iter).dma + (__iter).curr), (__iter).sgp;   \
+	     (((__iter).curr += (__step)) >= (__iter).max) ?            \
+	     (__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0)
 
 /**
  * for_each_sgt_page - iterate over the pages of the given sg_table
-- 
2.41.0

[Intel-gfx] [PATCH 4/7] drm/i915: Parameterize binder context creation

[Nirmoy Das]

Add i915_ggtt_require_binder() to indicate that i915
needs to create binder context which will be used
by subsequent patch to enable i915_address_space vfuncs
that will use GPU commands to update GGTT.

Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
Reviewed-by: Oak Zeng <oak.zeng@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
 drivers/gpu/drm/i915/gt/intel_gtt.c       | 4 ++++
 drivers/gpu/drm/i915/gt/intel_gtt.h       | 2 ++
 3 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 18ae56ea012a..25c8afca440a 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1478,7 +1478,7 @@ static int engine_init_common(struct intel_engine_cs *engine)
 	 * engines as well but BCS should be less busy engine so pick that for
 	 * GGTT updates.
 	 */
-	if (engine->id == BCS0) {
+	if (i915_ggtt_require_binder(engine->i915) && engine->id == BCS0) {
 		bce = create_ggtt_bind_context(engine);
 		if (IS_ERR(bce)) {
 			intel_engine_destroy_pinned_context(ce);
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 13944a14ea2d..4c89eb8d9af7 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -21,6 +21,10 @@
 #include "intel_gt_regs.h"
 #include "intel_gtt.h"
 
+bool i915_ggtt_require_binder(struct drm_i915_private *i915)
+{
+	return false;
+}
 
 static bool intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *i915)
 {
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
index 41e530d0a4e9..b471edac2699 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -691,4 +691,6 @@ static inline struct sgt_dma {
 	return (struct sgt_dma){ sg, addr, addr + sg_dma_len(sg) };
 }
 
+bool i915_ggtt_require_binder(struct drm_i915_private *i915);
+
 #endif
-- 
2.41.0

[Intel-gfx] [PATCH 5/7] drm/i915: Implement GGTT update method with MI_UPDATE_GTT

[Nirmoy Das]

Implement GGTT update method with blitter command, MI_UPDATE_GTT
and install those handlers if a platform requires that.

v2: Make sure we hold the GT wakeref and Blitter engine wakeref before
we call mutex_lock/intel_context_enter below. When GT/engine are not
awake, the intel_context_enter calls into some runtime pm function which
can end up with kmalloc/fs_reclaim. But trigger fs_reclaim holding a
mutex lock is not allowed because shrinker can also try to hold the same
mutex lock. It is a circular lock. So hold the GT/blitter engine wakeref
before calling mutex_lock, to fix the circular lock.

Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
Signed-off-by: Oak Zeng <oak.zeng@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_ggtt.c | 235 +++++++++++++++++++++++++++
 1 file changed, 235 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index dd0ed941441a..b94de7cebfce 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -15,18 +15,23 @@
 #include "display/intel_display.h"
 #include "gem/i915_gem_lmem.h"
 
+#include "intel_context.h"
 #include "intel_ggtt_gmch.h"
+#include "intel_gpu_commands.h"
 #include "intel_gt.h"
 #include "intel_gt_regs.h"
 #include "intel_pci_config.h"
+#include "intel_ring.h"
 #include "i915_drv.h"
 #include "i915_pci.h"
+#include "i915_request.h"
 #include "i915_scatterlist.h"
 #include "i915_utils.h"
 #include "i915_vgpu.h"
 
 #include "intel_gtt.h"
 #include "gen8_ppgtt.h"
+#include "intel_engine_pm.h"
 
 static void i915_ggtt_color_adjust(const struct drm_mm_node *node,
 				   unsigned long color,
@@ -252,6 +257,145 @@ u64 gen8_ggtt_pte_encode(dma_addr_t addr,
 	return pte;
 }
 
+static bool should_update_ggtt_with_bind(struct i915_ggtt *ggtt)
+{
+	struct intel_gt *gt = ggtt->vm.gt;
+
+	return intel_gt_is_bind_context_ready(gt);
+}
+
+static struct intel_context *gen8_ggtt_bind_get_ce(struct i915_ggtt *ggtt)
+{
+	struct intel_context *ce;
+	struct intel_gt *gt = ggtt->vm.gt;
+
+	if (intel_gt_is_wedged(gt))
+		return NULL;
+
+	ce = gt->engine[BCS0]->bind_context;
+	GEM_BUG_ON(!ce);
+
+	/*
+	 * If the GT is not awake already at this stage then fallback
+	 * to pci based GGTT update otherwise __intel_wakeref_get_first()
+	 * would conflict with fs_reclaim trying to allocate memory while
+	 * doing rpm_resume().
+	 */
+	if (!intel_gt_pm_get_if_awake(gt))
+		return NULL;
+
+	intel_engine_pm_get(ce->engine);
+
+	return ce;
+}
+
+static void gen8_ggtt_bind_put_ce(struct intel_context *ce)
+{
+	intel_engine_pm_put(ce->engine);
+	intel_gt_pm_put(ce->engine->gt);
+}
+
+static bool gen8_ggtt_bind_ptes(struct i915_ggtt *ggtt, u32 offset,
+				struct sg_table *pages, u32 num_entries,
+				const gen8_pte_t pte)
+{
+	struct i915_sched_attr attr = {};
+	struct intel_gt *gt = ggtt->vm.gt;
+	const gen8_pte_t scratch_pte = ggtt->vm.scratch[0]->encode;
+	struct sgt_iter iter;
+	struct i915_request *rq;
+	struct intel_context *ce;
+	u32 *cs;
+
+	if (!num_entries)
+		return true;
+
+	ce = gen8_ggtt_bind_get_ce(ggtt);
+	if (!ce)
+		return false;
+
+	if (pages)
+		iter = __sgt_iter(pages->sgl, true);
+
+	while (num_entries) {
+		int count = 0;
+		dma_addr_t addr;
+		/*
+		 * MI_UPDATE_GTT can update 512 entries in a single command but
+		 * that end up with engine reset, 511 works.
+		 */
+		u32 n_ptes = min_t(u32, 511, num_entries);
+
+		if (mutex_lock_interruptible(&ce->timeline->mutex))
+			goto put_ce;
+
+		intel_context_enter(ce);
+		rq = __i915_request_create(ce, GFP_NOWAIT | GFP_ATOMIC);
+		intel_context_exit(ce);
+		if (IS_ERR(rq)) {
+			GT_TRACE(gt, "Failed to get bind request\n");
+			mutex_unlock(&ce->timeline->mutex);
+			goto put_ce;
+		}
+
+		cs = intel_ring_begin(rq, 2 * n_ptes + 2);
+		if (IS_ERR(cs)) {
+			GT_TRACE(gt, "Failed to ring space for GGTT bind\n");
+			i915_request_set_error_once(rq, PTR_ERR(cs));
+			/* once a request is created, it must be queued */
+			goto queue_err_rq;
+		}
+
+		*cs++ = MI_UPDATE_GTT | (2 * n_ptes);
+		*cs++ = offset << 12;
+
+		if (pages) {
+			for_each_sgt_daddr_next(addr, iter) {
+				if (count == n_ptes)
+					break;
+				*cs++ = lower_32_bits(pte | addr);
+				*cs++ = upper_32_bits(pte | addr);
+				count++;
+			}
+			/* fill remaining with scratch pte, if any */
+			if (count < n_ptes) {
+				memset64((u64 *)cs, scratch_pte,
+					 n_ptes - count);
+				cs += (n_ptes - count) * 2;
+			}
+		} else {
+			memset64((u64 *)cs, pte, n_ptes);
+			cs += n_ptes * 2;
+		}
+
+		intel_ring_advance(rq, cs);
+queue_err_rq:
+		i915_request_get(rq);
+		__i915_request_commit(rq);
+		__i915_request_queue(rq, &attr);
+
+		mutex_unlock(&ce->timeline->mutex);
+		/* This will break if the request is complete or after engine reset */
+		i915_request_wait(rq, 0, MAX_SCHEDULE_TIMEOUT);
+		if (rq->fence.error)
+			goto err_rq;
+
+		i915_request_put(rq);
+
+		num_entries -= n_ptes;
+		offset += n_ptes;
+	}
+
+	gen8_ggtt_bind_put_ce(ce);
+	return true;
+
+err_rq:
+	i915_request_put(rq);
+put_ce:
+	gen8_ggtt_bind_put_ce(ce);
+	return false;
+}
+
 static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
 {
 	writeq(pte, addr);
@@ -272,6 +416,21 @@ static void gen8_ggtt_insert_page(struct i915_address_space *vm,
 	ggtt->invalidate(ggtt);
 }
 
+static void gen8_ggtt_insert_page_bind(struct i915_address_space *vm,
+				       dma_addr_t addr, u64 offset,
+				       unsigned int pat_index, u32 flags)
+{
+	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
+	gen8_pte_t pte;
+
+	pte = ggtt->vm.pte_encode(addr, pat_index, flags);
+	if (should_update_ggtt_with_bind(i915_vm_to_ggtt(vm)) &&
+	    gen8_ggtt_bind_ptes(ggtt, offset, NULL, 1, pte))
+		return ggtt->invalidate(ggtt);
+
+	gen8_ggtt_insert_page(vm, addr, offset, pat_index, flags);
+}
+
 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
 				     struct i915_vma_resource *vma_res,
 				     unsigned int pat_index,
@@ -311,6 +470,50 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
 	ggtt->invalidate(ggtt);
 }
 
+static bool __gen8_ggtt_insert_entries_bind(struct i915_address_space *vm,
+					    struct i915_vma_resource *vma_res,
+					    unsigned int pat_index, u32 flags)
+{
+	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
+	gen8_pte_t scratch_pte = vm->scratch[0]->encode;
+	gen8_pte_t pte_encode;
+	u64 start, end;
+
+	pte_encode = ggtt->vm.pte_encode(0, pat_index, flags);
+	start = (vma_res->start - vma_res->guard) / I915_GTT_PAGE_SIZE;
+	end = start + vma_res->guard / I915_GTT_PAGE_SIZE;
+	if (!gen8_ggtt_bind_ptes(ggtt, start, NULL, end - start, scratch_pte))
+		goto err;
+
+	start = end;
+	end += (vma_res->node_size + vma_res->guard) / I915_GTT_PAGE_SIZE;
+	if (!gen8_ggtt_bind_ptes(ggtt, start, vma_res->bi.pages,
+	      vma_res->node_size / I915_GTT_PAGE_SIZE, pte_encode))
+		goto err;
+
+	start += vma_res->node_size / I915_GTT_PAGE_SIZE;
+	if (!gen8_ggtt_bind_ptes(ggtt, start, NULL, end - start, scratch_pte))
+		goto err;
+
+	return true;
+
+err:
+	return false;
+}
+
+static void gen8_ggtt_insert_entries_bind(struct i915_address_space *vm,
+					  struct i915_vma_resource *vma_res,
+					  unsigned int pat_index, u32 flags)
+{
+	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
+
+	if (should_update_ggtt_with_bind(i915_vm_to_ggtt(vm)) &&
+	    __gen8_ggtt_insert_entries_bind(vm, vma_res, pat_index, flags))
+		return ggtt->invalidate(ggtt);
+
+	gen8_ggtt_insert_entries(vm, vma_res, pat_index, flags);
+}
+
 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
 				  u64 start, u64 length)
 {
@@ -332,6 +535,27 @@ static void gen8_ggtt_clear_range(struct i915_address_space *vm,
 		gen8_set_pte(&gtt_base[i], scratch_pte);
 }
 
+static void gen8_ggtt_scratch_range_bind(struct i915_address_space *vm,
+					 u64 start, u64 length)
+{
+	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
+	unsigned int first_entry = start / I915_GTT_PAGE_SIZE;
+	unsigned int num_entries = length / I915_GTT_PAGE_SIZE;
+	const gen8_pte_t scratch_pte = vm->scratch[0]->encode;
+	const int max_entries = ggtt_total_entries(ggtt) - first_entry;
+
+	if (WARN(num_entries > max_entries,
+		 "First entry = %d; Num entries = %d (max=%d)\n",
+		 first_entry, num_entries, max_entries))
+		num_entries = max_entries;
+
+	if (should_update_ggtt_with_bind(ggtt) && gen8_ggtt_bind_ptes(ggtt, first_entry,
+	     NULL, num_entries, scratch_pte))
+		return ggtt->invalidate(ggtt);
+
+	gen8_ggtt_clear_range(vm, start, length);
+}
+
 static void gen6_ggtt_insert_page(struct i915_address_space *vm,
 				  dma_addr_t addr,
 				  u64 offset,
@@ -997,6 +1221,17 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
 			I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND;
 	}
 
+	if (i915_ggtt_require_binder(i915)) {
+		ggtt->vm.scratch_range = gen8_ggtt_scratch_range_bind;
+		ggtt->vm.insert_page = gen8_ggtt_insert_page_bind;
+		ggtt->vm.insert_entries = gen8_ggtt_insert_entries_bind;
+		/*
+		 * On GPU is hung, we might bind VMAs for error capture.
+		 * Fallback to CPU GGTT updates in that case.
+		 */
+		ggtt->vm.raw_insert_page = gen8_ggtt_insert_page;
+	}
+
 	if (intel_uc_wants_guc(&ggtt->vm.gt->uc))
 		ggtt->invalidate = guc_ggtt_invalidate;
 	else
-- 
2.41.0

Re: [Intel-gfx] [PATCH 5/7] drm/i915: Implement GGTT update method with MI_UPDATE_GTT

[Zeng, Oak]

Thanks,
Oak

> -----Original Message-----
> From: Das, Nirmoy <nirmoy.das@intel.com>
> Sent: Friday, September 15, 2023 4:34 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Zeng, Oak <oak.zeng@intel.com>; chris.p.wilson@linux.intel.com; Piorkowski,
> Piotr <piotr.piorkowski@intel.com>; Shyti, Andi <andi.shyti@intel.com>; Mun,
> Gwan-gyeong <gwan-gyeong.mun@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>; Das, Nirmoy <nirmoy.das@intel.com>
> Subject: [PATCH 5/7] drm/i915: Implement GGTT update method with
> MI_UPDATE_GTT
> 
> Implement GGTT update method with blitter command, MI_UPDATE_GTT
> and install those handlers if a platform requires that.
> 
> v2: Make sure we hold the GT wakeref and Blitter engine wakeref before
> we call mutex_lock/intel_context_enter below. When GT/engine are not
> awake, the intel_context_enter calls into some runtime pm function which
> can end up with kmalloc/fs_reclaim. But trigger fs_reclaim holding a
> mutex lock is not allowed because shrinker can also try to hold the same
> mutex lock. It is a circular lock. So hold the GT/blitter engine wakeref
> before calling mutex_lock, to fix the circular lock.
> 
> Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
> Signed-off-by: Oak Zeng <oak.zeng@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_ggtt.c | 235 +++++++++++++++++++++++++++
>  1 file changed, 235 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> index dd0ed941441a..b94de7cebfce 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> @@ -15,18 +15,23 @@
>  #include "display/intel_display.h"
>  #include "gem/i915_gem_lmem.h"
> 
> +#include "intel_context.h"
>  #include "intel_ggtt_gmch.h"
> +#include "intel_gpu_commands.h"
>  #include "intel_gt.h"
>  #include "intel_gt_regs.h"
>  #include "intel_pci_config.h"
> +#include "intel_ring.h"
>  #include "i915_drv.h"
>  #include "i915_pci.h"
> +#include "i915_request.h"
>  #include "i915_scatterlist.h"
>  #include "i915_utils.h"
>  #include "i915_vgpu.h"
> 
>  #include "intel_gtt.h"
>  #include "gen8_ppgtt.h"
> +#include "intel_engine_pm.h"
> 
>  static void i915_ggtt_color_adjust(const struct drm_mm_node *node,
>  				   unsigned long color,
> @@ -252,6 +257,145 @@ u64 gen8_ggtt_pte_encode(dma_addr_t addr,
>  	return pte;
>  }
> 
> +static bool should_update_ggtt_with_bind(struct i915_ggtt *ggtt)
> +{
> +	struct intel_gt *gt = ggtt->vm.gt;
> +
> +	return intel_gt_is_bind_context_ready(gt);
> +}
> +
> +static struct intel_context *gen8_ggtt_bind_get_ce(struct i915_ggtt *ggtt)
> +{
> +	struct intel_context *ce;
> +	struct intel_gt *gt = ggtt->vm.gt;
> +
> +	if (intel_gt_is_wedged(gt))
> +		return NULL;
> +
> +	ce = gt->engine[BCS0]->bind_context;
> +	GEM_BUG_ON(!ce);
> +
> +	/*
> +	 * If the GT is not awake already at this stage then fallback
> +	 * to pci based GGTT update otherwise __intel_wakeref_get_first()
> +	 * would conflict with fs_reclaim trying to allocate memory while
> +	 * doing rpm_resume().
> +	 */
> +	if (!intel_gt_pm_get_if_awake(gt))
> +		return NULL;
> +
> +	intel_engine_pm_get(ce->engine);
> +
> +	return ce;
> +}
> +
> +static void gen8_ggtt_bind_put_ce(struct intel_context *ce)
> +{
> +	intel_engine_pm_put(ce->engine);
> +	intel_gt_pm_put(ce->engine->gt);
> +}
> +
> +static bool gen8_ggtt_bind_ptes(struct i915_ggtt *ggtt, u32 offset,
> +				struct sg_table *pages, u32 num_entries,
> +				const gen8_pte_t pte)
> +{
> +	struct i915_sched_attr attr = {};
> +	struct intel_gt *gt = ggtt->vm.gt;
> +	const gen8_pte_t scratch_pte = ggtt->vm.scratch[0]->encode;
> +	struct sgt_iter iter;
> +	struct i915_request *rq;
> +	struct intel_context *ce;
> +	u32 *cs;
> +
> +	if (!num_entries)
> +		return true;
> +
> +	ce = gen8_ggtt_bind_get_ce(ggtt);
> +	if (!ce)
> +		return false;
> +
> +	if (pages)
> +		iter = __sgt_iter(pages->sgl, true);
> +
> +	while (num_entries) {
> +		int count = 0;
> +		dma_addr_t addr;
> +		/*
> +		 * MI_UPDATE_GTT can update 512 entries in a single command
> but
> +		 * that end up with engine reset, 511 works.
> +		 */
> +		u32 n_ptes = min_t(u32, 511, num_entries);
> +
> +		if (mutex_lock_interruptible(&ce->timeline->mutex))
> +			goto put_ce;
> +
> +		intel_context_enter(ce);
> +		rq = __i915_request_create(ce, GFP_NOWAIT | GFP_ATOMIC);
> +		intel_context_exit(ce);
> +		if (IS_ERR(rq)) {
> +			GT_TRACE(gt, "Failed to get bind request\n");
> +			mutex_unlock(&ce->timeline->mutex);
> +			goto put_ce;
> +		}
> +
> +		cs = intel_ring_begin(rq, 2 * n_ptes + 2);
> +		if (IS_ERR(cs)) {
> +			GT_TRACE(gt, "Failed to ring space for GGTT bind\n");
> +			i915_request_set_error_once(rq, PTR_ERR(cs));
> +			/* once a request is created, it must be queued */
> +			goto queue_err_rq;
> +		}
> +
> +		*cs++ = MI_UPDATE_GTT | (2 * n_ptes);
> +		*cs++ = offset << 12;
> +
> +		if (pages) {
> +			for_each_sgt_daddr_next(addr, iter) {
> +				if (count == n_ptes)
> +					break;
> +				*cs++ = lower_32_bits(pte | addr);
> +				*cs++ = upper_32_bits(pte | addr);
> +				count++;
> +			}
> +			/* fill remaining with scratch pte, if any */
> +			if (count < n_ptes) {
> +				memset64((u64 *)cs, scratch_pte,
> +					 n_ptes - count);
> +				cs += (n_ptes - count) * 2;
> +			}

Should we return error instead of silently fill pte with scratch? Or maybe even gem_bug_on on this case? The caller didn't allocate enough pages, means something wrong happened...

Oak

> +		} else {
> +			memset64((u64 *)cs, pte, n_ptes);
> +			cs += n_ptes * 2;
> +		}
> +
> +		intel_ring_advance(rq, cs);
> +queue_err_rq:
> +		i915_request_get(rq);
> +		__i915_request_commit(rq);
> +		__i915_request_queue(rq, &attr);
> +
> +		mutex_unlock(&ce->timeline->mutex);
> +		/* This will break if the request is complete or after engine reset
> */
> +		i915_request_wait(rq, 0, MAX_SCHEDULE_TIMEOUT);
> +		if (rq->fence.error)
> +			goto err_rq;
> +
> +		i915_request_put(rq);
> +
> +		num_entries -= n_ptes;
> +		offset += n_ptes;
> +	}
> +
> +	gen8_ggtt_bind_put_ce(ce);
> +	return true;
> +
> +err_rq:
> +	i915_request_put(rq);
> +put_ce:
> +	gen8_ggtt_bind_put_ce(ce);
> +	return false;
> +}
> +
>  static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
>  {
>  	writeq(pte, addr);
> @@ -272,6 +416,21 @@ static void gen8_ggtt_insert_page(struct
> i915_address_space *vm,
>  	ggtt->invalidate(ggtt);
>  }
> 
> +static void gen8_ggtt_insert_page_bind(struct i915_address_space *vm,
> +				       dma_addr_t addr, u64 offset,
> +				       unsigned int pat_index, u32 flags)
> +{
> +	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
> +	gen8_pte_t pte;
> +
> +	pte = ggtt->vm.pte_encode(addr, pat_index, flags);
> +	if (should_update_ggtt_with_bind(i915_vm_to_ggtt(vm)) &&
> +	    gen8_ggtt_bind_ptes(ggtt, offset, NULL, 1, pte))
> +		return ggtt->invalidate(ggtt);
> +
> +	gen8_ggtt_insert_page(vm, addr, offset, pat_index, flags);
> +}
> +
>  static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
>  				     struct i915_vma_resource *vma_res,
>  				     unsigned int pat_index,
> @@ -311,6 +470,50 @@ static void gen8_ggtt_insert_entries(struct
> i915_address_space *vm,
>  	ggtt->invalidate(ggtt);
>  }
> 
> +static bool __gen8_ggtt_insert_entries_bind(struct i915_address_space *vm,
> +					    struct i915_vma_resource *vma_res,
> +					    unsigned int pat_index, u32 flags)
> +{
> +	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
> +	gen8_pte_t scratch_pte = vm->scratch[0]->encode;
> +	gen8_pte_t pte_encode;
> +	u64 start, end;
> +
> +	pte_encode = ggtt->vm.pte_encode(0, pat_index, flags);
> +	start = (vma_res->start - vma_res->guard) / I915_GTT_PAGE_SIZE;
> +	end = start + vma_res->guard / I915_GTT_PAGE_SIZE;
> +	if (!gen8_ggtt_bind_ptes(ggtt, start, NULL, end - start, scratch_pte))
> +		goto err;
> +
> +	start = end;
> +	end += (vma_res->node_size + vma_res->guard) / I915_GTT_PAGE_SIZE;
> +	if (!gen8_ggtt_bind_ptes(ggtt, start, vma_res->bi.pages,
> +	      vma_res->node_size / I915_GTT_PAGE_SIZE, pte_encode))
> +		goto err;
> +
> +	start += vma_res->node_size / I915_GTT_PAGE_SIZE;
> +	if (!gen8_ggtt_bind_ptes(ggtt, start, NULL, end - start, scratch_pte))
> +		goto err;
> +
> +	return true;
> +
> +err:
> +	return false;
> +}
> +
> +static void gen8_ggtt_insert_entries_bind(struct i915_address_space *vm,
> +					  struct i915_vma_resource *vma_res,
> +					  unsigned int pat_index, u32 flags)
> +{
> +	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
> +
> +	if (should_update_ggtt_with_bind(i915_vm_to_ggtt(vm)) &&
> +	    __gen8_ggtt_insert_entries_bind(vm, vma_res, pat_index, flags))
> +		return ggtt->invalidate(ggtt);
> +
> +	gen8_ggtt_insert_entries(vm, vma_res, pat_index, flags);
> +}
> +
>  static void gen8_ggtt_clear_range(struct i915_address_space *vm,
>  				  u64 start, u64 length)
>  {
> @@ -332,6 +535,27 @@ static void gen8_ggtt_clear_range(struct
> i915_address_space *vm,
>  		gen8_set_pte(&gtt_base[i], scratch_pte);
>  }
> 
> +static void gen8_ggtt_scratch_range_bind(struct i915_address_space *vm,
> +					 u64 start, u64 length)
> +{
> +	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
> +	unsigned int first_entry = start / I915_GTT_PAGE_SIZE;
> +	unsigned int num_entries = length / I915_GTT_PAGE_SIZE;
> +	const gen8_pte_t scratch_pte = vm->scratch[0]->encode;
> +	const int max_entries = ggtt_total_entries(ggtt) - first_entry;
> +
> +	if (WARN(num_entries > max_entries,
> +		 "First entry = %d; Num entries = %d (max=%d)\n",
> +		 first_entry, num_entries, max_entries))
> +		num_entries = max_entries;
> +
> +	if (should_update_ggtt_with_bind(ggtt) && gen8_ggtt_bind_ptes(ggtt,
> first_entry,
> +	     NULL, num_entries, scratch_pte))
> +		return ggtt->invalidate(ggtt);
> +
> +	gen8_ggtt_clear_range(vm, start, length);
> +}
> +
>  static void gen6_ggtt_insert_page(struct i915_address_space *vm,
>  				  dma_addr_t addr,
>  				  u64 offset,
> @@ -997,6 +1221,17 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
>  			I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND;
>  	}
> 
> +	if (i915_ggtt_require_binder(i915)) {
> +		ggtt->vm.scratch_range = gen8_ggtt_scratch_range_bind;
> +		ggtt->vm.insert_page = gen8_ggtt_insert_page_bind;
> +		ggtt->vm.insert_entries = gen8_ggtt_insert_entries_bind;
> +		/*
> +		 * On GPU is hung, we might bind VMAs for error capture.
> +		 * Fallback to CPU GGTT updates in that case.
> +		 */
> +		ggtt->vm.raw_insert_page = gen8_ggtt_insert_page;
> +	}
> +
>  	if (intel_uc_wants_guc(&ggtt->vm.gt->uc))
>  		ggtt->invalidate = guc_ggtt_invalidate;
>  	else
> --
> 2.41.0

Re: [Intel-gfx] [PATCH 5/7] drm/i915: Implement GGTT update method with MI_UPDATE_GTT

[Piotr Piórkowski]

Zeng, Oak <oak.zeng@intel.com> wrote on pią [2023-wrz-15 17:56:56 +0200]:
> 
> 
> Thanks,
> Oak
> 
> > -----Original Message-----
> > From: Das, Nirmoy <nirmoy.das@intel.com>
> > Sent: Friday, September 15, 2023 4:34 AM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Zeng, Oak <oak.zeng@intel.com>; chris.p.wilson@linux.intel.com; Piorkowski,
> > Piotr <piotr.piorkowski@intel.com>; Shyti, Andi <andi.shyti@intel.com>; Mun,
> > Gwan-gyeong <gwan-gyeong.mun@intel.com>; Roper, Matthew D
> > <matthew.d.roper@intel.com>; Das, Nirmoy <nirmoy.das@intel.com>
> > Subject: [PATCH 5/7] drm/i915: Implement GGTT update method with
> > MI_UPDATE_GTT
> > 
> > Implement GGTT update method with blitter command, MI_UPDATE_GTT
> > and install those handlers if a platform requires that.
> > 
> > v2: Make sure we hold the GT wakeref and Blitter engine wakeref before
> > we call mutex_lock/intel_context_enter below. When GT/engine are not
> > awake, the intel_context_enter calls into some runtime pm function which
> > can end up with kmalloc/fs_reclaim. But trigger fs_reclaim holding a
> > mutex lock is not allowed because shrinker can also try to hold the same
> > mutex lock. It is a circular lock. So hold the GT/blitter engine wakeref
> > before calling mutex_lock, to fix the circular lock.
> > 
> > Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
> > Signed-off-by: Oak Zeng <oak.zeng@intel.com>
> > ---
> >  drivers/gpu/drm/i915/gt/intel_ggtt.c | 235 +++++++++++++++++++++++++++
> >  1 file changed, 235 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > index dd0ed941441a..b94de7cebfce 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > @@ -15,18 +15,23 @@
> >  #include "display/intel_display.h"
> >  #include "gem/i915_gem_lmem.h"
> > 
> > +#include "intel_context.h"
> >  #include "intel_ggtt_gmch.h"
> > +#include "intel_gpu_commands.h"
> >  #include "intel_gt.h"
> >  #include "intel_gt_regs.h"
> >  #include "intel_pci_config.h"
> > +#include "intel_ring.h"
> >  #include "i915_drv.h"
> >  #include "i915_pci.h"
> > +#include "i915_request.h"
> >  #include "i915_scatterlist.h"
> >  #include "i915_utils.h"
> >  #include "i915_vgpu.h"
> > 
> >  #include "intel_gtt.h"
> >  #include "gen8_ppgtt.h"
> > +#include "intel_engine_pm.h"
> > 
> >  static void i915_ggtt_color_adjust(const struct drm_mm_node *node,
> >  				   unsigned long color,
> > @@ -252,6 +257,145 @@ u64 gen8_ggtt_pte_encode(dma_addr_t addr,
> >  	return pte;
> >  }
> > 
> > +static bool should_update_ggtt_with_bind(struct i915_ggtt *ggtt)
> > +{
> > +	struct intel_gt *gt = ggtt->vm.gt;
> > +
> > +	return intel_gt_is_bind_context_ready(gt);
> > +}
> > +
> > +static struct intel_context *gen8_ggtt_bind_get_ce(struct i915_ggtt *ggtt)
> > +{
> > +	struct intel_context *ce;
> > +	struct intel_gt *gt = ggtt->vm.gt;
> > +
> > +	if (intel_gt_is_wedged(gt))
> > +		return NULL;
> > +
> > +	ce = gt->engine[BCS0]->bind_context;
> > +	GEM_BUG_ON(!ce);
> > +
> > +	/*
> > +	 * If the GT is not awake already at this stage then fallback
> > +	 * to pci based GGTT update otherwise __intel_wakeref_get_first()
> > +	 * would conflict with fs_reclaim trying to allocate memory while
> > +	 * doing rpm_resume().
> > +	 */
> > +	if (!intel_gt_pm_get_if_awake(gt))
> > +		return NULL;
> > +
> > +	intel_engine_pm_get(ce->engine);
> > +
> > +	return ce;
> > +}
> > +
> > +static void gen8_ggtt_bind_put_ce(struct intel_context *ce)
> > +{
> > +	intel_engine_pm_put(ce->engine);
> > +	intel_gt_pm_put(ce->engine->gt);
> > +}
> > +
> > +static bool gen8_ggtt_bind_ptes(struct i915_ggtt *ggtt, u32 offset,
> > +				struct sg_table *pages, u32 num_entries,
> > +				const gen8_pte_t pte)
> > +{
> > +	struct i915_sched_attr attr = {};
> > +	struct intel_gt *gt = ggtt->vm.gt;
> > +	const gen8_pte_t scratch_pte = ggtt->vm.scratch[0]->encode;
> > +	struct sgt_iter iter;
> > +	struct i915_request *rq;
> > +	struct intel_context *ce;
> > +	u32 *cs;
> > +
> > +	if (!num_entries)
> > +		return true;
> > +
> > +	ce = gen8_ggtt_bind_get_ce(ggtt);
> > +	if (!ce)
> > +		return false;
> > +
> > +	if (pages)
> > +		iter = __sgt_iter(pages->sgl, true);
> > +
> > +	while (num_entries) {
> > +		int count = 0;
> > +		dma_addr_t addr;
> > +		/*
> > +		 * MI_UPDATE_GTT can update 512 entries in a single command
> > but
> > +		 * that end up with engine reset, 511 works.
> > +		 */
> > +		u32 n_ptes = min_t(u32, 511, num_entries);
> > +
> > +		if (mutex_lock_interruptible(&ce->timeline->mutex))
> > +			goto put_ce;
> > +
> > +		intel_context_enter(ce);
> > +		rq = __i915_request_create(ce, GFP_NOWAIT | GFP_ATOMIC);
> > +		intel_context_exit(ce);
> > +		if (IS_ERR(rq)) {
> > +			GT_TRACE(gt, "Failed to get bind request\n");
> > +			mutex_unlock(&ce->timeline->mutex);
> > +			goto put_ce;
> > +		}
> > +
> > +		cs = intel_ring_begin(rq, 2 * n_ptes + 2);
> > +		if (IS_ERR(cs)) {
> > +			GT_TRACE(gt, "Failed to ring space for GGTT bind\n");
> > +			i915_request_set_error_once(rq, PTR_ERR(cs));
> > +			/* once a request is created, it must be queued */
> > +			goto queue_err_rq;
> > +		}
> > +
> > +		*cs++ = MI_UPDATE_GTT | (2 * n_ptes);
> > +		*cs++ = offset << 12;
> > +
> > +		if (pages) {
> > +			for_each_sgt_daddr_next(addr, iter) {
> > +				if (count == n_ptes)
> > +					break;
> > +				*cs++ = lower_32_bits(pte | addr);
> > +				*cs++ = upper_32_bits(pte | addr);
> > +				count++;
> > +			}
> > +			/* fill remaining with scratch pte, if any */
> > +			if (count < n_ptes) {
> > +				memset64((u64 *)cs, scratch_pte,
> > +					 n_ptes - count);
> > +				cs += (n_ptes - count) * 2;
> > +			}
> 
> Should we return error instead of silently fill pte with scratch? Or maybe even gem_bug_on on this case? The caller didn't allocate enough pages, means something wrong happened...

We should avoid GEM_BUG_ON, however, maybe it's a good idea for this function to return an int
instead of a bool, because there are a lot of places here that return an err. In that case,
ret > 0 could mean the number of PTEs we updated correctly and ret < 0 would be an error.

Piotr

> 
> Oak
> 
> > +		} else {
> > +			memset64((u64 *)cs, pte, n_ptes);
> > +			cs += n_ptes * 2;
> > +		}
> > +
> > +		intel_ring_advance(rq, cs);
> > +queue_err_rq:
> > +		i915_request_get(rq);
> > +		__i915_request_commit(rq);
> > +		__i915_request_queue(rq, &attr);
> > +
> > +		mutex_unlock(&ce->timeline->mutex);
> > +		/* This will break if the request is complete or after engine reset
> > */
> > +		i915_request_wait(rq, 0, MAX_SCHEDULE_TIMEOUT);
> > +		if (rq->fence.error)
> > +			goto err_rq;
> > +
> > +		i915_request_put(rq);
> > +
> > +		num_entries -= n_ptes;
> > +		offset += n_ptes;
> > +	}
> > +
> > +	gen8_ggtt_bind_put_ce(ce);
> > +	return true;
> > +
> > +err_rq:
> > +	i915_request_put(rq);
> > +put_ce:
> > +	gen8_ggtt_bind_put_ce(ce);
> > +	return false;
> > +}
> > +
> >  static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
> >  {
> >  	writeq(pte, addr);
> > @@ -272,6 +416,21 @@ static void gen8_ggtt_insert_page(struct
> > i915_address_space *vm,
> >  	ggtt->invalidate(ggtt);
> >  }
> > 
> > +static void gen8_ggtt_insert_page_bind(struct i915_address_space *vm,
> > +				       dma_addr_t addr, u64 offset,
> > +				       unsigned int pat_index, u32 flags)
> > +{
> > +	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
> > +	gen8_pte_t pte;
> > +
> > +	pte = ggtt->vm.pte_encode(addr, pat_index, flags);
> > +	if (should_update_ggtt_with_bind(i915_vm_to_ggtt(vm)) &&
> > +	    gen8_ggtt_bind_ptes(ggtt, offset, NULL, 1, pte))
> > +		return ggtt->invalidate(ggtt);
> > +
> > +	gen8_ggtt_insert_page(vm, addr, offset, pat_index, flags);
> > +}
> > +
> >  static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
> >  				     struct i915_vma_resource *vma_res,
> >  				     unsigned int pat_index,
> > @@ -311,6 +470,50 @@ static void gen8_ggtt_insert_entries(struct
> > i915_address_space *vm,
> >  	ggtt->invalidate(ggtt);
> >  }
> > 
> > +static bool __gen8_ggtt_insert_entries_bind(struct i915_address_space *vm,
> > +					    struct i915_vma_resource *vma_res,
> > +					    unsigned int pat_index, u32 flags)
> > +{
> > +	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
> > +	gen8_pte_t scratch_pte = vm->scratch[0]->encode;
> > +	gen8_pte_t pte_encode;
> > +	u64 start, end;
> > +
> > +	pte_encode = ggtt->vm.pte_encode(0, pat_index, flags);
> > +	start = (vma_res->start - vma_res->guard) / I915_GTT_PAGE_SIZE;
> > +	end = start + vma_res->guard / I915_GTT_PAGE_SIZE;
> > +	if (!gen8_ggtt_bind_ptes(ggtt, start, NULL, end - start, scratch_pte))
> > +		goto err;
> > +
> > +	start = end;
> > +	end += (vma_res->node_size + vma_res->guard) / I915_GTT_PAGE_SIZE;
> > +	if (!gen8_ggtt_bind_ptes(ggtt, start, vma_res->bi.pages,
> > +	      vma_res->node_size / I915_GTT_PAGE_SIZE, pte_encode))
> > +		goto err;
> > +
> > +	start += vma_res->node_size / I915_GTT_PAGE_SIZE;
> > +	if (!gen8_ggtt_bind_ptes(ggtt, start, NULL, end - start, scratch_pte))
> > +		goto err;
> > +
> > +	return true;
> > +
> > +err:
> > +	return false;
> > +}
> > +
> > +static void gen8_ggtt_insert_entries_bind(struct i915_address_space *vm,
> > +					  struct i915_vma_resource *vma_res,
> > +					  unsigned int pat_index, u32 flags)
> > +{
> > +	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
> > +
> > +	if (should_update_ggtt_with_bind(i915_vm_to_ggtt(vm)) &&
> > +	    __gen8_ggtt_insert_entries_bind(vm, vma_res, pat_index, flags))
> > +		return ggtt->invalidate(ggtt);
> > +
> > +	gen8_ggtt_insert_entries(vm, vma_res, pat_index, flags);
> > +}
> > +
> >  static void gen8_ggtt_clear_range(struct i915_address_space *vm,
> >  				  u64 start, u64 length)
> >  {
> > @@ -332,6 +535,27 @@ static void gen8_ggtt_clear_range(struct
> > i915_address_space *vm,
> >  		gen8_set_pte(&gtt_base[i], scratch_pte);
> >  }
> > 
> > +static void gen8_ggtt_scratch_range_bind(struct i915_address_space *vm,
> > +					 u64 start, u64 length)
> > +{
> > +	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
> > +	unsigned int first_entry = start / I915_GTT_PAGE_SIZE;
> > +	unsigned int num_entries = length / I915_GTT_PAGE_SIZE;
> > +	const gen8_pte_t scratch_pte = vm->scratch[0]->encode;
> > +	const int max_entries = ggtt_total_entries(ggtt) - first_entry;
> > +
> > +	if (WARN(num_entries > max_entries,
> > +		 "First entry = %d; Num entries = %d (max=%d)\n",
> > +		 first_entry, num_entries, max_entries))
> > +		num_entries = max_entries;
> > +
> > +	if (should_update_ggtt_with_bind(ggtt) && gen8_ggtt_bind_ptes(ggtt,
> > first_entry,
> > +	     NULL, num_entries, scratch_pte))
> > +		return ggtt->invalidate(ggtt);
> > +
> > +	gen8_ggtt_clear_range(vm, start, length);
> > +}
> > +
> >  static void gen6_ggtt_insert_page(struct i915_address_space *vm,
> >  				  dma_addr_t addr,
> >  				  u64 offset,
> > @@ -997,6 +1221,17 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
> >  			I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND;
> >  	}
> > 
> > +	if (i915_ggtt_require_binder(i915)) {
> > +		ggtt->vm.scratch_range = gen8_ggtt_scratch_range_bind;
> > +		ggtt->vm.insert_page = gen8_ggtt_insert_page_bind;
> > +		ggtt->vm.insert_entries = gen8_ggtt_insert_entries_bind;
> > +		/*
> > +		 * On GPU is hung, we might bind VMAs for error capture.
> > +		 * Fallback to CPU GGTT updates in that case.
> > +		 */
> > +		ggtt->vm.raw_insert_page = gen8_ggtt_insert_page;
> > +	}
> > +
> >  	if (intel_uc_wants_guc(&ggtt->vm.gt->uc))
> >  		ggtt->invalidate = guc_ggtt_invalidate;
> >  	else
> > --
> > 2.41.0
> 

-- 

Re: [Intel-gfx] [PATCH 5/7] drm/i915: Implement GGTT update method with MI_UPDATE_GTT

[Nirmoy Das]

On 9/15/2023 5:56 PM, Zeng, Oak wrote:
>
> Thanks,
> Oak
>
>> -----Original Message-----
>> From: Das, Nirmoy <nirmoy.das@intel.com>
>> Sent: Friday, September 15, 2023 4:34 AM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Zeng, Oak <oak.zeng@intel.com>; chris.p.wilson@linux.intel.com; Piorkowski,
>> Piotr <piotr.piorkowski@intel.com>; Shyti, Andi <andi.shyti@intel.com>; Mun,
>> Gwan-gyeong <gwan-gyeong.mun@intel.com>; Roper, Matthew D
>> <matthew.d.roper@intel.com>; Das, Nirmoy <nirmoy.das@intel.com>
>> Subject: [PATCH 5/7] drm/i915: Implement GGTT update method with
>> MI_UPDATE_GTT
>>
>> Implement GGTT update method with blitter command, MI_UPDATE_GTT
>> and install those handlers if a platform requires that.
>>
>> v2: Make sure we hold the GT wakeref and Blitter engine wakeref before
>> we call mutex_lock/intel_context_enter below. When GT/engine are not
>> awake, the intel_context_enter calls into some runtime pm function which
>> can end up with kmalloc/fs_reclaim. But trigger fs_reclaim holding a
>> mutex lock is not allowed because shrinker can also try to hold the same
>> mutex lock. It is a circular lock. So hold the GT/blitter engine wakeref
>> before calling mutex_lock, to fix the circular lock.
>>
>> Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
>> Signed-off-by: Oak Zeng <oak.zeng@intel.com>
>> ---
>>   drivers/gpu/drm/i915/gt/intel_ggtt.c | 235 +++++++++++++++++++++++++++
>>   1 file changed, 235 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> b/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> index dd0ed941441a..b94de7cebfce 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> @@ -15,18 +15,23 @@
>>   #include "display/intel_display.h"
>>   #include "gem/i915_gem_lmem.h"
>>
>> +#include "intel_context.h"
>>   #include "intel_ggtt_gmch.h"
>> +#include "intel_gpu_commands.h"
>>   #include "intel_gt.h"
>>   #include "intel_gt_regs.h"
>>   #include "intel_pci_config.h"
>> +#include "intel_ring.h"
>>   #include "i915_drv.h"
>>   #include "i915_pci.h"
>> +#include "i915_request.h"
>>   #include "i915_scatterlist.h"
>>   #include "i915_utils.h"
>>   #include "i915_vgpu.h"
>>
>>   #include "intel_gtt.h"
>>   #include "gen8_ppgtt.h"
>> +#include "intel_engine_pm.h"
>>
>>   static void i915_ggtt_color_adjust(const struct drm_mm_node *node,
>>   				   unsigned long color,
>> @@ -252,6 +257,145 @@ u64 gen8_ggtt_pte_encode(dma_addr_t addr,
>>   	return pte;
>>   }
>>
>> +static bool should_update_ggtt_with_bind(struct i915_ggtt *ggtt)
>> +{
>> +	struct intel_gt *gt = ggtt->vm.gt;
>> +
>> +	return intel_gt_is_bind_context_ready(gt);
>> +}
>> +
>> +static struct intel_context *gen8_ggtt_bind_get_ce(struct i915_ggtt *ggtt)
>> +{
>> +	struct intel_context *ce;
>> +	struct intel_gt *gt = ggtt->vm.gt;
>> +
>> +	if (intel_gt_is_wedged(gt))
>> +		return NULL;
>> +
>> +	ce = gt->engine[BCS0]->bind_context;
>> +	GEM_BUG_ON(!ce);
>> +
>> +	/*
>> +	 * If the GT is not awake already at this stage then fallback
>> +	 * to pci based GGTT update otherwise __intel_wakeref_get_first()
>> +	 * would conflict with fs_reclaim trying to allocate memory while
>> +	 * doing rpm_resume().
>> +	 */
>> +	if (!intel_gt_pm_get_if_awake(gt))
>> +		return NULL;
>> +
>> +	intel_engine_pm_get(ce->engine);
>> +
>> +	return ce;
>> +}
>> +
>> +static void gen8_ggtt_bind_put_ce(struct intel_context *ce)
>> +{
>> +	intel_engine_pm_put(ce->engine);
>> +	intel_gt_pm_put(ce->engine->gt);
>> +}
>> +
>> +static bool gen8_ggtt_bind_ptes(struct i915_ggtt *ggtt, u32 offset,
>> +				struct sg_table *pages, u32 num_entries,
>> +				const gen8_pte_t pte)
>> +{
>> +	struct i915_sched_attr attr = {};
>> +	struct intel_gt *gt = ggtt->vm.gt;
>> +	const gen8_pte_t scratch_pte = ggtt->vm.scratch[0]->encode;
>> +	struct sgt_iter iter;
>> +	struct i915_request *rq;
>> +	struct intel_context *ce;
>> +	u32 *cs;
>> +
>> +	if (!num_entries)
>> +		return true;
>> +
>> +	ce = gen8_ggtt_bind_get_ce(ggtt);
>> +	if (!ce)
>> +		return false;
>> +
>> +	if (pages)
>> +		iter = __sgt_iter(pages->sgl, true);
>> +
>> +	while (num_entries) {
>> +		int count = 0;
>> +		dma_addr_t addr;
>> +		/*
>> +		 * MI_UPDATE_GTT can update 512 entries in a single command
>> but
>> +		 * that end up with engine reset, 511 works.
>> +		 */
>> +		u32 n_ptes = min_t(u32, 511, num_entries);
>> +
>> +		if (mutex_lock_interruptible(&ce->timeline->mutex))
>> +			goto put_ce;
>> +
>> +		intel_context_enter(ce);
>> +		rq = __i915_request_create(ce, GFP_NOWAIT | GFP_ATOMIC);
>> +		intel_context_exit(ce);
>> +		if (IS_ERR(rq)) {
>> +			GT_TRACE(gt, "Failed to get bind request\n");
>> +			mutex_unlock(&ce->timeline->mutex);
>> +			goto put_ce;
>> +		}
>> +
>> +		cs = intel_ring_begin(rq, 2 * n_ptes + 2);
>> +		if (IS_ERR(cs)) {
>> +			GT_TRACE(gt, "Failed to ring space for GGTT bind\n");
>> +			i915_request_set_error_once(rq, PTR_ERR(cs));
>> +			/* once a request is created, it must be queued */
>> +			goto queue_err_rq;
>> +		}
>> +
>> +		*cs++ = MI_UPDATE_GTT | (2 * n_ptes);
>> +		*cs++ = offset << 12;
>> +
>> +		if (pages) {
>> +			for_each_sgt_daddr_next(addr, iter) {
>> +				if (count == n_ptes)
>> +					break;
>> +				*cs++ = lower_32_bits(pte | addr);
>> +				*cs++ = upper_32_bits(pte | addr);
>> +				count++;
>> +			}
>> +			/* fill remaining with scratch pte, if any */
>> +			if (count < n_ptes) {
>> +				memset64((u64 *)cs, scratch_pte,
>> +					 n_ptes - count);
>> +				cs += (n_ptes - count) * 2;
>> +			}
> Should we return error instead of silently fill pte with scratch? Or maybe even gem_bug_on on this case? The caller didn't allocate enough pages, means something wrong happened...


We do the dame already in gen8_ggtt_insert_entries() so not adding 
something new here. The comment just made it obvious :)  I don't know 
the exact usecase when this happens but

I saw tons of pipe error without this.


Regards,

Nirmoy

>
> Oak
>
>> +		} else {
>> +			memset64((u64 *)cs, pte, n_ptes);
>> +			cs += n_ptes * 2;
>> +		}
>> +
>> +		intel_ring_advance(rq, cs);
>> +queue_err_rq:
>> +		i915_request_get(rq);
>> +		__i915_request_commit(rq);
>> +		__i915_request_queue(rq, &attr);
>> +
>> +		mutex_unlock(&ce->timeline->mutex);
>> +		/* This will break if the request is complete or after engine reset
>> */
>> +		i915_request_wait(rq, 0, MAX_SCHEDULE_TIMEOUT);
>> +		if (rq->fence.error)
>> +			goto err_rq;
>> +
>> +		i915_request_put(rq);
>> +
>> +		num_entries -= n_ptes;
>> +		offset += n_ptes;
>> +	}
>> +
>> +	gen8_ggtt_bind_put_ce(ce);
>> +	return true;
>> +
>> +err_rq:
>> +	i915_request_put(rq);
>> +put_ce:
>> +	gen8_ggtt_bind_put_ce(ce);
>> +	return false;
>> +}
>> +
>>   static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
>>   {
>>   	writeq(pte, addr);
>> @@ -272,6 +416,21 @@ static void gen8_ggtt_insert_page(struct
>> i915_address_space *vm,
>>   	ggtt->invalidate(ggtt);
>>   }
>>
>> +static void gen8_ggtt_insert_page_bind(struct i915_address_space *vm,
>> +				       dma_addr_t addr, u64 offset,
>> +				       unsigned int pat_index, u32 flags)
>> +{
>> +	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
>> +	gen8_pte_t pte;
>> +
>> +	pte = ggtt->vm.pte_encode(addr, pat_index, flags);
>> +	if (should_update_ggtt_with_bind(i915_vm_to_ggtt(vm)) &&
>> +	    gen8_ggtt_bind_ptes(ggtt, offset, NULL, 1, pte))
>> +		return ggtt->invalidate(ggtt);
>> +
>> +	gen8_ggtt_insert_page(vm, addr, offset, pat_index, flags);
>> +}
>> +
>>   static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
>>   				     struct i915_vma_resource *vma_res,
>>   				     unsigned int pat_index,
>> @@ -311,6 +470,50 @@ static void gen8_ggtt_insert_entries(struct
>> i915_address_space *vm,
>>   	ggtt->invalidate(ggtt);
>>   }
>>
>> +static bool __gen8_ggtt_insert_entries_bind(struct i915_address_space *vm,
>> +					    struct i915_vma_resource *vma_res,
>> +					    unsigned int pat_index, u32 flags)
>> +{
>> +	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
>> +	gen8_pte_t scratch_pte = vm->scratch[0]->encode;
>> +	gen8_pte_t pte_encode;
>> +	u64 start, end;
>> +
>> +	pte_encode = ggtt->vm.pte_encode(0, pat_index, flags);
>> +	start = (vma_res->start - vma_res->guard) / I915_GTT_PAGE_SIZE;
>> +	end = start + vma_res->guard / I915_GTT_PAGE_SIZE;
>> +	if (!gen8_ggtt_bind_ptes(ggtt, start, NULL, end - start, scratch_pte))
>> +		goto err;
>> +
>> +	start = end;
>> +	end += (vma_res->node_size + vma_res->guard) / I915_GTT_PAGE_SIZE;
>> +	if (!gen8_ggtt_bind_ptes(ggtt, start, vma_res->bi.pages,
>> +	      vma_res->node_size / I915_GTT_PAGE_SIZE, pte_encode))
>> +		goto err;
>> +
>> +	start += vma_res->node_size / I915_GTT_PAGE_SIZE;
>> +	if (!gen8_ggtt_bind_ptes(ggtt, start, NULL, end - start, scratch_pte))
>> +		goto err;
>> +
>> +	return true;
>> +
>> +err:
>> +	return false;
>> +}
>> +
>> +static void gen8_ggtt_insert_entries_bind(struct i915_address_space *vm,
>> +					  struct i915_vma_resource *vma_res,
>> +					  unsigned int pat_index, u32 flags)
>> +{
>> +	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
>> +
>> +	if (should_update_ggtt_with_bind(i915_vm_to_ggtt(vm)) &&
>> +	    __gen8_ggtt_insert_entries_bind(vm, vma_res, pat_index, flags))
>> +		return ggtt->invalidate(ggtt);
>> +
>> +	gen8_ggtt_insert_entries(vm, vma_res, pat_index, flags);
>> +}
>> +
>>   static void gen8_ggtt_clear_range(struct i915_address_space *vm,
>>   				  u64 start, u64 length)
>>   {
>> @@ -332,6 +535,27 @@ static void gen8_ggtt_clear_range(struct
>> i915_address_space *vm,
>>   		gen8_set_pte(&gtt_base[i], scratch_pte);
>>   }
>>
>> +static void gen8_ggtt_scratch_range_bind(struct i915_address_space *vm,
>> +					 u64 start, u64 length)
>> +{
>> +	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
>> +	unsigned int first_entry = start / I915_GTT_PAGE_SIZE;
>> +	unsigned int num_entries = length / I915_GTT_PAGE_SIZE;
>> +	const gen8_pte_t scratch_pte = vm->scratch[0]->encode;
>> +	const int max_entries = ggtt_total_entries(ggtt) - first_entry;
>> +
>> +	if (WARN(num_entries > max_entries,
>> +		 "First entry = %d; Num entries = %d (max=%d)\n",
>> +		 first_entry, num_entries, max_entries))
>> +		num_entries = max_entries;
>> +
>> +	if (should_update_ggtt_with_bind(ggtt) && gen8_ggtt_bind_ptes(ggtt,
>> first_entry,
>> +	     NULL, num_entries, scratch_pte))
>> +		return ggtt->invalidate(ggtt);
>> +
>> +	gen8_ggtt_clear_range(vm, start, length);
>> +}
>> +
>>   static void gen6_ggtt_insert_page(struct i915_address_space *vm,
>>   				  dma_addr_t addr,
>>   				  u64 offset,
>> @@ -997,6 +1221,17 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
>>   			I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND;
>>   	}
>>
>> +	if (i915_ggtt_require_binder(i915)) {
>> +		ggtt->vm.scratch_range = gen8_ggtt_scratch_range_bind;
>> +		ggtt->vm.insert_page = gen8_ggtt_insert_page_bind;
>> +		ggtt->vm.insert_entries = gen8_ggtt_insert_entries_bind;
>> +		/*
>> +		 * On GPU is hung, we might bind VMAs for error capture.
>> +		 * Fallback to CPU GGTT updates in that case.
>> +		 */
>> +		ggtt->vm.raw_insert_page = gen8_ggtt_insert_page;
>> +	}
>> +
>>   	if (intel_uc_wants_guc(&ggtt->vm.gt->uc))
>>   		ggtt->invalidate = guc_ggtt_invalidate;
>>   	else
>> --
>> 2.41.0

Re: [Intel-gfx] [PATCH 5/7] drm/i915: Implement GGTT update method with MI_UPDATE_GTT

[Zeng, Oak]

Thanks,
Oak

> -----Original Message-----
> From: Das, Nirmoy <nirmoy.das@intel.com>
> Sent: Monday, September 18, 2023 6:26 AM
> To: Zeng, Oak <oak.zeng@intel.com>; intel-gfx@lists.freedesktop.org;
> Piorkowski, Piotr <piotr.piorkowski@intel.com>
> Cc: chris.p.wilson@linux.intel.com; Shyti, Andi <andi.shyti@intel.com>; Mun,
> Gwan-gyeong <gwan-gyeong.mun@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>
> Subject: Re: [PATCH 5/7] drm/i915: Implement GGTT update method with
> MI_UPDATE_GTT
> 
> 
> On 9/15/2023 5:56 PM, Zeng, Oak wrote:
> >
> > Thanks,
> > Oak
> >
> >> -----Original Message-----
> >> From: Das, Nirmoy <nirmoy.das@intel.com>
> >> Sent: Friday, September 15, 2023 4:34 AM
> >> To: intel-gfx@lists.freedesktop.org
> >> Cc: Zeng, Oak <oak.zeng@intel.com>; chris.p.wilson@linux.intel.com;
> Piorkowski,
> >> Piotr <piotr.piorkowski@intel.com>; Shyti, Andi <andi.shyti@intel.com>; Mun,
> >> Gwan-gyeong <gwan-gyeong.mun@intel.com>; Roper, Matthew D
> >> <matthew.d.roper@intel.com>; Das, Nirmoy <nirmoy.das@intel.com>
> >> Subject: [PATCH 5/7] drm/i915: Implement GGTT update method with
> >> MI_UPDATE_GTT
> >>
> >> Implement GGTT update method with blitter command, MI_UPDATE_GTT
> >> and install those handlers if a platform requires that.
> >>
> >> v2: Make sure we hold the GT wakeref and Blitter engine wakeref before
> >> we call mutex_lock/intel_context_enter below. When GT/engine are not
> >> awake, the intel_context_enter calls into some runtime pm function which
> >> can end up with kmalloc/fs_reclaim. But trigger fs_reclaim holding a
> >> mutex lock is not allowed because shrinker can also try to hold the same
> >> mutex lock. It is a circular lock. So hold the GT/blitter engine wakeref
> >> before calling mutex_lock, to fix the circular lock.
> >>
> >> Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
> >> Signed-off-by: Oak Zeng <oak.zeng@intel.com>
> >> ---
> >>   drivers/gpu/drm/i915/gt/intel_ggtt.c | 235
> +++++++++++++++++++++++++++
> >>   1 file changed, 235 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> >> b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> >> index dd0ed941441a..b94de7cebfce 100644
> >> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> >> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> >> @@ -15,18 +15,23 @@
> >>   #include "display/intel_display.h"
> >>   #include "gem/i915_gem_lmem.h"
> >>
> >> +#include "intel_context.h"
> >>   #include "intel_ggtt_gmch.h"
> >> +#include "intel_gpu_commands.h"
> >>   #include "intel_gt.h"
> >>   #include "intel_gt_regs.h"
> >>   #include "intel_pci_config.h"
> >> +#include "intel_ring.h"
> >>   #include "i915_drv.h"
> >>   #include "i915_pci.h"
> >> +#include "i915_request.h"
> >>   #include "i915_scatterlist.h"
> >>   #include "i915_utils.h"
> >>   #include "i915_vgpu.h"
> >>
> >>   #include "intel_gtt.h"
> >>   #include "gen8_ppgtt.h"
> >> +#include "intel_engine_pm.h"
> >>
> >>   static void i915_ggtt_color_adjust(const struct drm_mm_node *node,
> >>   				   unsigned long color,
> >> @@ -252,6 +257,145 @@ u64 gen8_ggtt_pte_encode(dma_addr_t addr,
> >>   	return pte;
> >>   }
> >>
> >> +static bool should_update_ggtt_with_bind(struct i915_ggtt *ggtt)
> >> +{
> >> +	struct intel_gt *gt = ggtt->vm.gt;
> >> +
> >> +	return intel_gt_is_bind_context_ready(gt);
> >> +}
> >> +
> >> +static struct intel_context *gen8_ggtt_bind_get_ce(struct i915_ggtt *ggtt)
> >> +{
> >> +	struct intel_context *ce;
> >> +	struct intel_gt *gt = ggtt->vm.gt;
> >> +
> >> +	if (intel_gt_is_wedged(gt))
> >> +		return NULL;
> >> +
> >> +	ce = gt->engine[BCS0]->bind_context;
> >> +	GEM_BUG_ON(!ce);
> >> +
> >> +	/*
> >> +	 * If the GT is not awake already at this stage then fallback
> >> +	 * to pci based GGTT update otherwise __intel_wakeref_get_first()
> >> +	 * would conflict with fs_reclaim trying to allocate memory while
> >> +	 * doing rpm_resume().
> >> +	 */
> >> +	if (!intel_gt_pm_get_if_awake(gt))
> >> +		return NULL;
> >> +
> >> +	intel_engine_pm_get(ce->engine);
> >> +
> >> +	return ce;
> >> +}
> >> +
> >> +static void gen8_ggtt_bind_put_ce(struct intel_context *ce)
> >> +{
> >> +	intel_engine_pm_put(ce->engine);
> >> +	intel_gt_pm_put(ce->engine->gt);
> >> +}
> >> +
> >> +static bool gen8_ggtt_bind_ptes(struct i915_ggtt *ggtt, u32 offset,
> >> +				struct sg_table *pages, u32 num_entries,
> >> +				const gen8_pte_t pte)
> >> +{
> >> +	struct i915_sched_attr attr = {};
> >> +	struct intel_gt *gt = ggtt->vm.gt;
> >> +	const gen8_pte_t scratch_pte = ggtt->vm.scratch[0]->encode;
> >> +	struct sgt_iter iter;
> >> +	struct i915_request *rq;
> >> +	struct intel_context *ce;
> >> +	u32 *cs;
> >> +
> >> +	if (!num_entries)
> >> +		return true;
> >> +
> >> +	ce = gen8_ggtt_bind_get_ce(ggtt);
> >> +	if (!ce)
> >> +		return false;
> >> +
> >> +	if (pages)
> >> +		iter = __sgt_iter(pages->sgl, true);
> >> +
> >> +	while (num_entries) {
> >> +		int count = 0;
> >> +		dma_addr_t addr;
> >> +		/*
> >> +		 * MI_UPDATE_GTT can update 512 entries in a single command
> >> but
> >> +		 * that end up with engine reset, 511 works.
> >> +		 */
> >> +		u32 n_ptes = min_t(u32, 511, num_entries);
> >> +
> >> +		if (mutex_lock_interruptible(&ce->timeline->mutex))
> >> +			goto put_ce;
> >> +
> >> +		intel_context_enter(ce);
> >> +		rq = __i915_request_create(ce, GFP_NOWAIT | GFP_ATOMIC);
> >> +		intel_context_exit(ce);
> >> +		if (IS_ERR(rq)) {
> >> +			GT_TRACE(gt, "Failed to get bind request\n");
> >> +			mutex_unlock(&ce->timeline->mutex);
> >> +			goto put_ce;
> >> +		}
> >> +
> >> +		cs = intel_ring_begin(rq, 2 * n_ptes + 2);
> >> +		if (IS_ERR(cs)) {
> >> +			GT_TRACE(gt, "Failed to ring space for GGTT bind\n");
> >> +			i915_request_set_error_once(rq, PTR_ERR(cs));
> >> +			/* once a request is created, it must be queued */
> >> +			goto queue_err_rq;
> >> +		}
> >> +
> >> +		*cs++ = MI_UPDATE_GTT | (2 * n_ptes);
> >> +		*cs++ = offset << 12;
> >> +
> >> +		if (pages) {
> >> +			for_each_sgt_daddr_next(addr, iter) {
> >> +				if (count == n_ptes)
> >> +					break;
> >> +				*cs++ = lower_32_bits(pte | addr);
> >> +				*cs++ = upper_32_bits(pte | addr);
> >> +				count++;
> >> +			}
> >> +			/* fill remaining with scratch pte, if any */
> >> +			if (count < n_ptes) {
> >> +				memset64((u64 *)cs, scratch_pte,
> >> +					 n_ptes - count);
> >> +				cs += (n_ptes - count) * 2;
> >> +			}
> > Should we return error instead of silently fill pte with scratch? Or maybe even
> gem_bug_on on this case? The caller didn't allocate enough pages, means
> something wrong happened...
> 
> 
> We do the dame already in gen8_ggtt_insert_entries() so not adding
> something new here. The comment just made it obvious :)  I don't know
> the exact usecase when this happens but
> 
> I saw tons of pipe error without this.

Okay it is good to know. 

I don't see obvious issue of this patch. Acked-by: Oak Zeng <oak.zeng@intel.com>. Better someone else also review it.

Oak
> 
> 
> Regards,
> 
> Nirmoy
> 
> >
> > Oak
> >
> >> +		} else {
> >> +			memset64((u64 *)cs, pte, n_ptes);
> >> +			cs += n_ptes * 2;
> >> +		}
> >> +
> >> +		intel_ring_advance(rq, cs);
> >> +queue_err_rq:
> >> +		i915_request_get(rq);
> >> +		__i915_request_commit(rq);
> >> +		__i915_request_queue(rq, &attr);
> >> +
> >> +		mutex_unlock(&ce->timeline->mutex);
> >> +		/* This will break if the request is complete or after engine reset
> >> */
> >> +		i915_request_wait(rq, 0, MAX_SCHEDULE_TIMEOUT);
> >> +		if (rq->fence.error)
> >> +			goto err_rq;
> >> +
> >> +		i915_request_put(rq);
> >> +
> >> +		num_entries -= n_ptes;
> >> +		offset += n_ptes;
> >> +	}
> >> +
> >> +	gen8_ggtt_bind_put_ce(ce);
> >> +	return true;
> >> +
> >> +err_rq:
> >> +	i915_request_put(rq);
> >> +put_ce:
> >> +	gen8_ggtt_bind_put_ce(ce);
> >> +	return false;
> >> +}
> >> +
> >>   static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
> >>   {
> >>   	writeq(pte, addr);
> >> @@ -272,6 +416,21 @@ static void gen8_ggtt_insert_page(struct
> >> i915_address_space *vm,
> >>   	ggtt->invalidate(ggtt);
> >>   }
> >>
> >> +static void gen8_ggtt_insert_page_bind(struct i915_address_space *vm,
> >> +				       dma_addr_t addr, u64 offset,
> >> +				       unsigned int pat_index, u32 flags)
> >> +{
> >> +	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
> >> +	gen8_pte_t pte;
> >> +
> >> +	pte = ggtt->vm.pte_encode(addr, pat_index, flags);
> >> +	if (should_update_ggtt_with_bind(i915_vm_to_ggtt(vm)) &&
> >> +	    gen8_ggtt_bind_ptes(ggtt, offset, NULL, 1, pte))
> >> +		return ggtt->invalidate(ggtt);
> >> +
> >> +	gen8_ggtt_insert_page(vm, addr, offset, pat_index, flags);
> >> +}
> >> +
> >>   static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
> >>   				     struct i915_vma_resource *vma_res,
> >>   				     unsigned int pat_index,
> >> @@ -311,6 +470,50 @@ static void gen8_ggtt_insert_entries(struct
> >> i915_address_space *vm,
> >>   	ggtt->invalidate(ggtt);
> >>   }
> >>
> >> +static bool __gen8_ggtt_insert_entries_bind(struct i915_address_space *vm,
> >> +					    struct i915_vma_resource *vma_res,
> >> +					    unsigned int pat_index, u32 flags)
> >> +{
> >> +	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
> >> +	gen8_pte_t scratch_pte = vm->scratch[0]->encode;
> >> +	gen8_pte_t pte_encode;
> >> +	u64 start, end;
> >> +
> >> +	pte_encode = ggtt->vm.pte_encode(0, pat_index, flags);
> >> +	start = (vma_res->start - vma_res->guard) / I915_GTT_PAGE_SIZE;
> >> +	end = start + vma_res->guard / I915_GTT_PAGE_SIZE;
> >> +	if (!gen8_ggtt_bind_ptes(ggtt, start, NULL, end - start, scratch_pte))
> >> +		goto err;
> >> +
> >> +	start = end;
> >> +	end += (vma_res->node_size + vma_res->guard) / I915_GTT_PAGE_SIZE;
> >> +	if (!gen8_ggtt_bind_ptes(ggtt, start, vma_res->bi.pages,
> >> +	      vma_res->node_size / I915_GTT_PAGE_SIZE, pte_encode))
> >> +		goto err;
> >> +
> >> +	start += vma_res->node_size / I915_GTT_PAGE_SIZE;
> >> +	if (!gen8_ggtt_bind_ptes(ggtt, start, NULL, end - start, scratch_pte))
> >> +		goto err;
> >> +
> >> +	return true;
> >> +
> >> +err:
> >> +	return false;
> >> +}
> >> +
> >> +static void gen8_ggtt_insert_entries_bind(struct i915_address_space *vm,
> >> +					  struct i915_vma_resource *vma_res,
> >> +					  unsigned int pat_index, u32 flags)
> >> +{
> >> +	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
> >> +
> >> +	if (should_update_ggtt_with_bind(i915_vm_to_ggtt(vm)) &&
> >> +	    __gen8_ggtt_insert_entries_bind(vm, vma_res, pat_index, flags))
> >> +		return ggtt->invalidate(ggtt);
> >> +
> >> +	gen8_ggtt_insert_entries(vm, vma_res, pat_index, flags);
> >> +}
> >> +
> >>   static void gen8_ggtt_clear_range(struct i915_address_space *vm,
> >>   				  u64 start, u64 length)
> >>   {
> >> @@ -332,6 +535,27 @@ static void gen8_ggtt_clear_range(struct
> >> i915_address_space *vm,
> >>   		gen8_set_pte(&gtt_base[i], scratch_pte);
> >>   }
> >>
> >> +static void gen8_ggtt_scratch_range_bind(struct i915_address_space *vm,
> >> +					 u64 start, u64 length)
> >> +{
> >> +	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
> >> +	unsigned int first_entry = start / I915_GTT_PAGE_SIZE;
> >> +	unsigned int num_entries = length / I915_GTT_PAGE_SIZE;
> >> +	const gen8_pte_t scratch_pte = vm->scratch[0]->encode;
> >> +	const int max_entries = ggtt_total_entries(ggtt) - first_entry;
> >> +
> >> +	if (WARN(num_entries > max_entries,
> >> +		 "First entry = %d; Num entries = %d (max=%d)\n",
> >> +		 first_entry, num_entries, max_entries))
> >> +		num_entries = max_entries;
> >> +
> >> +	if (should_update_ggtt_with_bind(ggtt) && gen8_ggtt_bind_ptes(ggtt,
> >> first_entry,
> >> +	     NULL, num_entries, scratch_pte))
> >> +		return ggtt->invalidate(ggtt);
> >> +
> >> +	gen8_ggtt_clear_range(vm, start, length);
> >> +}
> >> +
> >>   static void gen6_ggtt_insert_page(struct i915_address_space *vm,
> >>   				  dma_addr_t addr,
> >>   				  u64 offset,
> >> @@ -997,6 +1221,17 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
> >>   			I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND;
> >>   	}
> >>
> >> +	if (i915_ggtt_require_binder(i915)) {
> >> +		ggtt->vm.scratch_range = gen8_ggtt_scratch_range_bind;
> >> +		ggtt->vm.insert_page = gen8_ggtt_insert_page_bind;
> >> +		ggtt->vm.insert_entries = gen8_ggtt_insert_entries_bind;
> >> +		/*
> >> +		 * On GPU is hung, we might bind VMAs for error capture.
> >> +		 * Fallback to CPU GGTT updates in that case.
> >> +		 */
> >> +		ggtt->vm.raw_insert_page = gen8_ggtt_insert_page;
> >> +	}
> >> +
> >>   	if (intel_uc_wants_guc(&ggtt->vm.gt->uc))
> >>   		ggtt->invalidate = guc_ggtt_invalidate;
> >>   	else
> >> --
> >> 2.41.0

[Intel-gfx] [PATCH 6/7] drm/i915: Toggle binder context ready status

[Nirmoy Das]

Toggle binder context ready status when needed.

To issue gpu commands, the driver must be primed to receive
requests. Maintain binder-based GGTT update disablement until driver
probing completes. Moreover, implement a temporary disablement
of blitter prior to entering suspend, followed by re-enablement
post-resume. This is acceptable as those transition periods are
mostly single threaded.

Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
Signed-off-by: Oak Zeng <oak.zeng@intel.com>
---
 drivers/gpu/drm/i915/i915_driver.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index f8dbee7a5af7..8cc289acdb39 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -815,6 +815,7 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 	i915_welcome_messages(i915);
 
 	i915->do_release = true;
+	intel_gt_bind_context_set_ready(to_gt(i915), true);
 
 	return 0;
 
@@ -855,6 +856,7 @@ void i915_driver_remove(struct drm_i915_private *i915)
 {
 	intel_wakeref_t wakeref;
 
+	intel_gt_bind_context_set_ready(to_gt(i915), false);
 	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
 
 	i915_driver_unregister(i915);
@@ -1077,6 +1079,8 @@ static int i915_drm_suspend(struct drm_device *dev)
 	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 	pci_power_t opregion_target_state;
 
+	intel_gt_bind_context_set_ready(to_gt(dev_priv), false);
+
 	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
 
 	/* We do a lot of poking in a lot of registers, make sure they work
@@ -1264,6 +1268,7 @@ static int i915_drm_resume(struct drm_device *dev)
 	intel_gvt_resume(dev_priv);
 
 	enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
+	intel_gt_bind_context_set_ready(to_gt(dev_priv), true);
 
 	return 0;
 }
-- 
2.41.0

Re: [Intel-gfx] [PATCH 6/7] drm/i915: Toggle binder context ready status

[Jani Nikula]

On Fri, 15 Sep 2023, Nirmoy Das <nirmoy.das@intel.com> wrote:
> Toggle binder context ready status when needed.
>
> To issue gpu commands, the driver must be primed to receive
> requests. Maintain binder-based GGTT update disablement until driver
> probing completes. Moreover, implement a temporary disablement
> of blitter prior to entering suspend, followed by re-enablement
> post-resume. This is acceptable as those transition periods are
> mostly single threaded.
>
> Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
> Signed-off-by: Oak Zeng <oak.zeng@intel.com>

Not a fan of adding more gt (or gem, or display) specific details at the
top level driver hooks. The direction should be to remove stuff from
there, and move to lower levels.

The top level functions have become really hard to understand because we
don't know the ordering constraints. This adds more constraints, and
looks like very specific and complicated ones too.

BR,
Jani.


> ---
>  drivers/gpu/drm/i915/i915_driver.c | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> index f8dbee7a5af7..8cc289acdb39 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -815,6 +815,7 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
>  	i915_welcome_messages(i915);
>  
>  	i915->do_release = true;
> +	intel_gt_bind_context_set_ready(to_gt(i915), true);
>  
>  	return 0;
>  
> @@ -855,6 +856,7 @@ void i915_driver_remove(struct drm_i915_private *i915)
>  {
>  	intel_wakeref_t wakeref;
>  
> +	intel_gt_bind_context_set_ready(to_gt(i915), false);
>  	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
>  
>  	i915_driver_unregister(i915);
> @@ -1077,6 +1079,8 @@ static int i915_drm_suspend(struct drm_device *dev)
>  	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
>  	pci_power_t opregion_target_state;
>  
> +	intel_gt_bind_context_set_ready(to_gt(dev_priv), false);
> +
>  	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
>  
>  	/* We do a lot of poking in a lot of registers, make sure they work
> @@ -1264,6 +1268,7 @@ static int i915_drm_resume(struct drm_device *dev)
>  	intel_gvt_resume(dev_priv);
>  
>  	enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
> +	intel_gt_bind_context_set_ready(to_gt(dev_priv), true);
>  
>  	return 0;
>  }

-- 
Jani Nikula, Intel

Re: [Intel-gfx] [PATCH 6/7] drm/i915: Toggle binder context ready status

[Nirmoy Das]

On 9/15/2023 11:50 AM, Jani Nikula wrote:
> On Fri, 15 Sep 2023, Nirmoy Das <nirmoy.das@intel.com> wrote:
>> Toggle binder context ready status when needed.
>>
>> To issue gpu commands, the driver must be primed to receive
>> requests. Maintain binder-based GGTT update disablement until driver
>> probing completes. Moreover, implement a temporary disablement
>> of blitter prior to entering suspend, followed by re-enablement
>> post-resume. This is acceptable as those transition periods are
>> mostly single threaded.
>>
>> Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
>> Signed-off-by: Oak Zeng <oak.zeng@intel.com>
> Not a fan of adding more gt (or gem, or display) specific details at the
> top level driver hooks. The direction should be to remove stuff from
> there, and move to lower levels.
>
> The top level functions have become really hard to understand because we
> don't know the ordering constraints. This adds more constraints, and
> looks like very specific and complicated ones too.

Tried to hook this into gt suspend/resume but didn't work well . I will 
try again.


Thanks,

Nirmoy

>
> BR,
> Jani.
>
>
>> ---
>>   drivers/gpu/drm/i915/i915_driver.c | 5 +++++
>>   1 file changed, 5 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
>> index f8dbee7a5af7..8cc289acdb39 100644
>> --- a/drivers/gpu/drm/i915/i915_driver.c
>> +++ b/drivers/gpu/drm/i915/i915_driver.c
>> @@ -815,6 +815,7 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
>>   	i915_welcome_messages(i915);
>>   
>>   	i915->do_release = true;
>> +	intel_gt_bind_context_set_ready(to_gt(i915), true);
>>   
>>   	return 0;
>>   
>> @@ -855,6 +856,7 @@ void i915_driver_remove(struct drm_i915_private *i915)
>>   {
>>   	intel_wakeref_t wakeref;
>>   
>> +	intel_gt_bind_context_set_ready(to_gt(i915), false);
>>   	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
>>   
>>   	i915_driver_unregister(i915);
>> @@ -1077,6 +1079,8 @@ static int i915_drm_suspend(struct drm_device *dev)
>>   	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
>>   	pci_power_t opregion_target_state;
>>   
>> +	intel_gt_bind_context_set_ready(to_gt(dev_priv), false);
>> +
>>   	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
>>   
>>   	/* We do a lot of poking in a lot of registers, make sure they work
>> @@ -1264,6 +1268,7 @@ static int i915_drm_resume(struct drm_device *dev)
>>   	intel_gvt_resume(dev_priv);
>>   
>>   	enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
>> +	intel_gt_bind_context_set_ready(to_gt(dev_priv), true);
>>   
>>   	return 0;
>>   }

[Intel-gfx] [PATCH 7/7] drm/i915: Enable GGTT updates with binder in MTL

[Nirmoy Das]

MTL can hang because of a HW bug while parallel reading/writing
from/to LMEM/GTTMMADR BAR so try to reduce GGTT update
related pci transactions with blitter command as recommended
for Wa_13010847436 and Wa_14019519902.

Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
Reviewed-by: Oak Zeng <oak.zeng@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gtt.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 4c89eb8d9af7..4fbed27ef0ec 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -23,7 +23,8 @@
 
 bool i915_ggtt_require_binder(struct drm_i915_private *i915)
 {
-	return false;
+	/* Wa_13010847436 & Wa_14019519902 */
+	return MEDIA_VER_FULL(i915) == IP_VER(13, 0);
 }
 
 static bool intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *i915)
-- 
2.41.0

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Update GGTT with MI_UPDATE_GTT on MTL (rev5)

[Patchwork]

== Series Details ==

Series: Update GGTT with MI_UPDATE_GTT on MTL (rev5)
URL   : https://patchwork.freedesktop.org/series/123329/
State : warning

== Summary ==

Error: dim checkpatch failed
a0021c40e766 drm/i915: Lift runtime-pm acquire callbacks out of intel_wakeref.mutex
-:57: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants
#57: FILE: drivers/gpu/drm/i915/intel_wakeref.c:27:
+		INTEL_WAKEREF_BUG_ON(wf->wakeref);

-:73: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants
#73: FILE: drivers/gpu/drm/i915/intel_wakeref.c:40:
+	INTEL_WAKEREF_BUG_ON(atomic_read(&wf->count) <= 0);

-:96: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants
#96: FILE: drivers/gpu/drm/i915/intel_wakeref.c:60:
+		INTEL_WAKEREF_BUG_ON(!wf->wakeref);

total: 0 errors, 3 warnings, 0 checks, 83 lines checked
1acfd47ecbad drm/i915: Create a kernel context for GGTT updates
2ec180291fbd drm/i915: Implement for_each_sgt_daddr_next
-:40: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__iter' - possible side-effects?
#40: FILE: drivers/gpu/drm/i915/i915_scatterlist.h:100:
+#define __for_each_daddr_next(__dp, __iter, __step)                  \
+	for (; ((__dp) = (__iter).dma + (__iter).curr), (__iter).sgp;   \
+	     (((__iter).curr += (__step)) >= (__iter).max) ?            \
+	     (__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0)

total: 0 errors, 0 warnings, 1 checks, 25 lines checked
a255746ff417 drm/i915: Parameterize binder context creation
511ca9ae60c0 drm/i915: Implement GGTT update method with MI_UPDATE_GTT
-:68: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants
#68: FILE: drivers/gpu/drm/i915/gt/intel_ggtt.c:276:
+	GEM_BUG_ON(!ce);

-:238: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#238: FILE: drivers/gpu/drm/i915/gt/intel_ggtt.c:491:
+	if (!gen8_ggtt_bind_ptes(ggtt, start, vma_res->bi.pages,
+	      vma_res->node_size / I915_GTT_PAGE_SIZE, pte_encode))

-:286: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#286: FILE: drivers/gpu/drm/i915/gt/intel_ggtt.c:553:
+	if (should_update_ggtt_with_bind(ggtt) && gen8_ggtt_bind_ptes(ggtt, first_entry,
+	     NULL, num_entries, scratch_pte))

total: 0 errors, 1 warnings, 2 checks, 283 lines checked
d6cdef709a9f drm/i915: Toggle binder context ready status
ebdb4284491b drm/i915: Enable GGTT updates with binder in MTL

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Update GGTT with MI_UPDATE_GTT on MTL (rev5)

[Patchwork]

== Series Details ==

Series: Update GGTT with MI_UPDATE_GTT on MTL (rev5)
URL   : https://patchwork.freedesktop.org/series/123329/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for Update GGTT with MI_UPDATE_GTT on MTL (rev5)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 5788 bytes --]

== Series Details ==

Series: Update GGTT with MI_UPDATE_GTT on MTL (rev5)
URL   : https://patchwork.freedesktop.org/series/123329/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13636 -> Patchwork_123329v5
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/index.html

Participating hosts (38 -> 36)
------------------------------

  Additional (1): fi-pnv-d510 
  Missing    (3): fi-kbl-8809g bat-adlp-6 fi-snb-2520m 

Known issues
------------

  Here are the changes found in Patchwork_123329v5 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live@workarounds:
    - bat-dg1-5:          [PASS][1] -> [ABORT][2] ([i915#4983])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/bat-dg1-5/igt@i915_selftest@live@workarounds.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/bat-dg1-5/igt@i915_selftest@live@workarounds.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - fi-hsw-4770:        NOTRUN -> [SKIP][3] ([fdo#109271]) +12 other tests skip
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/fi-hsw-4770/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
    - bat-dg2-11:         NOTRUN -> [SKIP][4] ([i915#1845]) +3 other tests skip
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-vga-1:
    - fi-hsw-4770:        NOTRUN -> [DMESG-WARN][5] ([i915#8841]) +6 other tests dmesg-warn
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/fi-hsw-4770/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-vga-1.html

  * igt@kms_psr@primary_page_flip:
    - fi-pnv-d510:        NOTRUN -> [SKIP][6] ([fdo#109271]) +31 other tests skip
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/fi-pnv-d510/igt@kms_psr@primary_page_flip.html

  * igt@kms_psr@sprite_plane_onoff:
    - fi-hsw-4770:        NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1072]) +3 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html

  
#### Possible fixes ####

  * igt@i915_module_load@reload:
    - bat-mtlp-8:         [DMESG-WARN][8] ([i915#1982]) -> [PASS][9]
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/bat-mtlp-8/igt@i915_module_load@reload.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/bat-mtlp-8/igt@i915_module_load@reload.html

  * igt@i915_selftest@live@mman:
    - bat-rpls-1:         [TIMEOUT][10] ([i915#6794] / [i915#7392]) -> [PASS][11]
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/bat-rpls-1/igt@i915_selftest@live@mman.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/bat-rpls-1/igt@i915_selftest@live@mman.html

  * igt@i915_suspend@basic-s2idle-without-i915:
    - bat-rpls-1:         [WARN][12] ([i915#8747]) -> [PASS][13]
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/bat-rpls-1/igt@i915_suspend@basic-s2idle-without-i915.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/bat-rpls-1/igt@i915_suspend@basic-s2idle-without-i915.html

  * igt@kms_hdmi_inject@inject-audio:
    - fi-kbl-guc:         [FAIL][14] ([IGT#3] / [i915#6121]) -> [PASS][15]
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [IGT#3]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/3
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#6121]: https://gitlab.freedesktop.org/drm/intel/issues/6121
  [i915#6794]: https://gitlab.freedesktop.org/drm/intel/issues/6794
  [i915#7392]: https://gitlab.freedesktop.org/drm/intel/issues/7392
  [i915#8747]: https://gitlab.freedesktop.org/drm/intel/issues/8747
  [i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841


Build changes
-------------

  * IGT: IGT_7489 -> IGTPW_9792
  * Linux: CI_DRM_13636 -> Patchwork_123329v5

  CI-20190529: 20190529
  CI_DRM_13636: 371f885605df83e5fd5680580b5bda86a10e7f7c @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_9792: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9792/index.html
  IGT_7489: c31111635650e76263faee031292290b1a393f2a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_123329v5: 371f885605df83e5fd5680580b5bda86a10e7f7c @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

51d129f1e0f3 drm/i915: Enable GGTT updates with binder in MTL
58aa8d4df781 drm/i915: Toggle binder context ready status
74f093686f30 drm/i915: Implement GGTT update method with MI_UPDATE_GTT
9d0930286601 drm/i915: Parameterize binder context creation
545a6a2efe42 drm/i915: Implement for_each_sgt_daddr_next
046adf7faa0d drm/i915: Create a kernel context for GGTT updates
03119b219f67 drm/i915: Lift runtime-pm acquire callbacks out of intel_wakeref.mutex

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/index.html

[-- Attachment #2: Type: text/html, Size: 6836 bytes --]

[Intel-gfx] ✗ Fi.CI.IGT: failure for Update GGTT with MI_UPDATE_GTT on MTL (rev5)

[Patchwork]

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== Series Details ==

Series: Update GGTT with MI_UPDATE_GTT on MTL (rev5)
URL   : https://patchwork.freedesktop.org/series/123329/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13636_full -> Patchwork_123329v5_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_123329v5_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_123329v5_full, please notify your bug team (lgci.bug.filing@intel.com) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 9)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_123329v5_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_exec_schedule@in-order@bcs0:
    - shard-mtlp:         NOTRUN -> [TIMEOUT][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-8/igt@gem_exec_schedule@in-order@bcs0.html

  * igt@gem_spin_batch@spin-all-new:
    - shard-mtlp:         NOTRUN -> [FAIL][2]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-8/igt@gem_spin_batch@spin-all-new.html

  
Known issues
------------

  Here are the changes found in Patchwork_123329v5_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@blit-reloc-purge-cache:
    - shard-dg2:          NOTRUN -> [SKIP][3] ([i915#8411])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-11/igt@api_intel_bb@blit-reloc-purge-cache.html

  * igt@api_intel_bb@render-ccs:
    - shard-dg2:          NOTRUN -> [FAIL][4] ([i915#6122])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-2/igt@api_intel_bb@render-ccs.html

  * igt@core_hotunplug@unbind-rebind:
    - shard-mtlp:         [PASS][5] -> [ABORT][6] ([i915#9262]) +5 other tests abort
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/shard-mtlp-6/igt@core_hotunplug@unbind-rebind.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-7/igt@core_hotunplug@unbind-rebind.html

  * igt@device_reset@cold-reset-bound:
    - shard-mtlp:         NOTRUN -> [SKIP][7] ([i915#7701])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-6/igt@device_reset@cold-reset-bound.html

  * igt@drm_buddy@drm_buddy_test:
    - shard-snb:          NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#8661])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-snb6/igt@drm_buddy@drm_buddy_test.html
    - shard-apl:          NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#8661])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-apl1/igt@drm_buddy@drm_buddy_test.html

  * igt@drm_fdinfo@all-busy-check-all:
    - shard-mtlp:         NOTRUN -> [SKIP][10] ([i915#8414]) +15 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-4/igt@drm_fdinfo@all-busy-check-all.html

  * igt@drm_fdinfo@busy-idle-check-all@vcs1:
    - shard-dg1:          NOTRUN -> [SKIP][11] ([i915#8414]) +4 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg1-12/igt@drm_fdinfo@busy-idle-check-all@vcs1.html

  * igt@drm_fdinfo@most-busy-idle-check-all@vecs1:
    - shard-dg2:          NOTRUN -> [SKIP][12] ([i915#8414]) +10 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-2/igt@drm_fdinfo@most-busy-idle-check-all@vecs1.html

  * igt@gem_ccs@ctrl-surf-copy:
    - shard-mtlp:         NOTRUN -> [SKIP][13] ([i915#3555])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-6/igt@gem_ccs@ctrl-surf-copy.html

  * igt@gem_ccs@ctrl-surf-copy-new-ctx:
    - shard-rkl:          NOTRUN -> [SKIP][14] ([i915#4098] / [i915#9323])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-rkl-7/igt@gem_ccs@ctrl-surf-copy-new-ctx.html

  * igt@gem_create@create-ext-cpu-access-sanity-check:
    - shard-mtlp:         NOTRUN -> [SKIP][15] ([i915#6335])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-3/igt@gem_create@create-ext-cpu-access-sanity-check.html

  * igt@gem_create@create-ext-set-pat:
    - shard-dg2:          NOTRUN -> [SKIP][16] ([i915#8562])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-1/igt@gem_create@create-ext-set-pat.html

  * igt@gem_ctx_exec@basic-nohangcheck:
    - shard-tglu:         [PASS][17] -> [FAIL][18] ([i915#6268])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/shard-tglu-4/igt@gem_ctx_exec@basic-nohangcheck.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-tglu-4/igt@gem_ctx_exec@basic-nohangcheck.html

  * igt@gem_ctx_persistence@heartbeat-hostile:
    - shard-dg2:          NOTRUN -> [SKIP][19] ([i915#8555]) +1 other test skip
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-10/igt@gem_ctx_persistence@heartbeat-hostile.html

  * igt@gem_ctx_persistence@heartbeat-many:
    - shard-mtlp:         NOTRUN -> [SKIP][20] ([i915#8555])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-6/igt@gem_ctx_persistence@heartbeat-many.html

  * igt@gem_ctx_persistence@legacy-engines-hang@bsd1:
    - shard-mtlp:         [PASS][21] -> [FAIL][22] ([i915#2410])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/shard-mtlp-3/igt@gem_ctx_persistence@legacy-engines-hang@bsd1.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-6/igt@gem_ctx_persistence@legacy-engines-hang@bsd1.html

  * igt@gem_ctx_persistence@legacy-engines-mixed-process:
    - shard-snb:          NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#1099])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-snb6/igt@gem_ctx_persistence@legacy-engines-mixed-process.html

  * igt@gem_ctx_sseu@mmap-args:
    - shard-mtlp:         NOTRUN -> [SKIP][24] ([i915#280])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-6/igt@gem_ctx_sseu@mmap-args.html

  * igt@gem_eio@unwedge-stress:
    - shard-dg1:          [PASS][25] -> [FAIL][26] ([i915#5784])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/shard-dg1-19/igt@gem_eio@unwedge-stress.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg1-15/igt@gem_eio@unwedge-stress.html
    - shard-mtlp:         [PASS][27] -> [FAIL][28] ([i915#3354])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/shard-mtlp-5/igt@gem_eio@unwedge-stress.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-4/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_balancer@bonded-dual:
    - shard-mtlp:         NOTRUN -> [SKIP][29] ([i915#4771])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-6/igt@gem_exec_balancer@bonded-dual.html

  * igt@gem_exec_balancer@bonded-false-hang:
    - shard-dg2:          NOTRUN -> [SKIP][30] ([i915#4812]) +1 other test skip
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-1/igt@gem_exec_balancer@bonded-false-hang.html

  * igt@gem_exec_balancer@bonded-true-hang:
    - shard-mtlp:         NOTRUN -> [SKIP][31] ([i915#4812]) +2 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-4/igt@gem_exec_balancer@bonded-true-hang.html

  * igt@gem_exec_balancer@parallel-bb-first:
    - shard-rkl:          NOTRUN -> [SKIP][32] ([i915#4525])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-rkl-1/igt@gem_exec_balancer@parallel-bb-first.html

  * igt@gem_exec_capture@capture-invisible@smem0:
    - shard-mtlp:         NOTRUN -> [SKIP][33] ([i915#6334])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-6/igt@gem_exec_capture@capture-invisible@smem0.html

  * igt@gem_exec_capture@pi@vcs0:
    - shard-mtlp:         [PASS][34] -> [FAIL][35] ([i915#4475])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/shard-mtlp-7/igt@gem_exec_capture@pi@vcs0.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-7/igt@gem_exec_capture@pi@vcs0.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - shard-rkl:          NOTRUN -> [FAIL][36] ([i915#2842])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-rkl-1/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@gem_exec_fair@basic-none-vip:
    - shard-mtlp:         NOTRUN -> [SKIP][37] ([i915#4473] / [i915#4771]) +3 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-4/igt@gem_exec_fair@basic-none-vip.html

  * igt@gem_exec_fair@basic-pace-solo:
    - shard-dg2:          NOTRUN -> [SKIP][38] ([i915#3539])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-2/igt@gem_exec_fair@basic-pace-solo.html

  * igt@gem_exec_flush@basic-uc-ro-default:
    - shard-dg2:          NOTRUN -> [SKIP][39] ([i915#3539] / [i915#4852]) +2 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-10/igt@gem_exec_flush@basic-uc-ro-default.html

  * igt@gem_exec_gttfill@multigpu-basic:
    - shard-dg2:          NOTRUN -> [SKIP][40] ([i915#7697])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-5/igt@gem_exec_gttfill@multigpu-basic.html

  * igt@gem_exec_params@rsvd2-dirt:
    - shard-mtlp:         NOTRUN -> [SKIP][41] ([i915#5107])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-1/igt@gem_exec_params@rsvd2-dirt.html
    - shard-dg2:          NOTRUN -> [SKIP][42] ([fdo#109283] / [i915#5107])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-11/igt@gem_exec_params@rsvd2-dirt.html

  * igt@gem_exec_reloc@basic-cpu-active:
    - shard-mtlp:         NOTRUN -> [SKIP][43] ([i915#3281]) +13 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-1/igt@gem_exec_reloc@basic-cpu-active.html

  * igt@gem_exec_reloc@basic-cpu-gtt-noreloc:
    - shard-dg2:          NOTRUN -> [SKIP][44] ([i915#3281]) +13 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-2/igt@gem_exec_reloc@basic-cpu-gtt-noreloc.html

  * igt@gem_exec_reloc@basic-gtt-read-active:
    - shard-rkl:          NOTRUN -> [SKIP][45] ([i915#3281]) +1 other test skip
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-rkl-2/igt@gem_exec_reloc@basic-gtt-read-active.html

  * igt@gem_exec_reloc@basic-write-gtt:
    - shard-dg1:          NOTRUN -> [SKIP][46] ([i915#3281])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg1-15/igt@gem_exec_reloc@basic-write-gtt.html

  * igt@gem_exec_schedule@deep@rcs0:
    - shard-mtlp:         NOTRUN -> [SKIP][47] ([i915#4537])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-6/igt@gem_exec_schedule@deep@rcs0.html

  * igt@gem_exec_schedule@preempt-queue-contexts:
    - shard-mtlp:         NOTRUN -> [SKIP][48] ([i915#4537] / [i915#4812]) +1 other test skip
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-1/igt@gem_exec_schedule@preempt-queue-contexts.html

  * igt@gem_exec_schedule@semaphore-resolve:
    - shard-mtlp:         NOTRUN -> [ABORT][49] ([i915#4537] / [i915#9262])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-5/igt@gem_exec_schedule@semaphore-resolve.html

  * igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible:
    - shard-dg2:          NOTRUN -> [SKIP][50] ([i915#4860])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-7/igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible.html

  * igt@gem_fenced_exec_thrash@too-many-fences:
    - shard-mtlp:         NOTRUN -> [SKIP][51] ([i915#4860]) +3 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-2/igt@gem_fenced_exec_thrash@too-many-fences.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - shard-tglu:         NOTRUN -> [SKIP][52] ([i915#4613])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-tglu-10/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_lmem_swapping@random-engines:
    - shard-rkl:          NOTRUN -> [SKIP][53] ([i915#4613]) +1 other test skip
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-rkl-1/igt@gem_lmem_swapping@random-engines.html

  * igt@gem_lmem_swapping@smem-oom:
    - shard-mtlp:         NOTRUN -> [SKIP][54] ([i915#4613]) +2 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-6/igt@gem_lmem_swapping@smem-oom.html

  * igt@gem_lmem_swapping@smem-oom@lmem0:
    - shard-dg1:          [PASS][55] -> [DMESG-WARN][56] ([i915#4936] / [i915#5493])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/shard-dg1-12/igt@gem_lmem_swapping@smem-oom@lmem0.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg1-16/igt@gem_lmem_swapping@smem-oom@lmem0.html

  * igt@gem_lmem_swapping@verify:
    - shard-apl:          NOTRUN -> [SKIP][57] ([fdo#109271] / [i915#4613])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-apl3/igt@gem_lmem_swapping@verify.html

  * igt@gem_media_vme:
    - shard-dg2:          NOTRUN -> [SKIP][58] ([i915#284])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-2/igt@gem_media_vme.html

  * igt@gem_mmap@big-bo:
    - shard-dg1:          NOTRUN -> [SKIP][59] ([i915#4083])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg1-17/igt@gem_mmap@big-bo.html

  * igt@gem_mmap_gtt@bad-object:
    - shard-dg1:          NOTRUN -> [SKIP][60] ([i915#4077]) +4 other tests skip
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg1-14/igt@gem_mmap_gtt@bad-object.html

  * igt@gem_mmap_gtt@big-bo-tiledy:
    - shard-mtlp:         NOTRUN -> [SKIP][61] ([i915#4077]) +17 other tests skip
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-6/igt@gem_mmap_gtt@big-bo-tiledy.html

  * igt@gem_mmap_gtt@cpuset-big-copy-odd:
    - shard-dg2:          NOTRUN -> [SKIP][62] ([i915#4077]) +20 other tests skip
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-11/igt@gem_mmap_gtt@cpuset-big-copy-odd.html

  * igt@gem_mmap_wc@copy:
    - shard-dg2:          NOTRUN -> [SKIP][63] ([i915#4083]) +8 other tests skip
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-11/igt@gem_mmap_wc@copy.html

  * igt@gem_mmap_wc@read-write:
    - shard-mtlp:         NOTRUN -> [SKIP][64] ([i915#4083]) +9 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-2/igt@gem_mmap_wc@read-write.html

  * igt@gem_partial_pwrite_pread@writes-after-reads:
    - shard-mtlp:         NOTRUN -> [SKIP][65] ([i915#3282]) +3 other tests skip
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-6/igt@gem_partial_pwrite_pread@writes-after-reads.html

  * igt@gem_pread@snoop:
    - shard-dg2:          NOTRUN -> [SKIP][66] ([i915#3282]) +2 other tests skip
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-7/igt@gem_pread@snoop.html
    - shard-rkl:          NOTRUN -> [SKIP][67] ([i915#3282]) +2 other tests skip
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-rkl-7/igt@gem_pread@snoop.html

  * igt@gem_pxp@create-valid-protected-context:
    - shard-mtlp:         NOTRUN -> [SKIP][68] ([i915#4270]) +3 other tests skip
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-6/igt@gem_pxp@create-valid-protected-context.html

  * igt@gem_pxp@regular-baseline-src-copy-readible:
    - shard-dg2:          NOTRUN -> [SKIP][69] ([i915#4270]) +6 other tests skip
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-11/igt@gem_pxp@regular-baseline-src-copy-readible.html
    - shard-rkl:          NOTRUN -> [SKIP][70] ([i915#4270]) +1 other test skip
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-rkl-6/igt@gem_pxp@regular-baseline-src-copy-readible.html

  * igt@gem_pxp@verify-pxp-stale-ctx-execution:
    - shard-dg1:          NOTRUN -> [SKIP][71] ([i915#4270])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg1-18/igt@gem_pxp@verify-pxp-stale-ctx-execution.html

  * igt@gem_render_copy@y-tiled-to-vebox-x-tiled:
    - shard-mtlp:         NOTRUN -> [SKIP][72] ([i915#8428]) +7 other tests skip
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-6/igt@gem_render_copy@y-tiled-to-vebox-x-tiled.html

  * igt@gem_render_tiled_blits@basic:
    - shard-dg2:          NOTRUN -> [SKIP][73] ([i915#4079]) +1 other test skip
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-3/igt@gem_render_tiled_blits@basic.html

  * igt@gem_spin_batch@spin-all-new:
    - shard-dg2:          NOTRUN -> [FAIL][74] ([i915#5889])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-11/igt@gem_spin_batch@spin-all-new.html

  * igt@gem_userptr_blits@coherency-sync:
    - shard-dg1:          NOTRUN -> [SKIP][75] ([i915#3297])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg1-18/igt@gem_userptr_blits@coherency-sync.html

  * igt@gem_userptr_blits@dmabuf-unsync:
    - shard-dg2:          NOTRUN -> [SKIP][76] ([i915#3297]) +1 other test skip
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-6/igt@gem_userptr_blits@dmabuf-unsync.html

  * igt@gem_userptr_blits@map-fixed-invalidate:
    - shard-dg2:          NOTRUN -> [SKIP][77] ([i915#3297] / [i915#4880])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-3/igt@gem_userptr_blits@map-fixed-invalidate.html

  * igt@gem_userptr_blits@map-fixed-invalidate-overlap:
    - shard-mtlp:         NOTRUN -> [SKIP][78] ([i915#3297]) +1 other test skip
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-4/igt@gem_userptr_blits@map-fixed-invalidate-overlap.html

  * igt@gem_userptr_blits@vma-merge:
    - shard-mtlp:         NOTRUN -> [FAIL][79] ([i915#3318])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-1/igt@gem_userptr_blits@vma-merge.html

  * igt@gen3_render_linear_blits:
    - shard-rkl:          NOTRUN -> [SKIP][80] ([fdo#109289]) +1 other test skip
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-rkl-2/igt@gen3_render_linear_blits.html

  * igt@gen7_exec_parse@basic-offset:
    - shard-dg2:          NOTRUN -> [SKIP][81] ([fdo#109289]) +4 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-5/igt@gen7_exec_parse@basic-offset.html

  * igt@gen7_exec_parse@load-register-reg:
    - shard-mtlp:         NOTRUN -> [SKIP][82] ([fdo#109289]) +6 other tests skip
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-2/igt@gen7_exec_parse@load-register-reg.html

  * igt@gen9_exec_parse@bb-secure:
    - shard-dg1:          NOTRUN -> [SKIP][83] ([i915#2527])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg1-14/igt@gen9_exec_parse@bb-secure.html

  * igt@gen9_exec_parse@bb-start-param:
    - shard-dg2:          NOTRUN -> [SKIP][84] ([i915#2856]) +5 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-5/igt@gen9_exec_parse@bb-start-param.html

  * igt@gen9_exec_parse@unaligned-jump:
    - shard-mtlp:         NOTRUN -> [SKIP][85] ([i915#2856]) +4 other tests skip
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-3/igt@gen9_exec_parse@unaligned-jump.html

  * igt@i915_fb_tiling:
    - shard-mtlp:         NOTRUN -> [SKIP][86] ([i915#4881])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-6/igt@i915_fb_tiling.html

  * igt@i915_hangman@detector@vcs0:
    - shard-mtlp:         NOTRUN -> [FAIL][87] ([i915#8456]) +2 other tests fail
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-2/igt@i915_hangman@detector@vcs0.html

  * igt@i915_module_load@load:
    - shard-dg1:          NOTRUN -> [SKIP][88] ([i915#6227])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg1-15/igt@i915_module_load@load.html
    - shard-dg2:          NOTRUN -> [SKIP][89] ([i915#6227])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-7/igt@i915_module_load@load.html

  * igt@i915_pm_freq_api@freq-basic-api:
    - shard-rkl:          NOTRUN -> [SKIP][90] ([i915#8399])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-rkl-6/igt@i915_pm_freq_api@freq-basic-api.html

  * igt@i915_pm_rc6_residency@rc6-idle@vcs0:
    - shard-dg1:          [PASS][91] -> [FAIL][92] ([i915#3591])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html

  * igt@i915_pm_rpm@dpms-mode-unset-lpsp:
    - shard-dg2:          [PASS][93] -> [SKIP][94] ([i915#1397])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/shard-dg2-10/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-2/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html

  * igt@i915_pm_rpm@dpms-non-lpsp:
    - shard-rkl:          [PASS][95] -> [SKIP][96] ([i915#1397]) +1 other test skip
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/shard-rkl-6/igt@i915_pm_rpm@dpms-non-lpsp.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-rkl-7/igt@i915_pm_rpm@dpms-non-lpsp.html

  * igt@i915_pm_rpm@modeset-lpsp-stress:
    - shard-dg1:          [PASS][97] -> [SKIP][98] ([i915#1397])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/shard-dg1-19/igt@i915_pm_rpm@modeset-lpsp-stress.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg1-15/igt@i915_pm_rpm@modeset-lpsp-stress.html

  * igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
    - shard-dg2:          NOTRUN -> [SKIP][99] ([i915#1397]) +1 other test skip
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-3/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html

  * igt@i915_pm_rpm@modeset-non-lpsp-stress:
    - shard-tglu:         NOTRUN -> [SKIP][100] ([fdo#111644] / [i915#1397])
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-tglu-8/igt@i915_pm_rpm@modeset-non-lpsp-stress.html

  * igt@i915_pm_rpm@modeset-pc8-residency-stress:
    - shard-rkl:          NOTRUN -> [SKIP][101] ([fdo#109506])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-rkl-7/igt@i915_pm_rpm@modeset-pc8-residency-stress.html

  * igt@i915_pm_rps@min-max-config-idle:
    - shard-dg2:          NOTRUN -> [SKIP][102] ([i915#6621]) +1 other test skip
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-11/igt@i915_pm_rps@min-max-config-idle.html

  * igt@i915_pm_rps@thresholds-idle-park@gt0:
    - shard-dg1:          NOTRUN -> [SKIP][103] ([i915#8925])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg1-18/igt@i915_pm_rps@thresholds-idle-park@gt0.html

  * igt@i915_pm_rps@thresholds-idle@gt0:
    - shard-dg2:          NOTRUN -> [SKIP][104] ([i915#8925]) +1 other test skip
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-1/igt@i915_pm_rps@thresholds-idle@gt0.html

  * igt@i915_pm_rps@waitboost:
    - shard-mtlp:         NOTRUN -> [FAIL][105] ([i915#8346])
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-5/igt@i915_pm_rps@waitboost.html

  * igt@i915_query@query-topology-known-pci-ids:
    - shard-mtlp:         NOTRUN -> [SKIP][106] ([fdo#109303])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-3/igt@i915_query@query-topology-known-pci-ids.html

  * igt@i915_query@query-topology-unsupported:
    - shard-dg2:          NOTRUN -> [SKIP][107] ([fdo#109302])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-11/igt@i915_query@query-topology-unsupported.html
    - shard-mtlp:         NOTRUN -> [SKIP][108] ([fdo#109302])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-8/igt@i915_query@query-topology-unsupported.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
    - shard-dg2:          NOTRUN -> [SKIP][109] ([i915#4215] / [i915#5190])
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-11/igt@kms_addfb_basic@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
    - shard-mtlp:         NOTRUN -> [SKIP][110] ([i915#4212]) +1 other test skip
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-7/igt@kms_addfb_basic@tile-pitch-mismatch.html

  * igt@kms_async_flips@crc@pipe-d-dp-4:
    - shard-dg2:          NOTRUN -> [FAIL][111] ([i915#8247]) +3 other tests fail
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-11/igt@kms_async_flips@crc@pipe-d-dp-4.html

  * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
    - shard-mtlp:         NOTRUN -> [SKIP][112] ([i915#404])
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-1/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html

  * igt@kms_atomic_transition@plane-all-modeset-transition:
    - shard-mtlp:         NOTRUN -> [SKIP][113] ([i915#1769] / [i915#3555])
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-8/igt@kms_atomic_transition@plane-all-modeset-transition.html

  * igt@kms_big_fb@4-tiled-16bpp-rotate-270:
    - shard-tglu:         NOTRUN -> [SKIP][114] ([fdo#111615] / [i915#5286])
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-tglu-6/igt@kms_big_fb@4-tiled-16bpp-rotate-270.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-270:
    - shard-dg2:          NOTRUN -> [SKIP][115] ([fdo#111614]) +3 other tests skip
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-7/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-0:
    - shard-rkl:          NOTRUN -> [SKIP][116] ([i915#5286])
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-rkl-2/igt@kms_big_fb@4-tiled-64bpp-rotate-0.html

  * igt@kms_big_fb@4-tiled-8bpp-rotate-90:
    - shard-dg1:          NOTRUN -> [SKIP][117] ([i915#4538] / [i915#5286]) +1 other test skip
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg1-15/igt@kms_big_fb@4-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-mtlp:         NOTRUN -> [FAIL][118] ([i915#5138])
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@x-tiled-8bpp-rotate-270:
    - shard-mtlp:         NOTRUN -> [SKIP][119] ([fdo#111614]) +3 other tests skip
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-4/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
    - shard-tglu:         [PASS][120] -> [FAIL][121] ([i915#3743])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/shard-tglu-5/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-tglu-6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
    - shard-dg2:          NOTRUN -> [SKIP][122] ([i915#5190]) +17 other tests skip
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-1/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-90:
    - shard-tglu:         NOTRUN -> [SKIP][123] ([fdo#111615]) +1 other test skip
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-tglu-8/igt@kms_big_fb@yf-tiled-16bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-8bpp-rotate-0:
    - shard-dg2:          NOTRUN -> [SKIP][124] ([i915#4538] / [i915#5190]) +6 other tests skip
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-2/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-rkl:          NOTRUN -> [SKIP][125] ([fdo#110723]) +1 other test skip
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-rkl-1/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - shard-mtlp:         NOTRUN -> [SKIP][126] ([fdo#111615]) +12 other tests skip
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-3/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_big_joiner@basic:
    - shard-mtlp:         NOTRUN -> [SKIP][127] ([i915#2705])
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-6/igt@kms_big_joiner@basic.html

  * igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_ccs:
    - shard-dg1:          NOTRUN -> [SKIP][128] ([i915#3689] / [i915#5354] / [i915#6095]) +2 other tests skip
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg1-18/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_ccs.html

  * igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
    - shard-mtlp:         NOTRUN -> [SKIP][129] ([i915#3886] / [i915#6095]) +13 other tests skip
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-5/igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-a-crc-sprite-planes-basic-4_tiled_dg2_mc_ccs:
    - shard-mtlp:         NOTRUN -> [SKIP][130] ([i915#6095]) +40 other tests skip
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-1/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-4_tiled_dg2_mc_ccs.html

  * igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_ccs:
    - shard-dg2:          NOTRUN -> [SKIP][131] ([i915#3689] / [i915#5354]) +27 other tests skip
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-7/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_ccs.html

  * igt@kms_ccs@pipe-b-bad-rotation-90-4_tiled_mtl_mc_ccs:
    - shard-rkl:          NOTRUN -> [SKIP][132] ([i915#5354] / [i915#6095]) +6 other tests skip
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-rkl-4/igt@kms_ccs@pipe-b-bad-rotation-90-4_tiled_mtl_mc_ccs.html

  * igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
    - shard-apl:          NOTRUN -> [SKIP][133] ([fdo#109271] / [i915#3886]) +1 other test skip
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-apl2/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs_cc:
    - shard-snb:          NOTRUN -> [SKIP][134] ([fdo#109271]) +335 other tests skip
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-snb6/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
    - shard-dg2:          NOTRUN -> [SKIP][135] ([i915#3689] / [i915#3886] / [i915#5354]) +13 other tests skip
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-6/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
    - shard-rkl:          NOTRUN -> [SKIP][136] ([i915#5354]) +7 other tests skip
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-rkl-7/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-d-crc-primary-rotation-180-4_tiled_dg2_rc_ccs_cc:
    - shard-tglu:         NOTRUN -> [SKIP][137] ([i915#5354] / [i915#6095]) +1 other test skip
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-tglu-7/igt@kms_ccs@pipe-d-crc-primary-rotation-180-4_tiled_dg2_rc_ccs_cc.html

  * igt@kms_ccs@pipe-d-missing-ccs-buffer-4_tiled_mtl_rc_ccs_cc:
    - shard-dg1:          NOTRUN -> [SKIP][138] ([i915#5354] / [i915#6095]) +5 other tests skip
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg1-16/igt@kms_ccs@pipe-d-missing-ccs-buffer-4_tiled_mtl_rc_ccs_cc.html

  * igt@kms_cdclk@plane-scaling@pipe-b-dp-4:
    - shard-dg2:          NOTRUN -> [SKIP][139] ([i915#4087]) +3 other tests skip
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-11/igt@kms_cdclk@plane-scaling@pipe-b-dp-4.html

  * igt@kms_chamelium_color@ctm-negative:
    - shard-dg2:          NOTRUN -> [SKIP][140] ([fdo#111827]) +3 other tests skip
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-7/igt@kms_chamelium_color@ctm-negative.html
    - shard-mtlp:         NOTRUN -> [SKIP][141] ([fdo#111827])
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-8/igt@kms_chamelium_color@ctm-negative.html

  * igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k:
    - shard-dg2:          NOTRUN -> [SKIP][142] ([i915#7828]) +13 other tests skip
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-3/igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k.html

  * igt@kms_chamelium_frames@hdmi-cmp-planar-formats:
    - shard-rkl:          NOTRUN -> [SKIP][143] ([i915#7828]) +1 other test skip
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-rkl-1/igt@kms_chamelium_frames@hdmi-cmp-planar-formats.html

  * igt@kms_chamelium_frames@vga-frame-dump:
    - shard-dg1:          NOTRUN -> [SKIP][144] ([i915#7828]) +2 other tests skip
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg1-18/igt@kms_chamelium_frames@vga-frame-dump.html

  * igt@kms_chamelium_hpd@vga-hpd-enable-disable-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][145] ([i915#7828]) +9 other tests skip
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-1/igt@kms_chamelium_hpd@vga-hpd-enable-disable-mode.html

  * igt@kms_content_protection@atomic:
    - shard-rkl:          NOTRUN -> [SKIP][146] ([i915#7118])
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-rkl-6/igt@kms_content_protection@atomic.html
    - shard-mtlp:         NOTRUN -> [SKIP][147] ([i915#6944])
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-8/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@atomic@pipe-a-dp-4:
    - shard-dg2:          NOTRUN -> [TIMEOUT][148] ([i915#7173]) +1 other test timeout
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-11/igt@kms_content_protection@atomic@pipe-a-dp-4.html

  * igt@kms_content_protection@dp-mst-lic-type-1:
    - shard-dg2:          NOTRUN -> [SKIP][149] ([i915#3299]) +1 other test skip
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-3/igt@kms_content_protection@dp-mst-lic-type-1.html

  * igt@kms_content_protection@srm:
    - shard-dg2:          NOTRUN -> [SKIP][150] ([i915#7118]) +1 other test skip
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-6/igt@kms_content_protection@srm.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-dg2:          NOTRUN -> [SKIP][151] ([i915#3359])
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-3/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_cursor_crc@cursor-offscreen-max-size:
    - shard-mtlp:         NOTRUN -> [SKIP][152] ([i915#3555] / [i915#8814])
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-1/igt@kms_cursor_crc@cursor-offscreen-max-size.html

  * igt@kms_cursor_crc@cursor-random-256x85@pipe-d-edp-1:
    - shard-mtlp:         NOTRUN -> [FAIL][153] ([i915#8787]) +1 other test fail
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-8/igt@kms_cursor_crc@cursor-random-256x85@pipe-d-edp-1.html

  * igt@kms_cursor_crc@cursor-random-32x10:
    - shard-dg1:          NOTRUN -> [SKIP][154] ([i915#3555])
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg1-12/igt@kms_cursor_crc@cursor-random-32x10.html

  * igt@kms_cursor_crc@cursor-rapid-movement-32x32:
    - shard-dg2:          NOTRUN -> [SKIP][155] ([i915#3555]) +7 other tests skip
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-2/igt@kms_cursor_crc@cursor-rapid-movement-32x32.html

  * igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy:
    - shard-dg2:          NOTRUN -> [SKIP][156] ([fdo#109274] / [i915#5354]) +3 other tests skip
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-10/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - shard-mtlp:         NOTRUN -> [SKIP][157] ([i915#4213]) +1 other test skip
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic:
    - shard-mtlp:         NOTRUN -> [SKIP][158] ([i915#3546]) +4 other tests skip
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-5/igt@kms_cursor_legacy@cursora-vs-flipb-atomic.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
    - shard-snb:          NOTRUN -> [SKIP][159] ([fdo#109271] / [fdo#111767]) +1 other test skip
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-snb1/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
    - shard-mtlp:         NOTRUN -> [SKIP][160] ([fdo#111767] / [i915#3546])
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-3/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-glk:          [PASS][161] -> [FAIL][162] ([i915#2346]) +1 other test fail
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/shard-glk7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-dg2:          NOTRUN -> [SKIP][163] ([i915#4103] / [i915#4213]) +1 other test skip
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-2/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
    - shard-dg1:          NOTRUN -> [SKIP][164] ([i915#4103] / [i915#4213])
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg1-18/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][165] ([i915#3804])
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-rkl-7/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html

  * igt@kms_draw_crc@draw-method-mmap-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][166] ([i915#8812])
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-5/igt@kms_draw_crc@draw-method-mmap-gtt.html

  * igt@kms_dsc@dsc-with-formats:
    - shard-mtlp:         NOTRUN -> [SKIP][167] ([i915#3555] / [i915#3840])
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-3/igt@kms_dsc@dsc-with-formats.html

  * igt@kms_fbcon_fbt@psr:
    - shard-dg2:          NOTRUN -> [SKIP][168] ([i915#3469]) +1 other test skip
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-1/igt@kms_fbcon_fbt@psr.html

  * igt@kms_flip@2x-absolute-wf_vblank:
    - shard-rkl:          NOTRUN -> [SKIP][169] ([fdo#111825]) +1 other test skip
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-rkl-7/igt@kms_flip@2x-absolute-wf_vblank.html

  * igt@kms_flip@2x-flip-vs-panning-vs-hang:
    - shard-dg2:          NOTRUN -> [SKIP][170] ([fdo#109274]) +7 other tests skip
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-10/igt@kms_flip@2x-flip-vs-panning-vs-hang.html

  * igt@kms_flip@2x-plain-flip:
    - shard-mtlp:         NOTRUN -> [SKIP][171] ([i915#3637]) +1 other test skip
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-8/igt@kms_flip@2x-plain-flip.html

  * igt@kms_flip@flip-vs-fences:
    - shard-mtlp:         NOTRUN -> [SKIP][172] ([i915#8381])
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-8/igt@kms_flip@flip-vs-fences.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-valid-mode:
    - shard-rkl:          NOTRUN -> [SKIP][173] ([i915#2672])
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][174] ([i915#2672] / [i915#3555]) +3 other tests skip
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][175] ([i915#2672])
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-8/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][176] ([i915#8810])
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-3/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][177] ([i915#3555] / [i915#8810])
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-3/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-valid-mode:
    - shard-dg2:          NOTRUN -> [SKIP][178] ([i915#2672]) +5 other tests skip
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-valid-mode.html

  * igt@kms_force_connector_basic@prune-stale-modes:
    - shard-dg2:          NOTRUN -> [SKIP][179] ([i915#5274])
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-6/igt@kms_force_connector_basic@prune-stale-modes.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
    - shard-dg2:          [PASS][180] -> [FAIL][181] ([i915#6880])
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/shard-dg2-7/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt:
    - shard-dg2:          NOTRUN -> [SKIP][182] ([i915#5354]) +66 other tests skip
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-3/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-render:
    - shard-dg1:          NOTRUN -> [SKIP][183] ([fdo#111825]) +4 other tests skip
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg1-16/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt:
    - shard-mtlp:         NOTRUN -> [SKIP][184] ([i915#1825]) +39 other tests skip
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-onoff:
    - shard-tglu:         NOTRUN -> [SKIP][185] ([fdo#109280])
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-tglu-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-msflip-blt:
    - shard-rkl:          NOTRUN -> [SKIP][186] ([fdo#111825] / [i915#1825]) +11 other tests skip
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-rkl-1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][187] ([i915#8708]) +24 other tests skip
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-10/igt@kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-blt:
    - shard-dg1:          NOTRUN -> [SKIP][188] ([i915#3458]) +4 other tests skip
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg1-15/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][189] ([i915#8708]) +11 other tests skip
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
    - shard-mtlp:         NOTRUN -> [SKIP][190] ([i915#5460])
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-8/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-render:
    - shard-tglu:         NOTRUN -> [SKIP][191] ([fdo#110189]) +2 other tests skip
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-tglu-5/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt:
    - shard-rkl:          NOTRUN -> [SKIP][192] ([i915#3023]) +6 other tests skip
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-rkl-2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-gtt:
    - shard-dg1:          NOTRUN -> [SKIP][193] ([i915#8708]) +3 other tests skip
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg1-12/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary:
    - shard-dg2:          NOTRUN -> [SKIP][194] ([i915#3458]) +26 other tests skip
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-11/igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary.html

  * igt@kms_hdr@static-toggle-suspend:
    - shard-dg2:          NOTRUN -> [SKIP][195] ([i915#3555] / [i915#8228]) +2 other tests skip
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-7/igt@kms_hdr@static-toggle-suspend.html
    - shard-mtlp:         NOTRUN -> [SKIP][196] ([i915#3555] / [i915#8228]) +1 other test skip
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-8/igt@kms_hdr@static-toggle-suspend.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-mtlp:         NOTRUN -> [SKIP][197] ([i915#4816])
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-1/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
    - shard-mtlp:         NOTRUN -> [ABORT][198] ([i915#9262]) +6 other tests abort
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-4/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
    - shard-mtlp:         NOTRUN -> [DMESG-WARN][199] ([i915#9262])
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-4/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html

  * igt@kms_plane_multiple@tiling-y:
    - shard-dg2:          NOTRUN -> [SKIP][200] ([i915#8806])
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-6/igt@kms_plane_multiple@tiling-y.html

  * igt@kms_plane_multiple@tiling-yf:
    - shard-rkl:          NOTRUN -> [SKIP][201] ([i915#3555]) +2 other tests skip
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-rkl-2/igt@kms_plane_multiple@tiling-yf.html
    - shard-dg2:          NOTRUN -> [SKIP][202] ([i915#3555] / [i915#8806])
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-11/igt@kms_plane_multiple@tiling-yf.html

  * igt@kms_plane_scaling@intel-max-src-size:
    - shard-mtlp:         NOTRUN -> [SKIP][203] ([i915#6953])
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-3/igt@kms_plane_scaling@intel-max-src-size.html

  * igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1:
    - shard-tglu:         [PASS][204] -> [FAIL][205] ([i915#8292])
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/shard-tglu-6/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1.html
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-tglu-9/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1.html

  * igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-3:
    - shard-dg1:          NOTRUN -> [FAIL][206] ([i915#8292])
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg1-12/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-3.html

  * igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-a-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][207] ([i915#5176]) +7 other tests skip
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-3/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-a-hdmi-a-3.html

  * igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-c-dp-1:
    - shard-apl:          NOTRUN -> [SKIP][208] ([fdo#109271]) +55 other tests skip
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-apl6/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-c-dp-1.html

  * igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-c-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][209] ([i915#5176]) +3 other tests skip
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-1/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-c-edp-1.html

  * igt@kms_plane_scaling@plane-upscale-with-rotation-20x20@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][210] ([i915#5176]) +11 other tests skip
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-rkl-7/igt@kms_plane_scaling@plane-upscale-with-rotation-20x20@pipe-a-hdmi-a-1.html

  * igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-b-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][211] ([i915#5176]) +15 other tests skip
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg1-18/igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-b-hdmi-a-4.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-c-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][212] ([i915#5235]) +7 other tests skip
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg1-16/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-c-hdmi-a-4.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-d-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][213] ([i915#5235]) +15 other tests skip
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-1/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-d-hdmi-a-3.html

  * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-d-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][214] ([i915#5235]) +19 other tests skip
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-8/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-d-edp-1.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][215] ([i915#5235]) +3 other tests skip
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-rkl-7/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-hdmi-a-1.html

  * igt@kms_prime@basic-modeset-hybrid:
    - shard-dg2:          NOTRUN -> [SKIP][216] ([i915#6524] / [i915#6805]) +1 other test skip
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-7/igt@kms_prime@basic-modeset-hybrid.html

  * igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf:
    - shard-rkl:          NOTRUN -> [SKIP][217] ([i915#658]) +1 other test skip
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-rkl-1/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-mtlp:         NOTRUN -> [SKIP][218] ([i915#4348]) +1 other test skip
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-8/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr2_su@page_flip-nv12:
    - shard-dg2:          NOTRUN -> [SKIP][219] ([i915#658]) +3 other tests skip
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-2/igt@kms_psr2_su@page_flip-nv12.html

  * igt@kms_psr2_su@page_flip-xrgb8888:
    - shard-apl:          NOTRUN -> [SKIP][220] ([fdo#109271] / [i915#658])
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-apl1/igt@kms_psr2_su@page_flip-xrgb8888.html

  * igt@kms_psr@psr2_cursor_plane_onoff:
    - shard-rkl:          NOTRUN -> [SKIP][221] ([i915#1072])
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-rkl-6/igt@kms_psr@psr2_cursor_plane_onoff.html

  * igt@kms_psr@psr2_sprite_mmap_gtt:
    - shard-dg2:          NOTRUN -> [SKIP][222] ([i915#1072]) +10 other tests skip
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-7/igt@kms_psr@psr2_sprite_mmap_gtt.html

  * igt@kms_psr@psr2_sprite_render:
    - shard-mtlp:         [PASS][223] -> [FAIL][224] ([i915#9066])
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/shard-mtlp-3/igt@kms_psr@psr2_sprite_render.html
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-7/igt@kms_psr@psr2_sprite_render.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-0:
    - shard-mtlp:         NOTRUN -> [SKIP][225] ([i915#5289])
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-8/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
    - shard-tglu:         NOTRUN -> [SKIP][226] ([fdo#111615] / [i915#5289])
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-tglu-5/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@sprite-rotation-90:
    - shard-dg2:          NOTRUN -> [SKIP][227] ([i915#4235])
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-10/igt@kms_rotation_crc@sprite-rotation-90.html
    - shard-mtlp:         NOTRUN -> [SKIP][228] ([i915#4235]) +3 other tests skip
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-6/igt@kms_rotation_crc@sprite-rotation-90.html

  * igt@kms_selftest@drm_cmdline:
    - shard-mtlp:         NOTRUN -> [SKIP][229] ([i915#8661])
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-4/igt@kms_selftest@drm_cmdline.html

  * igt@kms_selftest@framebuffer:
    - shard-rkl:          NOTRUN -> [SKIP][230] ([i915#8661])
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-rkl-7/igt@kms_selftest@framebuffer.html

  * igt@kms_setmode@basic@pipe-a-hdmi-a-1:
    - shard-snb:          NOTRUN -> [FAIL][231] ([i915#5465]) +1 other test fail
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-snb1/igt@kms_setmode@basic@pipe-a-hdmi-a-1.html

  * igt@kms_setmode@invalid-clone-single-crtc:
    - shard-mtlp:         NOTRUN -> [SKIP][232] ([i915#3555] / [i915#8809]) +1 other test skip
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-5/igt@kms_setmode@invalid-clone-single-crtc.html

  * igt@kms_sysfs_edid_timing:
    - shard-dg2:          NOTRUN -> [FAIL][233] ([IGT#2])
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-6/igt@kms_sysfs_edid_timing.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-mtlp:         NOTRUN -> [SKIP][234] ([i915#8623])
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-8/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_universal_plane@cursor-fb-leak-pipe-c:
    - shard-glk:          [PASS][235] -> [FAIL][236] ([i915#9196])
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/shard-glk9/igt@kms_universal_plane@cursor-fb-leak-pipe-c.html
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-glk1/igt@kms_universal_plane@cursor-fb-leak-pipe-c.html

  * igt@kms_vblank@pipe-c-wait-forked-busy-hang:
    - shard-rkl:          NOTRUN -> [SKIP][237] ([i915#4070] / [i915#6768])
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-rkl-2/igt@kms_vblank@pipe-c-wait-forked-busy-hang.html

  * igt@kms_vblank@pipe-d-ts-continuation-suspend:
    - shard-rkl:          NOTRUN -> [SKIP][238] ([i915#4070] / [i915#533] / [i915#6768])
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-rkl-6/igt@kms_vblank@pipe-d-ts-continuation-suspend.html

  * igt@kms_vblank@pipe-d-wait-idle:
    - shard-apl:          NOTRUN -> [SKIP][239] ([fdo#109271] / [i915#533])
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-apl3/igt@kms_vblank@pipe-d-wait-idle.html

  * igt@kms_vrr@flip-dpms:
    - shard-mtlp:         NOTRUN -> [SKIP][240] ([i915#3555] / [i915#8808])
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-4/igt@kms_vrr@flip-dpms.html

  * igt@kms_writeback@writeback-invalid-parameters:
    - shard-dg2:          NOTRUN -> [SKIP][241] ([i915#2437])
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-6/igt@kms_writeback@writeback-invalid-parameters.html

  * igt@perf@polling@1-vcs0:
    - shard-mtlp:         NOTRUN -> [FAIL][242] ([i915#9259]) +2 other tests fail
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-7/igt@perf@polling@1-vcs0.html

  * igt@perf_pmu@busy-idle-check-all@bcs0:
    - shard-mtlp:         NOTRUN -> [FAIL][243] ([i915#4521]) +2 other tests fail
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-1/igt@perf_pmu@busy-idle-check-all@bcs0.html

  * igt@perf_pmu@faulting-read@gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][244] ([i915#8440])
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-4/igt@perf_pmu@faulting-read@gtt.html

  * igt@perf_pmu@module-unload:
    - shard-dg2:          NOTRUN -> [FAIL][245] ([i915#5793] / [i915#6121])
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-7/igt@perf_pmu@module-unload.html

  * igt@perf_pmu@multi-client@ccs0:
    - shard-mtlp:         NOTRUN -> [FAIL][246] ([i915#4349]) +5 other tests fail
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-3/igt@perf_pmu@multi-client@ccs0.html

  * igt@perf_pmu@rc6-all-gts:
    - shard-mtlp:         NOTRUN -> [ABORT][247] ([i915#9268] / [i915#9335])
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-4/igt@perf_pmu@rc6-all-gts.html

  * igt@perf_pmu@rc6-suspend:
    - shard-snb:          NOTRUN -> [DMESG-WARN][248] ([i915#8841]) +2 other tests dmesg-warn
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-snb1/igt@perf_pmu@rc6-suspend.html
    - shard-mtlp:         NOTRUN -> [ABORT][249] ([i915#9268])
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-3/igt@perf_pmu@rc6-suspend.html
    - shard-dg2:          [PASS][250] -> [INCOMPLETE][251] ([i915#8772])
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/shard-dg2-2/igt@perf_pmu@rc6-suspend.html
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-5/igt@perf_pmu@rc6-suspend.html

  * igt@prime_vgem@basic-blt:
    - shard-mtlp:         NOTRUN -> [FAIL][252] ([i915#8445])
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-6/igt@prime_vgem@basic-blt.html

  * igt@prime_vgem@basic-fence-read:
    - shard-dg2:          NOTRUN -> [SKIP][253] ([i915#3291] / [i915#3708]) +1 other test skip
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-11/igt@prime_vgem@basic-fence-read.html

  * igt@prime_vgem@basic-write:
    - shard-mtlp:         NOTRUN -> [SKIP][254] ([i915#3708])
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-7/igt@prime_vgem@basic-write.html

  * igt@prime_vgem@fence-flip-hang:
    - shard-dg2:          NOTRUN -> [SKIP][255] ([i915#3708])
   [255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-10/igt@prime_vgem@fence-flip-hang.html

  * igt@tools_test@sysfs_l3_parity:
    - shard-mtlp:         NOTRUN -> [SKIP][256] ([i915#4818])
   [256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-4/igt@tools_test@sysfs_l3_parity.html

  * igt@v3d/v3d_perfmon@get-values-invalid-pad:
    - shard-mtlp:         NOTRUN -> [SKIP][257] ([i915#2575]) +14 other tests skip
   [257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-3/igt@v3d/v3d_perfmon@get-values-invalid-pad.html

  * igt@v3d/v3d_submit_cl@bad-in-sync:
    - shard-rkl:          NOTRUN -> [SKIP][258] ([fdo#109315]) +1 other test skip
   [258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-rkl-2/igt@v3d/v3d_submit_cl@bad-in-sync.html

  * igt@v3d/v3d_submit_cl@bad-multisync-extension:
    - shard-dg1:          NOTRUN -> [SKIP][259] ([i915#2575]) +2 other tests skip
   [259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg1-19/igt@v3d/v3d_submit_cl@bad-multisync-extension.html

  * igt@v3d/v3d_wait_bo@used-bo-1ns:
    - shard-dg2:          NOTRUN -> [SKIP][260] ([i915#2575]) +15 other tests skip
   [260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-2/igt@v3d/v3d_wait_bo@used-bo-1ns.html

  * igt@vc4/vc4_dmabuf_poll@poll-read-waits-until-write-done:
    - shard-rkl:          NOTRUN -> [SKIP][261] ([i915#7711]) +3 other tests skip
   [261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-rkl-2/igt@vc4/vc4_dmabuf_poll@poll-read-waits-until-write-done.html

  * igt@vc4/vc4_purgeable_bo@free-purged-bo:
    - shard-mtlp:         NOTRUN -> [SKIP][262] ([i915#7711]) +8 other tests skip
   [262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-7/igt@vc4/vc4_purgeable_bo@free-purged-bo.html

  * igt@vc4/vc4_tiling@set-bad-handle:
    - shard-dg1:          NOTRUN -> [SKIP][263] ([i915#7711]) +1 other test skip
   [263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg1-16/igt@vc4/vc4_tiling@set-bad-handle.html

  * igt@vc4/vc4_wait_bo@used-bo-1ns:
    - shard-dg2:          NOTRUN -> [SKIP][264] ([i915#7711]) +12 other tests skip
   [264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-2/igt@vc4/vc4_wait_bo@used-bo-1ns.html

  
#### Possible fixes ####

  * igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
    - shard-rkl:          [FAIL][265] ([i915#7742]) -> [PASS][266]
   [265]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/shard-rkl-7/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
   [266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-rkl-7/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html

  * igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0:
    - shard-dg2:          [INCOMPLETE][267] ([i915#7297]) -> [PASS][268]
   [267]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/shard-dg2-1/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0.html
   [268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-11/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0.html

  * igt@gem_eio@reset-stress:
    - shard-dg1:          [FAIL][269] ([i915#5784]) -> [PASS][270]
   [269]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/shard-dg1-16/igt@gem_eio@reset-stress.html
   [270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg1-18/igt@gem_eio@reset-stress.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-rkl:          [FAIL][271] ([i915#2842]) -> [PASS][272] +2 other tests pass
   [271]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/shard-rkl-4/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-rkl-1/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_spin_batch@user-each:
    - shard-mtlp:         [ABORT][273] ([i915#9121] / [i915#9262]) -> [PASS][274]
   [273]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/shard-mtlp-4/igt@gem_spin_batch@user-each.html
   [274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-5/igt@gem_spin_batch@user-each.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-apl:          [INCOMPLETE][275] -> [PASS][276]
   [275]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/shard-apl6/igt@gen9_exec_parse@allowed-single.html
   [276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-apl2/igt@gen9_exec_parse@allowed-single.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-dg2:          [DMESG-WARN][277] ([i915#7061] / [i915#8617]) -> [PASS][278]
   [277]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/shard-dg2-6/igt@i915_module_load@reload-with-fault-injection.html
   [278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-11/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_rpm@dpms-mode-unset-lpsp:
    - shard-rkl:          [SKIP][279] ([i915#1397]) -> [PASS][280]
   [279]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/shard-rkl-4/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
   [280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-rkl-7/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
    - shard-tglu:         [FAIL][281] ([i915#3743]) -> [PASS][282]
   [281]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/shard-tglu-6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
   [282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-tglu-9/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-apl:          [FAIL][283] ([i915#2346]) -> [PASS][284]
   [283]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/shard-apl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-apl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-edp-1:
    - shard-mtlp:         [ABORT][285] ([i915#9262]) -> [PASS][286] +1 other test pass
   [285]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/shard-mtlp-5/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-edp-1.html
   [286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-8/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-edp-1.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-edp-1:
    - shard-mtlp:         [DMESG-WARN][287] ([i915#9262]) -> [PASS][288] +2 other tests pass
   [287]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/shard-mtlp-5/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-edp-1.html
   [288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-mtlp-8/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-edp-1.html

  * {igt@kms_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a}:
    - shard-dg2:          [SKIP][289] ([i915#1937]) -> [PASS][290]
   [289]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/shard-dg2-3/igt@kms_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
   [290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-10/igt@kms_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html

  * igt@kms_universal_plane@cursor-fb-leak-pipe-a:
    - shard-tglu:         [FAIL][291] ([i915#9196]) -> [PASS][292]
   [291]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/shard-tglu-6/igt@kms_universal_plane@cursor-fb-leak-pipe-a.html
   [292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-tglu-9/igt@kms_universal_plane@cursor-fb-leak-pipe-a.html

  * igt@perf@enable-disable@0-rcs0:
    - shard-dg2:          [FAIL][293] ([i915#8724]) -> [PASS][294]
   [293]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/shard-dg2-11/igt@perf@enable-disable@0-rcs0.html
   [294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-5/igt@perf@enable-disable@0-rcs0.html

  
#### Warnings ####

  * igt@kms_content_protection@mei_interface:
    - shard-dg1:          [SKIP][295] ([i915#7116]) -> [SKIP][296] ([fdo#109300])
   [295]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/shard-dg1-14/igt@kms_content_protection@mei_interface.html
   [296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg1-15/igt@kms_content_protection@mei_interface.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-rkl:          [SKIP][297] ([fdo#110189] / [i915#3955]) -> [SKIP][298] ([i915#3955]) +1 other test skip
   [297]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/shard-rkl-1/igt@kms_fbcon_fbt@psr-suspend.html
   [298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-rkl-4/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_force_connector_basic@force-load-detect:
    - shard-rkl:          [SKIP][299] ([fdo#109285] / [i915#4098]) -> [SKIP][300] ([fdo#109285])
   [299]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/shard-rkl-1/igt@kms_force_connector_basic@force-load-detect.html
   [300]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-rkl-6/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-msflip-blt:
    - shard-dg1:          [SKIP][301] ([fdo#111825] / [i915#4423]) -> [SKIP][302] ([fdo#111825])
   [301]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/shard-dg1-12/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-msflip-blt.html
   [302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg1-17/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-msflip-blt.html

  * igt@kms_psr@sprite_plane_onoff:
    - shard-dg1:          [SKIP][303] ([i915#1072] / [i915#4078]) -> [SKIP][304] ([i915#1072]) +1 other test skip
   [303]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/shard-dg1-16/igt@kms_psr@sprite_plane_onoff.html
   [304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg1-14/igt@kms_psr@sprite_plane_onoff.html

  * igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem:
    - shard-dg2:          [CRASH][305] ([i915#7331]) -> [INCOMPLETE][306] ([i915#5493])
   [305]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/shard-dg2-7/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
   [306]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/shard-dg2-7/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
  [fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
  [fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
  [fdo#111767]: https://bugs.freedesktop.org/show_bug.cgi?id=111767
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
  [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
  [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
  [i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
  [i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
  [i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
  [i915#3354]: https://gitlab.freedesktop.org/drm/intel/issues/3354
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
  [i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
  [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
  [i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
  [i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4087]: https://gitlab.freedesktop.org/drm/intel/issues/4087
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
  [i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
  [i915#4348]: https://gitlab.freedesktop.org/drm/intel/issues/4348
  [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
  [i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
  [i915#4473]: https://gitlab.freedesktop.org/drm/intel/issues/4473
  [i915#4475]: https://gitlab.freedesktop.org/drm/intel/issues/4475
  [i915#4521]: https://gitlab.freedesktop.org/drm/intel/issues/4521
  [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
  [i915#4537]: https://gitlab.freedesktop.org/drm/intel/issues/4537
  [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
  [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
  [i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
  [i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818
  [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
  [i915#4854]: https://gitlab.freedesktop.org/drm/intel/issues/4854
  [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
  [i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
  [i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
  [i915#4936]: https://gitlab.freedesktop.org/drm/intel/issues/4936
  [i915#5107]: https://gitlab.freedesktop.org/drm/intel/issues/5107
  [i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#5460]: https://gitlab.freedesktop.org/drm/intel/issues/5460
  [i915#5465]: https://gitlab.freedesktop.org/drm/intel/issues/5465
  [i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
  [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
  [i915#5793]: https://gitlab.freedesktop.org/drm/intel/issues/5793
  [i915#5889]: https://gitlab.freedesktop.org/drm/intel/issues/5889
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6121]: https://gitlab.freedesktop.org/drm/intel/issues/6121
  [i915#6122]: https://gitlab.freedesktop.org/drm/intel/issues/6122
  [i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
  [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
  [i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
  [i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
  [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
  [i915#6805]: https://gitlab.freedesktop.org/drm/intel/issues/6805
  [i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
  [i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
  [i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
  [i915#7061]: https://gitlab.freedesktop.org/drm/intel/issues/7061
  [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
  [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
  [i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173
  [i915#7297]: https://gitlab.freedesktop.org/drm/intel/issues/7297
  [i915#7331]: https://gitlab.freedesktop.org/drm/intel/issues/7331
  [i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
  [i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
  [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
  [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
  [i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
  [i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
  [i915#8346]: https://gitlab.freedesktop.org/drm/intel/issues/8346
  [i915#8381]: https://gitlab.freedesktop.org/drm/intel/issues/8381
  [i915#8399]: https://gitlab.freedesktop.org/drm/intel/issues/8399
  [i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411
  [i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
  [i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428
  [i915#8440]: https://gitlab.freedesktop.org/drm/intel/issues/8440
  [i915#8445]: https://gitlab.freedesktop.org/drm/intel/issues/8445
  [i915#8456]: https://gitlab.freedesktop.org/drm/intel/issues/8456
  [i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555
  [i915#8562]: https://gitlab.freedesktop.org/drm/intel/issues/8562
  [i915#8617]: https://gitlab.freedesktop.org/drm/intel/issues/8617
  [i915#8623]: https://gitlab.freedesktop.org/drm/intel/issues/8623
  [i915#8661]: https://gitlab.freedesktop.org/drm/intel/issues/8661
  [i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
  [i915#8724]: https://gitlab.freedesktop.org/drm/intel/issues/8724
  [i915#8772]: https://gitlab.freedesktop.org/drm/intel/issues/8772
  [i915#8787]: https://gitlab.freedesktop.org/drm/intel/issues/8787
  [i915#8806]: https://gitlab.freedesktop.org/drm/intel/issues/8806
  [i915#8808]: https://gitlab.freedesktop.org/drm/intel/issues/8808
  [i915#8809]: https://gitlab.freedesktop.org/drm/intel/issues/8809
  [i915#8810]: https://gitlab.freedesktop.org/drm/intel/issues/8810
  [i915#8812]: https://gitlab.freedesktop.org/drm/intel/issues/8812
  [i915#8814]: https://gitlab.freedesktop.org/drm/intel/issues/8814
  [i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841
  [i915#8925]: https://gitlab.freedesktop.org/drm/intel/issues/8925
  [i915#9066]: https://gitlab.freedesktop.org/drm/intel/issues/9066
  [i915#9067]: https://gitlab.freedesktop.org/drm/intel/issues/9067
  [i915#9121]: https://gitlab.freedesktop.org/drm/intel/issues/9121
  [i915#9196]: https://gitlab.freedesktop.org/drm/intel/issues/9196
  [i915#9259]: https://gitlab.freedesktop.org/drm/intel/issues/9259
  [i915#9262]: https://gitlab.freedesktop.org/drm/intel/issues/9262
  [i915#9268]: https://gitlab.freedesktop.org/drm/intel/issues/9268
  [i915#9323]: https://gitlab.freedesktop.org/drm/intel/issues/9323
  [i915#9335]: https://gitlab.freedesktop.org/drm/intel/issues/9335


Build changes
-------------

  * IGT: IGT_7489 -> IGTPW_9792
  * Linux: CI_DRM_13636 -> Patchwork_123329v5

  CI-20190529: 20190529
  CI_DRM_13636: 371f885605df83e5fd5680580b5bda86a10e7f7c @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_9792: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9792/index.html
  IGT_7489: c31111635650e76263faee031292290b1a393f2a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_123329v5: 371f885605df83e5fd5680580b5bda86a10e7f7c @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v5/index.html

[-- Attachment #2: Type: text/html, Size: 104023 bytes --]

[Intel-gfx] [PATCH 0/7] Update GGTT with MI_UPDATE_GTT on MTL

[Nirmoy Das]

Implement a way to update GGTT using MI_UPDATE_GTT command 
when possible for MTL as a suggested work around for HW bugs,
Wa_13010847436 and Wa_14019519902.

v2: Fix lockdep warning related to GT wakeref vs 
    blitter engine wakeref.

v3: Rearrange patches/diffs to fix code mixups(Andi)

v4: fix ce leak(Oak)

v5: rebase & resend with new "Test-with"

Test-with: 20230918164747.30171-1-nirmoy.das@intel.com

Chris Wilson (1):
  drm/i915: Lift runtime-pm acquire callbacks out of intel_wakeref.mutex

Nirmoy Das (6):
  drm/i915: Create a kernel context for GGTT updates
  drm/i915: Implement for_each_sgt_daddr_next
  drm/i915: Parameterize binder context creation
  drm/i915: Implement GGTT update method with MI_UPDATE_GTT
  drm/i915: Toggle binder context ready status
  drm/i915: Enable GGTT updates with binder in MTL

 drivers/gpu/drm/i915/gt/intel_engine.h       |   2 +
 drivers/gpu/drm/i915/gt/intel_engine_cs.c    |  35 ++-
 drivers/gpu/drm/i915/gt/intel_engine_types.h |   3 +
 drivers/gpu/drm/i915/gt/intel_ggtt.c         | 235 +++++++++++++++++++
 drivers/gpu/drm/i915/gt/intel_gt.c           |  18 ++
 drivers/gpu/drm/i915/gt/intel_gt.h           |   2 +
 drivers/gpu/drm/i915/gt/intel_gtt.c          |   5 +
 drivers/gpu/drm/i915/gt/intel_gtt.h          |   5 +
 drivers/gpu/drm/i915/i915_driver.c           |   5 +
 drivers/gpu/drm/i915/i915_scatterlist.h      |  10 +
 drivers/gpu/drm/i915/intel_wakeref.c         |  43 ++--
 11 files changed, 340 insertions(+), 23 deletions(-)

-- 
2.41.0

[Intel-gfx] [PATCH 6/7] drm/i915: Toggle binder context ready status

[Nirmoy Das]

Toggle binder context ready status when needed.

To issue gpu commands, the driver must be primed to receive
requests. Maintain binder-based GGTT update disablement until driver
probing completes. Moreover, implement a temporary disablement
of blitter prior to entering suspend, followed by re-enablement
post-resume. This is acceptable as those transition periods are
mostly single threaded.

Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
Signed-off-by: Oak Zeng <oak.zeng@intel.com>
---
 drivers/gpu/drm/i915/i915_driver.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index e5d693904123..07e95e9ab504 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -817,6 +817,7 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 	i915_welcome_messages(i915);
 
 	i915->do_release = true;
+	intel_gt_bind_context_set_ready(to_gt(i915), true);
 
 	return 0;
 
@@ -857,6 +858,7 @@ void i915_driver_remove(struct drm_i915_private *i915)
 {
 	intel_wakeref_t wakeref;
 
+	intel_gt_bind_context_set_ready(to_gt(i915), false);
 	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
 
 	i915_driver_unregister(i915);
@@ -1079,6 +1081,8 @@ static int i915_drm_suspend(struct drm_device *dev)
 	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 	pci_power_t opregion_target_state;
 
+	intel_gt_bind_context_set_ready(to_gt(dev_priv), false);
+
 	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
 
 	/* We do a lot of poking in a lot of registers, make sure they work
@@ -1266,6 +1270,7 @@ static int i915_drm_resume(struct drm_device *dev)
 	intel_gvt_resume(dev_priv);
 
 	enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
+	intel_gt_bind_context_set_ready(to_gt(dev_priv), true);
 
 	return 0;
 }
-- 
2.41.0

Re: [Intel-gfx] [PATCH 6/7] drm/i915: Toggle binder context ready status

[Andi Shyti]

Hi Nirmoy,

[...]

> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> index e5d693904123..07e95e9ab504 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -817,6 +817,7 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
>  	i915_welcome_messages(i915);
>  
>  	i915->do_release = true;
> +	intel_gt_bind_context_set_ready(to_gt(i915), true);
>  
>  	return 0;
>  
> @@ -857,6 +858,7 @@ void i915_driver_remove(struct drm_i915_private *i915)
>  {
>  	intel_wakeref_t wakeref;
>  
> +	intel_gt_bind_context_set_ready(to_gt(i915), false);
>  	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
>  
>  	i915_driver_unregister(i915);
> @@ -1079,6 +1081,8 @@ static int i915_drm_suspend(struct drm_device *dev)
>  	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
>  	pci_power_t opregion_target_state;
>  
> +	intel_gt_bind_context_set_ready(to_gt(dev_priv), false);
> +
>  	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
>  
>  	/* We do a lot of poking in a lot of registers, make sure they work
> @@ -1266,6 +1270,7 @@ static int i915_drm_resume(struct drm_device *dev)
>  	intel_gvt_resume(dev_priv);
>  
>  	enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
> +	intel_gt_bind_context_set_ready(to_gt(dev_priv), true);

would be nice if there were inline wrappers like:

static inline void intel_gt_bind_context_set_ready(struct intel_gt *gt)
{
	__intel_gt_bind_context_set_ready(gt, true);
}

static inline void intel_gt_bind_context_set_unready(struct intel_gt *gt)
{
	__intel_gt_bind_context_set_ready(gt, gt);
}

I always had a personal dislike of booleans in arguments as they
mean very little to whoever reads them. On the other hand, set
ready to "false" is more meaningful than set unready. Your
choice.

Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> 

Andi

[Intel-gfx] [PATCH 0/7] Update GGTT with MI_UPDATE_GTT on MTL

[Nirmoy Das]

Implement a way to update GGTT using MI_UPDATE_GTT command 
when possible for MTL as a suggested work around for HW bugs,
Wa_13010847436 and Wa_14019519902.

v2: Fix lockdep warning related to GT wakeref vs 
    blitter engine wakeref.

v3: Rearrange patches/diffs to fix code mixups(Andi) 

Test-with: 20230913094252.6246-1-nirmoy.das@intel.com

Chris Wilson (1):
  drm/i915: Lift runtime-pm acquire callbacks out of intel_wakeref.mutex

Nirmoy Das (6):
  drm/i915: Create a kernel context for GGTT updates
  drm/i915: Implement for_each_sgt_daddr_next
  drm/i915: Parameterize binder context creation
  drm/i915: Implement GGTT update method with MI_UPDATE_GTT
  drm/i915: Toggle binder context ready status
  drm/i915: Enable GGTT updates with binder in MTL

 drivers/gpu/drm/i915/gt/intel_engine.h       |   2 +
 drivers/gpu/drm/i915/gt/intel_engine_cs.c    |  33 ++-
 drivers/gpu/drm/i915/gt/intel_engine_types.h |   3 +
 drivers/gpu/drm/i915/gt/intel_ggtt.c         | 235 +++++++++++++++++++
 drivers/gpu/drm/i915/gt/intel_gt.c           |  18 ++
 drivers/gpu/drm/i915/gt/intel_gt.h           |   2 +
 drivers/gpu/drm/i915/gt/intel_gtt.c          |   5 +
 drivers/gpu/drm/i915/gt/intel_gtt.h          |   5 +
 drivers/gpu/drm/i915/i915_driver.c           |   5 +
 drivers/gpu/drm/i915/i915_scatterlist.h      |  10 +
 drivers/gpu/drm/i915/intel_wakeref.c         |  43 ++--
 11 files changed, 338 insertions(+), 23 deletions(-)

-- 
2.41.0

[Intel-gfx] [PATCH 6/7] drm/i915: Toggle binder context ready status

[Nirmoy Das]

Toggle binder context ready status when needed.

To issue gpu commands, the driver must be primed to receive
requests. Maintain binder-based GGTT update disablement until driver
probing completes. Moreover, implement a temporary disablement
of blitter prior to entering suspend, followed by re-enablement
post-resume. This is acceptable as those transition periods are
mostly single threaded.

Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
Signed-off-by: Oak Zeng <oak.zeng@intel.com>
---
 drivers/gpu/drm/i915/i915_driver.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index f8dbee7a5af7..8cc289acdb39 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -815,6 +815,7 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 	i915_welcome_messages(i915);
 
 	i915->do_release = true;
+	intel_gt_bind_context_set_ready(to_gt(i915), true);
 
 	return 0;
 
@@ -855,6 +856,7 @@ void i915_driver_remove(struct drm_i915_private *i915)
 {
 	intel_wakeref_t wakeref;
 
+	intel_gt_bind_context_set_ready(to_gt(i915), false);
 	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
 
 	i915_driver_unregister(i915);
@@ -1077,6 +1079,8 @@ static int i915_drm_suspend(struct drm_device *dev)
 	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 	pci_power_t opregion_target_state;
 
+	intel_gt_bind_context_set_ready(to_gt(dev_priv), false);
+
 	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
 
 	/* We do a lot of poking in a lot of registers, make sure they work
@@ -1264,6 +1268,7 @@ static int i915_drm_resume(struct drm_device *dev)
 	intel_gvt_resume(dev_priv);
 
 	enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
+	intel_gt_bind_context_set_ready(to_gt(dev_priv), true);
 
 	return 0;
 }
-- 
2.41.0