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* [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U
@ 2022-11-30  7:46 Chaitanya Kumar Borah
  2022-11-30  7:46 ` [Intel-gfx] [RFC 1/2] drm/i915: Add RPL-U CDCLK table Chaitanya Kumar Borah
                   ` (2 more replies)
  0 siblings, 3 replies; 11+ messages in thread
From: Chaitanya Kumar Borah @ 2022-11-30  7:46 UTC (permalink / raw)
  To: intel-gfx; +Cc: ville.syrjala

A new step of 480MHz has been added on SKUs that have a RPL-U
device id. This particular step is to better support 120Hz panels.

This patchset adds a new table to include this new CDCLK
step. Details can be found in BSpec entry 55409.

In addition to identifying RPL-U device id, we need to make a
distinction between ES and QS parts as this change comes only to
QS parts. For this CPUID Brand string is used. 480Mhz step is only
supported in SKUs which does not contain the string "Genuine Intel" in
the Brand string.

Even though ES parts will be deprecated in future we are adding this
distinction since they are currently in use. However, here the question
arises if we keep this change in upstream or not as this could just be dead
code down the line. Feedbacks are appreciated on this.

Chaitanya Kumar Borah (2):
  drm/i915: Add RPL-U CDCLK table
  drm/i915: Add additional check for 480Mhz step CDCLK

 drivers/gpu/drm/i915/display/intel_cdclk.c | 53 ++++++++++++++++++++++
 1 file changed, 53 insertions(+)

-- 
2.25.1


^ permalink raw reply	[flat|nested] 11+ messages in thread

end of thread, other threads:[~2023-01-02  6:32 UTC | newest]

Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-11-30  7:46 [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U Chaitanya Kumar Borah
2022-11-30  7:46 ` [Intel-gfx] [RFC 1/2] drm/i915: Add RPL-U CDCLK table Chaitanya Kumar Borah
2022-11-30  8:28   ` Jani Nikula
2023-01-02  6:28     ` Borah, Chaitanya Kumar
2022-11-30 14:04   ` kernel test robot
2022-11-30 16:45   ` kernel test robot
2022-11-30  7:46 ` [Intel-gfx] [RFC 2/2] drm/i915: Add additional check for 480Mhz step CDCLK Chaitanya Kumar Borah
2022-11-30  8:37   ` Jani Nikula
2023-01-02  6:32     ` Borah, Chaitanya Kumar
2022-11-30 14:14   ` kernel test robot
2022-11-30 10:11 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Add new CDCLK step for RPL-U Patchwork

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