From: "Alex Bennée" <alex.bennee@linaro.org>
To: Shashi Mallela <shashi.mallela@linaro.org>
Cc: peter.maydell@linaro.org, leif@nuviainc.com, rad@semihalf.com,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH v1 1/8] hw/intc: GICv3 ITS initial framework
Date: Thu, 25 Mar 2021 17:18:20 +0000 [thread overview]
Message-ID: <87o8f7gnhy.fsf@linaro.org> (raw)
In-Reply-To: <20210323041238.133835-2-shashi.mallela@linaro.org>
Shashi Mallela <shashi.mallela@linaro.org> writes:
> Added register definitions relevant to ITS,implemented overall
> ITS device framework with stubs for ITS control and translater
> regions read/write,extended ITS common to handle mmio init between
> existing kvm device and newer qemu device.
>
> Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
> ---
<snip>
>
> typedef struct GICv3ITSState GICv3ITSState;
>
Also could we kernel-doc this function and explain when and why tops
would be NULL.
> -void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops);
> +void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops,
> + const MemoryRegionOps *tops);
>
> #define TYPE_ARM_GICV3_ITS_COMMON "arm-gicv3-its-common"
> typedef struct GICv3ITSCommonClass GICv3ITSCommonClass;
--
Alex Bennée
WARNING: multiple messages have this Message-ID (diff)
From: "Alex Bennée" <alex.bennee@linaro.org>
To: Shashi Mallela <shashi.mallela@linaro.org>
Cc: peter.maydell@linaro.org, leif@nuviainc.com,
qemu-devel@nongnu.org, qemu-arm@nongnu.org, rad@semihalf.com
Subject: Re: [PATCH v1 1/8] hw/intc: GICv3 ITS initial framework
Date: Thu, 25 Mar 2021 17:18:20 +0000 [thread overview]
Message-ID: <87o8f7gnhy.fsf@linaro.org> (raw)
In-Reply-To: <20210323041238.133835-2-shashi.mallela@linaro.org>
Shashi Mallela <shashi.mallela@linaro.org> writes:
> Added register definitions relevant to ITS,implemented overall
> ITS device framework with stubs for ITS control and translater
> regions read/write,extended ITS common to handle mmio init between
> existing kvm device and newer qemu device.
>
> Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
> ---
<snip>
>
> typedef struct GICv3ITSState GICv3ITSState;
>
Also could we kernel-doc this function and explain when and why tops
would be NULL.
> -void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops);
> +void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops,
> + const MemoryRegionOps *tops);
>
> #define TYPE_ARM_GICV3_ITS_COMMON "arm-gicv3-its-common"
> typedef struct GICv3ITSCommonClass GICv3ITSCommonClass;
--
Alex Bennée
next prev parent reply other threads:[~2021-03-25 17:19 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-23 4:12 [PATCH v1 0/8] GICv3 LPI and ITS feature implementation Shashi Mallela
2021-03-23 4:12 ` [PATCH v1 1/8] hw/intc: GICv3 ITS initial framework Shashi Mallela
2021-03-25 16:43 ` Alex Bennée
2021-03-25 16:43 ` Alex Bennée
2021-03-25 17:18 ` Alex Bennée [this message]
2021-03-25 17:18 ` Alex Bennée
2021-03-23 4:12 ` [PATCH v1 2/8] hw/intc: GICv3 ITS register definitions added Shashi Mallela
2021-03-25 19:34 ` Alex Bennée
2021-03-25 19:34 ` Alex Bennée
2021-03-31 16:48 ` shashi.mallela
2021-03-31 16:48 ` shashi.mallela
2021-03-31 23:31 ` Richard Henderson
2021-03-23 4:12 ` [PATCH v1 3/8] hw/intc: GICv3 ITS command queue framework Shashi Mallela
2021-03-23 4:12 ` [PATCH v1 4/8] hw/intc: GICv3 ITS Command processing Shashi Mallela
2021-03-23 4:12 ` [PATCH v1 5/8] hw/intc: GICv3 ITS Feature enablement Shashi Mallela
2021-03-23 4:12 ` [PATCH v1 6/8] hw/intc: GICv3 redistributor ITS processing Shashi Mallela
2021-03-23 4:12 ` [PATCH v1 7/8] hw/arm/sbsa-ref: add ITS support in SBSA GIC Shashi Mallela
2021-03-23 4:12 ` [PATCH v1 8/8] hw/arm/virt: add ITS support in virt GIC Shashi Mallela
2021-03-25 17:59 ` [PATCH v1 0/8] GICv3 LPI and ITS feature implementation Alex Bennée
2021-03-25 17:59 ` Alex Bennée
2021-03-25 19:44 ` Alex Bennée
2021-03-25 19:44 ` Alex Bennée
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