From: Marc Zyngier <maz@kernel.org>
To: Quentin Perret <qperret@google.com>
Cc: kernel-team@android.com, android-kvm@google.com,
catalin.marinas@arm.com, mate.toth-pal@arm.com, tabba@google.com,
linux-kernel@vger.kernel.org, robh+dt@kernel.org,
linux-arm-kernel@lists.infradead.org, seanjc@google.com,
will@kernel.org, kvmarm@lists.cs.columbia.edu
Subject: Re: [PATCH v6 13/38] KVM: arm64: Enable access to sanitized CPU features at EL2
Date: Mon, 22 Mar 2021 13:44:38 +0000 [thread overview]
Message-ID: <87o8fbgv5l.wl-maz@kernel.org> (raw)
In-Reply-To: <20210319100146.1149909-14-qperret@google.com>
Hi Quentin,
On Fri, 19 Mar 2021 10:01:21 +0000,
Quentin Perret <qperret@google.com> wrote:
>
> Introduce the infrastructure in KVM enabling to copy CPU feature
> registers into EL2-owned data-structures, to allow reading sanitised
> values directly at EL2 in nVHE.
>
> Given that only a subset of these features are being read by the
> hypervisor, the ones that need to be copied are to be listed under
> <asm/kvm_cpufeature.h> together with the name of the nVHE variable that
> will hold the copy. This introduces only the infrastructure enabling
> this copy. The first users will follow shortly.
>
> Signed-off-by: Quentin Perret <qperret@google.com>
> ---
> arch/arm64/include/asm/cpufeature.h | 1 +
> arch/arm64/include/asm/kvm_cpufeature.h | 22 ++++++++++++++++++++++
> arch/arm64/include/asm/kvm_host.h | 4 ++++
> arch/arm64/kernel/cpufeature.c | 13 +++++++++++++
> arch/arm64/kvm/sys_regs.c | 19 +++++++++++++++++++
> 5 files changed, 59 insertions(+)
> create mode 100644 arch/arm64/include/asm/kvm_cpufeature.h
>
> diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
> index 61177bac49fa..a85cea2cac57 100644
> --- a/arch/arm64/include/asm/cpufeature.h
> +++ b/arch/arm64/include/asm/cpufeature.h
> @@ -607,6 +607,7 @@ void check_local_cpu_capabilities(void);
>
> u64 read_sanitised_ftr_reg(u32 id);
> u64 __read_sysreg_by_encoding(u32 sys_id);
> +int copy_ftr_reg(u32 id, struct arm64_ftr_reg *dst);
>
> static inline bool cpu_supports_mixed_endian_el0(void)
> {
> diff --git a/arch/arm64/include/asm/kvm_cpufeature.h b/arch/arm64/include/asm/kvm_cpufeature.h
> new file mode 100644
> index 000000000000..3d245f96a9fe
> --- /dev/null
> +++ b/arch/arm64/include/asm/kvm_cpufeature.h
> @@ -0,0 +1,22 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (C) 2020 - Google LLC
> + * Author: Quentin Perret <qperret@google.com>
> + */
> +
> +#ifndef __ARM64_KVM_CPUFEATURE_H__
> +#define __ARM64_KVM_CPUFEATURE_H__
> +
> +#include <asm/cpufeature.h>
> +
> +#include <linux/build_bug.h>
> +
> +#if defined(__KVM_NVHE_HYPERVISOR__)
> +#define DECLARE_KVM_HYP_CPU_FTR_REG(name) extern struct arm64_ftr_reg name
> +#define DEFINE_KVM_HYP_CPU_FTR_REG(name) struct arm64_ftr_reg name
> +#else
> +#define DECLARE_KVM_HYP_CPU_FTR_REG(name) extern struct arm64_ftr_reg kvm_nvhe_sym(name)
> +#define DEFINE_KVM_HYP_CPU_FTR_REG(name) BUILD_BUG()
> +#endif
> +
> +#endif
> diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
> index 6a2031af9562..02e172dc5087 100644
> --- a/arch/arm64/include/asm/kvm_host.h
> +++ b/arch/arm64/include/asm/kvm_host.h
> @@ -740,9 +740,13 @@ void kvm_clr_pmu_events(u32 clr);
>
> void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu);
> void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu);
> +
> +void setup_kvm_el2_caps(void);
> #else
> static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {}
> static inline void kvm_clr_pmu_events(u32 clr) {}
> +
> +static inline void setup_kvm_el2_caps(void) {}
> #endif
>
> void kvm_vcpu_load_sysregs_vhe(struct kvm_vcpu *vcpu);
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index 066030717a4c..6252476e4e73 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -1154,6 +1154,18 @@ u64 read_sanitised_ftr_reg(u32 id)
> }
> EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg);
>
> +int copy_ftr_reg(u32 id, struct arm64_ftr_reg *dst)
> +{
> + struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
> +
> + if (!regp)
> + return -EINVAL;
> +
> + *dst = *regp;
> +
> + return 0;
> +}
> +
> #define read_sysreg_case(r) \
> case r: val = read_sysreg_s(r); break;
>
> @@ -2773,6 +2785,7 @@ void __init setup_cpu_features(void)
>
> setup_system_capabilities();
> setup_elf_hwcaps(arm64_elf_hwcaps);
> + setup_kvm_el2_caps();
>
> if (system_supports_32bit_el0())
> setup_elf_hwcaps(compat_elf_hwcaps);
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index 4f2f1e3145de..6c5d133689ae 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -21,6 +21,7 @@
> #include <asm/debug-monitors.h>
> #include <asm/esr.h>
> #include <asm/kvm_arm.h>
> +#include <asm/kvm_cpufeature.h>
> #include <asm/kvm_emulate.h>
> #include <asm/kvm_hyp.h>
> #include <asm/kvm_mmu.h>
> @@ -2775,3 +2776,21 @@ void kvm_sys_reg_table_init(void)
> /* Clear all higher bits. */
> cache_levels &= (1 << (i*3))-1;
> }
> +
> +#define CPU_FTR_REG_HYP_COPY(id, name) \
> + { .sys_id = id, .dst = (struct arm64_ftr_reg *)&kvm_nvhe_sym(name) }
> +struct __ftr_reg_copy_entry {
> + u32 sys_id;
> + struct arm64_ftr_reg *dst;
> +} hyp_ftr_regs[] __initdata = {
> +};
> +
> +void __init setup_kvm_el2_caps(void)
> +{
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(hyp_ftr_regs); i++) {
> + WARN(copy_ftr_reg(hyp_ftr_regs[i].sys_id, hyp_ftr_regs[i].dst),
> + "%u feature register not found\n", hyp_ftr_regs[i].sys_id);
> + }
> +}
> --
> 2.31.0.rc2.261.g7f71774620-goog
>
>
I can't say I'm thrilled with this. Actually, it is fair to say that I
don't like it at all! ;-) Copying whole structures with pointers that
make no sense at EL2 feels... wrong.
As we discussed offline, the main reason for this infrastructure is
that the read_ctr macro directly uses arm64_ftr_reg_ctrel0.sys_val
when ARM64_MISMATCHED_CACHE_TYPE is set.
One thing to realise is that with the protected mode, we can rely on
patching as there is no such thing as a "late" CPU. So by specialising
read_ctr when compiled for nVHE, we can just make it give us the final
value, provided that KVM's own __flush_dcache_area() is limited to
protected mode.
Once this problem is solved, this whole patch can mostly go, as we are
left with exactly *two* u64 quantities to be populated, something that
we can probably do in kvm_sys_reg_table_init().
I'll post some patches later today to try and explain what I have in
mind.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Quentin Perret <qperret@google.com>
Cc: catalin.marinas@arm.com, will@kernel.org, james.morse@arm.com,
julien.thierry.kdev@gmail.com, suzuki.poulose@arm.com,
android-kvm@google.com, seanjc@google.com, mate.toth-pal@arm.com,
linux-kernel@vger.kernel.org, robh+dt@kernel.org,
linux-arm-kernel@lists.infradead.org, kernel-team@android.com,
kvmarm@lists.cs.columbia.edu, tabba@google.com, ardb@kernel.org,
mark.rutland@arm.com, dbrazdil@google.com
Subject: Re: [PATCH v6 13/38] KVM: arm64: Enable access to sanitized CPU features at EL2
Date: Mon, 22 Mar 2021 13:44:38 +0000 [thread overview]
Message-ID: <87o8fbgv5l.wl-maz@kernel.org> (raw)
In-Reply-To: <20210319100146.1149909-14-qperret@google.com>
Hi Quentin,
On Fri, 19 Mar 2021 10:01:21 +0000,
Quentin Perret <qperret@google.com> wrote:
>
> Introduce the infrastructure in KVM enabling to copy CPU feature
> registers into EL2-owned data-structures, to allow reading sanitised
> values directly at EL2 in nVHE.
>
> Given that only a subset of these features are being read by the
> hypervisor, the ones that need to be copied are to be listed under
> <asm/kvm_cpufeature.h> together with the name of the nVHE variable that
> will hold the copy. This introduces only the infrastructure enabling
> this copy. The first users will follow shortly.
>
> Signed-off-by: Quentin Perret <qperret@google.com>
> ---
> arch/arm64/include/asm/cpufeature.h | 1 +
> arch/arm64/include/asm/kvm_cpufeature.h | 22 ++++++++++++++++++++++
> arch/arm64/include/asm/kvm_host.h | 4 ++++
> arch/arm64/kernel/cpufeature.c | 13 +++++++++++++
> arch/arm64/kvm/sys_regs.c | 19 +++++++++++++++++++
> 5 files changed, 59 insertions(+)
> create mode 100644 arch/arm64/include/asm/kvm_cpufeature.h
>
> diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
> index 61177bac49fa..a85cea2cac57 100644
> --- a/arch/arm64/include/asm/cpufeature.h
> +++ b/arch/arm64/include/asm/cpufeature.h
> @@ -607,6 +607,7 @@ void check_local_cpu_capabilities(void);
>
> u64 read_sanitised_ftr_reg(u32 id);
> u64 __read_sysreg_by_encoding(u32 sys_id);
> +int copy_ftr_reg(u32 id, struct arm64_ftr_reg *dst);
>
> static inline bool cpu_supports_mixed_endian_el0(void)
> {
> diff --git a/arch/arm64/include/asm/kvm_cpufeature.h b/arch/arm64/include/asm/kvm_cpufeature.h
> new file mode 100644
> index 000000000000..3d245f96a9fe
> --- /dev/null
> +++ b/arch/arm64/include/asm/kvm_cpufeature.h
> @@ -0,0 +1,22 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (C) 2020 - Google LLC
> + * Author: Quentin Perret <qperret@google.com>
> + */
> +
> +#ifndef __ARM64_KVM_CPUFEATURE_H__
> +#define __ARM64_KVM_CPUFEATURE_H__
> +
> +#include <asm/cpufeature.h>
> +
> +#include <linux/build_bug.h>
> +
> +#if defined(__KVM_NVHE_HYPERVISOR__)
> +#define DECLARE_KVM_HYP_CPU_FTR_REG(name) extern struct arm64_ftr_reg name
> +#define DEFINE_KVM_HYP_CPU_FTR_REG(name) struct arm64_ftr_reg name
> +#else
> +#define DECLARE_KVM_HYP_CPU_FTR_REG(name) extern struct arm64_ftr_reg kvm_nvhe_sym(name)
> +#define DEFINE_KVM_HYP_CPU_FTR_REG(name) BUILD_BUG()
> +#endif
> +
> +#endif
> diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
> index 6a2031af9562..02e172dc5087 100644
> --- a/arch/arm64/include/asm/kvm_host.h
> +++ b/arch/arm64/include/asm/kvm_host.h
> @@ -740,9 +740,13 @@ void kvm_clr_pmu_events(u32 clr);
>
> void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu);
> void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu);
> +
> +void setup_kvm_el2_caps(void);
> #else
> static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {}
> static inline void kvm_clr_pmu_events(u32 clr) {}
> +
> +static inline void setup_kvm_el2_caps(void) {}
> #endif
>
> void kvm_vcpu_load_sysregs_vhe(struct kvm_vcpu *vcpu);
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index 066030717a4c..6252476e4e73 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -1154,6 +1154,18 @@ u64 read_sanitised_ftr_reg(u32 id)
> }
> EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg);
>
> +int copy_ftr_reg(u32 id, struct arm64_ftr_reg *dst)
> +{
> + struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
> +
> + if (!regp)
> + return -EINVAL;
> +
> + *dst = *regp;
> +
> + return 0;
> +}
> +
> #define read_sysreg_case(r) \
> case r: val = read_sysreg_s(r); break;
>
> @@ -2773,6 +2785,7 @@ void __init setup_cpu_features(void)
>
> setup_system_capabilities();
> setup_elf_hwcaps(arm64_elf_hwcaps);
> + setup_kvm_el2_caps();
>
> if (system_supports_32bit_el0())
> setup_elf_hwcaps(compat_elf_hwcaps);
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index 4f2f1e3145de..6c5d133689ae 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -21,6 +21,7 @@
> #include <asm/debug-monitors.h>
> #include <asm/esr.h>
> #include <asm/kvm_arm.h>
> +#include <asm/kvm_cpufeature.h>
> #include <asm/kvm_emulate.h>
> #include <asm/kvm_hyp.h>
> #include <asm/kvm_mmu.h>
> @@ -2775,3 +2776,21 @@ void kvm_sys_reg_table_init(void)
> /* Clear all higher bits. */
> cache_levels &= (1 << (i*3))-1;
> }
> +
> +#define CPU_FTR_REG_HYP_COPY(id, name) \
> + { .sys_id = id, .dst = (struct arm64_ftr_reg *)&kvm_nvhe_sym(name) }
> +struct __ftr_reg_copy_entry {
> + u32 sys_id;
> + struct arm64_ftr_reg *dst;
> +} hyp_ftr_regs[] __initdata = {
> +};
> +
> +void __init setup_kvm_el2_caps(void)
> +{
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(hyp_ftr_regs); i++) {
> + WARN(copy_ftr_reg(hyp_ftr_regs[i].sys_id, hyp_ftr_regs[i].dst),
> + "%u feature register not found\n", hyp_ftr_regs[i].sys_id);
> + }
> +}
> --
> 2.31.0.rc2.261.g7f71774620-goog
>
>
I can't say I'm thrilled with this. Actually, it is fair to say that I
don't like it at all! ;-) Copying whole structures with pointers that
make no sense at EL2 feels... wrong.
As we discussed offline, the main reason for this infrastructure is
that the read_ctr macro directly uses arm64_ftr_reg_ctrel0.sys_val
when ARM64_MISMATCHED_CACHE_TYPE is set.
One thing to realise is that with the protected mode, we can rely on
patching as there is no such thing as a "late" CPU. So by specialising
read_ctr when compiled for nVHE, we can just make it give us the final
value, provided that KVM's own __flush_dcache_area() is limited to
protected mode.
Once this problem is solved, this whole patch can mostly go, as we are
left with exactly *two* u64 quantities to be populated, something that
we can probably do in kvm_sys_reg_table_init().
I'll post some patches later today to try and explain what I have in
mind.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Quentin Perret <qperret@google.com>
Cc: catalin.marinas@arm.com, will@kernel.org, james.morse@arm.com,
julien.thierry.kdev@gmail.com, suzuki.poulose@arm.com,
android-kvm@google.com, seanjc@google.com, mate.toth-pal@arm.com,
linux-kernel@vger.kernel.org, robh+dt@kernel.org,
linux-arm-kernel@lists.infradead.org, kernel-team@android.com,
kvmarm@lists.cs.columbia.edu, tabba@google.com, ardb@kernel.org,
mark.rutland@arm.com, dbrazdil@google.com
Subject: Re: [PATCH v6 13/38] KVM: arm64: Enable access to sanitized CPU features at EL2
Date: Mon, 22 Mar 2021 13:44:38 +0000 [thread overview]
Message-ID: <87o8fbgv5l.wl-maz@kernel.org> (raw)
In-Reply-To: <20210319100146.1149909-14-qperret@google.com>
Hi Quentin,
On Fri, 19 Mar 2021 10:01:21 +0000,
Quentin Perret <qperret@google.com> wrote:
>
> Introduce the infrastructure in KVM enabling to copy CPU feature
> registers into EL2-owned data-structures, to allow reading sanitised
> values directly at EL2 in nVHE.
>
> Given that only a subset of these features are being read by the
> hypervisor, the ones that need to be copied are to be listed under
> <asm/kvm_cpufeature.h> together with the name of the nVHE variable that
> will hold the copy. This introduces only the infrastructure enabling
> this copy. The first users will follow shortly.
>
> Signed-off-by: Quentin Perret <qperret@google.com>
> ---
> arch/arm64/include/asm/cpufeature.h | 1 +
> arch/arm64/include/asm/kvm_cpufeature.h | 22 ++++++++++++++++++++++
> arch/arm64/include/asm/kvm_host.h | 4 ++++
> arch/arm64/kernel/cpufeature.c | 13 +++++++++++++
> arch/arm64/kvm/sys_regs.c | 19 +++++++++++++++++++
> 5 files changed, 59 insertions(+)
> create mode 100644 arch/arm64/include/asm/kvm_cpufeature.h
>
> diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
> index 61177bac49fa..a85cea2cac57 100644
> --- a/arch/arm64/include/asm/cpufeature.h
> +++ b/arch/arm64/include/asm/cpufeature.h
> @@ -607,6 +607,7 @@ void check_local_cpu_capabilities(void);
>
> u64 read_sanitised_ftr_reg(u32 id);
> u64 __read_sysreg_by_encoding(u32 sys_id);
> +int copy_ftr_reg(u32 id, struct arm64_ftr_reg *dst);
>
> static inline bool cpu_supports_mixed_endian_el0(void)
> {
> diff --git a/arch/arm64/include/asm/kvm_cpufeature.h b/arch/arm64/include/asm/kvm_cpufeature.h
> new file mode 100644
> index 000000000000..3d245f96a9fe
> --- /dev/null
> +++ b/arch/arm64/include/asm/kvm_cpufeature.h
> @@ -0,0 +1,22 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (C) 2020 - Google LLC
> + * Author: Quentin Perret <qperret@google.com>
> + */
> +
> +#ifndef __ARM64_KVM_CPUFEATURE_H__
> +#define __ARM64_KVM_CPUFEATURE_H__
> +
> +#include <asm/cpufeature.h>
> +
> +#include <linux/build_bug.h>
> +
> +#if defined(__KVM_NVHE_HYPERVISOR__)
> +#define DECLARE_KVM_HYP_CPU_FTR_REG(name) extern struct arm64_ftr_reg name
> +#define DEFINE_KVM_HYP_CPU_FTR_REG(name) struct arm64_ftr_reg name
> +#else
> +#define DECLARE_KVM_HYP_CPU_FTR_REG(name) extern struct arm64_ftr_reg kvm_nvhe_sym(name)
> +#define DEFINE_KVM_HYP_CPU_FTR_REG(name) BUILD_BUG()
> +#endif
> +
> +#endif
> diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
> index 6a2031af9562..02e172dc5087 100644
> --- a/arch/arm64/include/asm/kvm_host.h
> +++ b/arch/arm64/include/asm/kvm_host.h
> @@ -740,9 +740,13 @@ void kvm_clr_pmu_events(u32 clr);
>
> void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu);
> void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu);
> +
> +void setup_kvm_el2_caps(void);
> #else
> static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {}
> static inline void kvm_clr_pmu_events(u32 clr) {}
> +
> +static inline void setup_kvm_el2_caps(void) {}
> #endif
>
> void kvm_vcpu_load_sysregs_vhe(struct kvm_vcpu *vcpu);
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index 066030717a4c..6252476e4e73 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -1154,6 +1154,18 @@ u64 read_sanitised_ftr_reg(u32 id)
> }
> EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg);
>
> +int copy_ftr_reg(u32 id, struct arm64_ftr_reg *dst)
> +{
> + struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
> +
> + if (!regp)
> + return -EINVAL;
> +
> + *dst = *regp;
> +
> + return 0;
> +}
> +
> #define read_sysreg_case(r) \
> case r: val = read_sysreg_s(r); break;
>
> @@ -2773,6 +2785,7 @@ void __init setup_cpu_features(void)
>
> setup_system_capabilities();
> setup_elf_hwcaps(arm64_elf_hwcaps);
> + setup_kvm_el2_caps();
>
> if (system_supports_32bit_el0())
> setup_elf_hwcaps(compat_elf_hwcaps);
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index 4f2f1e3145de..6c5d133689ae 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -21,6 +21,7 @@
> #include <asm/debug-monitors.h>
> #include <asm/esr.h>
> #include <asm/kvm_arm.h>
> +#include <asm/kvm_cpufeature.h>
> #include <asm/kvm_emulate.h>
> #include <asm/kvm_hyp.h>
> #include <asm/kvm_mmu.h>
> @@ -2775,3 +2776,21 @@ void kvm_sys_reg_table_init(void)
> /* Clear all higher bits. */
> cache_levels &= (1 << (i*3))-1;
> }
> +
> +#define CPU_FTR_REG_HYP_COPY(id, name) \
> + { .sys_id = id, .dst = (struct arm64_ftr_reg *)&kvm_nvhe_sym(name) }
> +struct __ftr_reg_copy_entry {
> + u32 sys_id;
> + struct arm64_ftr_reg *dst;
> +} hyp_ftr_regs[] __initdata = {
> +};
> +
> +void __init setup_kvm_el2_caps(void)
> +{
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(hyp_ftr_regs); i++) {
> + WARN(copy_ftr_reg(hyp_ftr_regs[i].sys_id, hyp_ftr_regs[i].dst),
> + "%u feature register not found\n", hyp_ftr_regs[i].sys_id);
> + }
> +}
> --
> 2.31.0.rc2.261.g7f71774620-goog
>
>
I can't say I'm thrilled with this. Actually, it is fair to say that I
don't like it at all! ;-) Copying whole structures with pointers that
make no sense at EL2 feels... wrong.
As we discussed offline, the main reason for this infrastructure is
that the read_ctr macro directly uses arm64_ftr_reg_ctrel0.sys_val
when ARM64_MISMATCHED_CACHE_TYPE is set.
One thing to realise is that with the protected mode, we can rely on
patching as there is no such thing as a "late" CPU. So by specialising
read_ctr when compiled for nVHE, we can just make it give us the final
value, provided that KVM's own __flush_dcache_area() is limited to
protected mode.
Once this problem is solved, this whole patch can mostly go, as we are
left with exactly *two* u64 quantities to be populated, something that
we can probably do in kvm_sys_reg_table_init().
I'll post some patches later today to try and explain what I have in
mind.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2021-03-22 13:44 UTC|newest]
Thread overview: 143+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-19 10:01 [PATCH v6 00/38] KVM: arm64: Stage-2 for the host Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` [PATCH v6 01/38] arm64: lib: Annotate {clear, copy}_page() as position-independent Quentin Perret
2021-03-19 10:01 ` [PATCH v6 01/38] arm64: lib: Annotate {clear,copy}_page() " Quentin Perret
2021-03-19 10:01 ` [PATCH v6 01/38] arm64: lib: Annotate {clear, copy}_page() " Quentin Perret
2021-03-19 10:01 ` [PATCH v6 02/38] KVM: arm64: Link position-independent string routines into .hyp.text Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` [PATCH v6 03/38] arm64: kvm: Add standalone ticket spinlock implementation for use at hyp Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` [PATCH v6 04/38] KVM: arm64: Initialize kvm_nvhe_init_params early Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` [PATCH v6 05/38] KVM: arm64: Avoid free_page() in page-table allocator Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` [PATCH v6 06/38] KVM: arm64: Factor memory allocation out of pgtable.c Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` [PATCH v6 07/38] KVM: arm64: Introduce a BSS section for use at Hyp Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` [PATCH v6 08/38] KVM: arm64: Make kvm_call_hyp() a function call " Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` [PATCH v6 09/38] KVM: arm64: Allow using kvm_nvhe_sym() in hyp code Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` [PATCH v6 10/38] KVM: arm64: Introduce an early Hyp page allocator Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` [PATCH v6 11/38] KVM: arm64: Stub CONFIG_DEBUG_LIST at Hyp Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` [PATCH v6 12/38] KVM: arm64: Introduce a Hyp buddy page allocator Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` [PATCH v6 13/38] KVM: arm64: Enable access to sanitized CPU features at EL2 Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-22 11:24 ` Will Deacon
2021-03-22 11:24 ` Will Deacon
2021-03-22 11:24 ` Will Deacon
2021-03-22 13:44 ` Marc Zyngier [this message]
2021-03-22 13:44 ` Marc Zyngier
2021-03-22 13:44 ` Marc Zyngier
2021-03-22 14:19 ` Quentin Perret
2021-03-22 14:19 ` Quentin Perret
2021-03-22 14:19 ` Quentin Perret
2021-03-19 10:01 ` [PATCH v6 14/38] KVM: arm64: Provide __flush_dcache_area " Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-22 11:25 ` Will Deacon
2021-03-22 11:25 ` Will Deacon
2021-03-22 11:25 ` Will Deacon
2021-03-19 10:01 ` [PATCH v6 15/38] KVM: arm64: Factor out vector address calculation Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` [PATCH v6 16/38] arm64: asm: Provide set_sctlr_el2 macro Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` [PATCH v6 17/38] KVM: arm64: Prepare the creation of s1 mappings at EL2 Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 13:06 ` kernel test robot
2021-03-19 10:01 ` [PATCH v6 18/38] KVM: arm64: Elevate hypervisor mappings creation " Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` [PATCH v6 19/38] KVM: arm64: Use kvm_arch for stage 2 pgtable Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` [PATCH v6 20/38] KVM: arm64: Use kvm_arch in kvm_s2_mmu Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` [PATCH v6 21/38] KVM: arm64: Set host stage 2 using kvm_nvhe_init_params Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` [PATCH v6 22/38] KVM: arm64: Refactor kvm_arm_setup_stage2() Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` [PATCH v6 23/38] KVM: arm64: Refactor __load_guest_stage2() Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` [PATCH v6 24/38] KVM: arm64: Refactor __populate_fault_info() Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` [PATCH v6 25/38] KVM: arm64: Make memcache anonymous in pgtable allocator Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` [PATCH v6 26/38] KVM: arm64: Reserve memory for host stage 2 Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` [PATCH v6 27/38] KVM: arm64: Sort the hypervisor memblocks Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` [PATCH v6 28/38] KVM: arm64: Always zero invalid PTEs Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` [PATCH v6 29/38] KVM: arm64: Use page-table to track page ownership Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-22 11:27 ` Will Deacon
2021-03-22 11:27 ` Will Deacon
2021-03-22 11:27 ` Will Deacon
2021-03-19 10:01 ` [PATCH v6 30/38] KVM: arm64: Refactor the *_map_set_prot_attr() helpers Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` [PATCH v6 31/38] KVM: arm64: Add kvm_pgtable_stage2_find_range() Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` [PATCH v6 32/38] KVM: arm64: Introduce KVM_PGTABLE_S2_NOFWB stage 2 flag Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-22 12:19 ` Will Deacon
2021-03-22 12:19 ` Will Deacon
2021-03-22 12:19 ` Will Deacon
2021-03-19 10:01 ` [PATCH v6 33/38] KVM: arm64: Introduce KVM_PGTABLE_S2_IDMAP " Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-22 11:33 ` Will Deacon
2021-03-22 11:33 ` Will Deacon
2021-03-22 11:33 ` Will Deacon
2021-03-19 10:01 ` [PATCH v6 34/38] KVM: arm64: Provide sanitized mmfr* registers at EL2 Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` [PATCH v6 35/38] KVM: arm64: Wrap the host with a stage 2 Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 13:52 ` kernel test robot
2021-03-19 10:01 ` [PATCH v6 36/38] KVM: arm64: Page-align the .hyp sections Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` [PATCH v6 37/38] KVM: arm64: Disable PMU support in protected mode Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` [PATCH v6 38/38] KVM: arm64: Protect the .hyp sections from the host Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-19 10:01 ` Quentin Perret
2021-03-25 11:13 ` [PATCH v6 00/38] KVM: arm64: Stage-2 for " Marc Zyngier
2021-03-25 11:13 ` Marc Zyngier
2021-03-25 11:13 ` Marc Zyngier
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