[PATCH v5 0/4] drm/xe/rtp: WA table context testing

[PATCH v5 0/4] drm/xe/rtp: WA table context testing

[Violet Monti]

This series adds testing for existing WA lists within
drm/xe/xe_wa.c, which previously were allowed to match
rules for contexts that were not valid at their initialization
time.

These tests function by parsing each target RTP table,
checking for invalid contexts rules determined by an
enumeration of match types, and raises an expectation fail
if an improper match is found

Signed-off-by: Violet Monti <violet.monti@intel.com>
---

Changes in v5:
- Removed code accidentally added with conflict resolution
- Removed unnecessary headers
- Link to v4: https://lore.kernel.org/intel-xe/20260526173056.967215-6-violet.monti@intel.com/

Changes in v4:
- Fix conflicts with main branch
- Link to v3: https://lore.kernel.org/intel-xe/20260522185609.2252126-6-violet.monti@intel.com/

Changes in v3:
- Removed unnecessary keywords
- Added gt_tunings[] to test cases
- Reworked tests to more easily identify an error
- Link to v2: https://lore.kernel.org/intel-xe/20260519193216.546048-6-violet.monti@intel.com/

Changes in v2:
- Cleaned up and refined code logic as per review suggestions.
- Link to v1: https://lore.kernel.org/intel-xe/20260513212129.691628-6-violet.monti@intel.com/

---

Gustavo Sousa (1):
  drm/xe/rtp: Add struct types for RTP tables

Violet Monti (3):
  drm/xe/rtp: Ensure gt_was doesn't evaluate rules with engine types
  drm/xe/rtp: Ensure oob_was does not evaluate engine type rules
  drm/xe/rtp: Ensure device_oob_was only evaluates correct rules

 drivers/gpu/drm/xe/tests/Makefile             |   1 +
 drivers/gpu/drm/xe/tests/xe_rtp_tables_test.c |  91 ++++++++++++++++
 drivers/gpu/drm/xe/tests/xe_rtp_test.c        | 101 +++++++-----------
 drivers/gpu/drm/xe/xe_hw_engine.c             |  14 ++-
 drivers/gpu/drm/xe/xe_reg_whitelist.c         |   7 +-
 drivers/gpu/drm/xe/xe_rtp.c                   |  31 +++---
 drivers/gpu/drm/xe/xe_rtp.h                   |  16 ++-
 drivers/gpu/drm/xe/xe_rtp_types.h             |  10 ++
 drivers/gpu/drm/xe/xe_tuning.c                |  46 ++++----
 drivers/gpu/drm/xe/xe_tuning.h                |   6 ++
 drivers/gpu/drm/xe/xe_wa.c                    |  92 ++++++++--------
 drivers/gpu/drm/xe/xe_wa.h                    |   7 ++
 12 files changed, 265 insertions(+), 157 deletions(-)
 create mode 100644 drivers/gpu/drm/xe/tests/xe_rtp_tables_test.c

-- 
2.43.0

[PATCH v5 1/4] drm/xe/rtp: Add struct types for RTP tables

[Violet Monti]

From: Gustavo Sousa <gustavo.sousa@intel.com>

We currently have a mixture of styles for our RTP tables with respect of
how we define the number of entries:

  * xe_rtp_process_to_sr() expects to receive the number of entries as
    arguments;
  * xe_rtp_process() expects the array to have a sentinel at the end of
    the array;
  * in xe_rtp_test.c, even though xe_rtp_process_to_sr() does not
    require a sentinel value, we need to rely on that technique to be
    able to count xe_rtp_entry_sr entries because simply using
    ARRAY_SIZE() is not possible.

The style used by xe_rtp_process_to_sr() makes it hard to share the
tables with other compilation units (e.g. kunit tests), since the number
of entries is calculated with ARRAY_SIZE(), which is done at compile
time.

Since we use the size of the tables to create some bitmasks, using a
sentinel style doesn't seem great either.

A way to reconcile things into a single style is to have a struct type
that would hold the entries array and the number of entries.  Since we
have xe_rtp_entry and xe_rtp_entry_sr, we would have one type for each.

The advantage of the proposed approach is that now we have a nice way to
share the tables directly to kunit tests with information about their
size.

v5:
    - Remove added code from conflict resolution issues

v4:
    - Removed conflicts with main branch

v3:
    - No changes

v2:
    - Add compatibility with new xe_rtp_table_sr format for
      "bad-mcr-reg-forced-to-regular" and
      "bad-regular-reg-forced-to-mcr"

Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Violet Monti <violet.monti@intel.com>
---
 drivers/gpu/drm/xe/tests/xe_rtp_test.c | 101 ++++++++++---------------
 drivers/gpu/drm/xe/xe_hw_engine.c      |  14 ++--
 drivers/gpu/drm/xe/xe_reg_whitelist.c  |   7 +-
 drivers/gpu/drm/xe/xe_rtp.c            |  31 ++++----
 drivers/gpu/drm/xe/xe_rtp.h            |  16 +++-
 drivers/gpu/drm/xe/xe_rtp_types.h      |  10 +++
 drivers/gpu/drm/xe/xe_tuning.c         |  45 +++++------
 drivers/gpu/drm/xe/xe_wa.c             |  89 ++++++++++++----------
 8 files changed, 156 insertions(+), 157 deletions(-)

diff --git a/drivers/gpu/drm/xe/tests/xe_rtp_test.c b/drivers/gpu/drm/xe/tests/xe_rtp_test.c
index 642f6e090ad0..16bf85033c0c 100644
--- a/drivers/gpu/drm/xe/tests/xe_rtp_test.c
+++ b/drivers/gpu/drm/xe/tests/xe_rtp_test.c
@@ -54,13 +54,13 @@ struct rtp_to_sr_test_case {
 	unsigned long expected_count_sr_entries;
 	unsigned int expected_sr_errors;
 	unsigned long expected_active;
-	const struct xe_rtp_entry_sr *entries;
+	const struct xe_rtp_table_sr table;
 };
 
 struct rtp_test_case {
 	const char *name;
 	unsigned long expected_active;
-	const struct xe_rtp_entry *entries;
+	const struct xe_rtp_table table;
 };
 
 static bool fake_xe_gt_mcr_check_reg(struct xe_gt *gt, struct xe_reg reg)
@@ -289,7 +289,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
 		.expected_active = BIT(0) | BIT(1),
 		.expected_count_sr_entries = 1,
 		/* Different bits on the same register: create a single entry */
-		.entries = (const struct xe_rtp_entry_sr[]) {
+		.table = XE_RTP_TABLE_SR(
 			{ XE_RTP_NAME("basic-1"),
 			  XE_RTP_RULES(FUNC(match_yes)),
 			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
@@ -298,8 +298,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
 			  XE_RTP_RULES(FUNC(match_yes)),
 			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1)))
 			},
-			{}
-		},
+		),
 	},
 	{
 		.name = "no-match-no-add",
@@ -309,7 +308,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
 		.expected_active = BIT(0),
 		.expected_count_sr_entries = 1,
 		/* Don't coalesce second entry since rules don't match */
-		.entries = (const struct xe_rtp_entry_sr[]) {
+		.table = XE_RTP_TABLE_SR(
 			{ XE_RTP_NAME("basic-1"),
 			  XE_RTP_RULES(FUNC(match_yes)),
 			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
@@ -318,8 +317,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
 			  XE_RTP_RULES(FUNC(match_no)),
 			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1)))
 			},
-			{}
-		},
+		),
 	},
 	{
 		.name = "two-regs-two-entries",
@@ -329,7 +327,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
 		.expected_active = BIT(0) | BIT(1),
 		.expected_count_sr_entries = 2,
 		/* Same bits on different registers are not coalesced */
-		.entries = (const struct xe_rtp_entry_sr[]) {
+		.table = XE_RTP_TABLE_SR(
 			{ XE_RTP_NAME("basic-1"),
 			  XE_RTP_RULES(FUNC(match_yes)),
 			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
@@ -338,8 +336,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
 			  XE_RTP_RULES(FUNC(match_yes)),
 			  XE_RTP_ACTIONS(SET(REGULAR_REG2, REG_BIT(0)))
 			},
-			{}
-		},
+		),
 	},
 	{
 		.name = "clr-one-set-other",
@@ -349,7 +346,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
 		.expected_active = BIT(0) | BIT(1),
 		.expected_count_sr_entries = 1,
 		/* Check clr vs set actions on different bits */
-		.entries = (const struct xe_rtp_entry_sr[]) {
+		.table = XE_RTP_TABLE_SR(
 			{ XE_RTP_NAME("basic-1"),
 			  XE_RTP_RULES(FUNC(match_yes)),
 			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
@@ -358,8 +355,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
 			  XE_RTP_RULES(FUNC(match_yes)),
 			  XE_RTP_ACTIONS(CLR(REGULAR_REG1, REG_BIT(1)))
 			},
-			{}
-		},
+		),
 	},
 	{
 #define TEMP_MASK	REG_GENMASK(10, 8)
@@ -371,14 +367,13 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
 		.expected_active = BIT(0),
 		.expected_count_sr_entries = 1,
 		/* Check FIELD_SET works */
-		.entries = (const struct xe_rtp_entry_sr[]) {
+		.table = XE_RTP_TABLE_SR(
 			{ XE_RTP_NAME("basic-1"),
 			  XE_RTP_RULES(FUNC(match_yes)),
 			  XE_RTP_ACTIONS(FIELD_SET(REGULAR_REG1,
 						   TEMP_MASK, TEMP_FIELD))
 			},
-			{}
-		},
+		),
 #undef TEMP_MASK
 #undef TEMP_FIELD
 	},
@@ -390,7 +385,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
 		.expected_active = BIT(0) | BIT(1),
 		.expected_count_sr_entries = 1,
 		.expected_sr_errors = 1,
-		.entries = (const struct xe_rtp_entry_sr[]) {
+		.table = XE_RTP_TABLE_SR(
 			{ XE_RTP_NAME("basic-1"),
 			  XE_RTP_RULES(FUNC(match_yes)),
 			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
@@ -400,8 +395,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
 			  XE_RTP_RULES(FUNC(match_yes)),
 			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
 			},
-			{}
-		},
+		),
 	},
 	{
 		.name = "conflict-not-disjoint",
@@ -411,7 +405,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
 		.expected_active = BIT(0) | BIT(1),
 		.expected_count_sr_entries = 1,
 		.expected_sr_errors = 1,
-		.entries = (const struct xe_rtp_entry_sr[]) {
+		.table = XE_RTP_TABLE_SR(
 			{ XE_RTP_NAME("basic-1"),
 			  XE_RTP_RULES(FUNC(match_yes)),
 			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
@@ -421,8 +415,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
 			  XE_RTP_RULES(FUNC(match_yes)),
 			  XE_RTP_ACTIONS(CLR(REGULAR_REG1, REG_GENMASK(1, 0)))
 			},
-			{}
-		},
+		),
 	},
 	{
 		.name = "conflict-reg-type",
@@ -432,7 +425,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
 		.expected_active = BIT(0) | BIT(1) | BIT(2),
 		.expected_count_sr_entries = 1,
 		.expected_sr_errors = 2,
-		.entries = (const struct xe_rtp_entry_sr[]) {
+		.table = XE_RTP_TABLE_SR(
 			{ XE_RTP_NAME("basic-1"),
 			  XE_RTP_RULES(FUNC(match_yes)),
 			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
@@ -447,8 +440,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
 			  XE_RTP_RULES(FUNC(match_yes)),
 			  XE_RTP_ACTIONS(SET(MASKED_REG1, REG_BIT(0)))
 			},
-			{}
-		},
+		),
 	},
 	{
 		.name = "bad-mcr-reg-forced-to-regular",
@@ -458,13 +450,13 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
 		.expected_active = BIT(0),
 		.expected_count_sr_entries = 1,
 		.expected_sr_errors = 1,
-		.entries = (const struct xe_rtp_entry_sr[]) {
+		.table = XE_RTP_TABLE_SR(
 			{ XE_RTP_NAME("bad-mcr-regular-reg"),
 			  XE_RTP_RULES(FUNC(match_yes)),
 			  XE_RTP_ACTIONS(SET(BAD_MCR_REG4, REG_BIT(0)))
 			},
 			{}
-		},
+		),
 	},
 	{
 		.name = "bad-regular-reg-forced-to-mcr",
@@ -474,13 +466,13 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
 		.expected_active = BIT(0),
 		.expected_count_sr_entries = 1,
 		.expected_sr_errors = 1,
-		.entries = (const struct xe_rtp_entry_sr[]) {
+		.table = XE_RTP_TABLE_SR(
 			{ XE_RTP_NAME("bad-regular-reg"),
 			  XE_RTP_RULES(FUNC(match_yes)),
 			  XE_RTP_ACTIONS(SET(BAD_REGULAR_REG5, REG_BIT(0)))
 			},
 			{}
-		},
+		),
 	},
 };
 
@@ -492,16 +484,12 @@ static void xe_rtp_process_to_sr_tests(struct kunit *test)
 	struct xe_reg_sr *reg_sr = &gt->reg_sr;
 	const struct xe_reg_sr_entry *sre, *sr_entry = NULL;
 	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
-	unsigned long idx, count_sr_entries = 0, count_rtp_entries = 0, active = 0;
+	unsigned long idx, count_sr_entries = 0, active = 0;
 
 	xe_reg_sr_init(reg_sr, "xe_rtp_to_sr_tests", xe);
 
-	while (param->entries[count_rtp_entries].rules)
-		count_rtp_entries++;
-
-	xe_rtp_process_ctx_enable_active_tracking(&ctx, &active, count_rtp_entries);
-	xe_rtp_process_to_sr(&ctx, param->entries, count_rtp_entries,
-			     reg_sr, false);
+	xe_rtp_process_ctx_enable_active_tracking(&ctx, &active, param->table.n_entries);
+	xe_rtp_process_to_sr(&ctx, &param->table, reg_sr, false);
 
 	xa_for_each(&reg_sr->xa, idx, sre) {
 		if (idx == param->expected_reg.addr)
@@ -534,56 +522,52 @@ static const struct rtp_test_case rtp_cases[] = {
 	{
 		.name = "active1",
 		.expected_active = BIT(0),
-		.entries = (const struct xe_rtp_entry[]) {
+		.table = XE_RTP_TABLE(
 			{ XE_RTP_NAME("r1"),
 			  XE_RTP_RULES(FUNC(match_yes)),
 			},
-			{}
-		},
+		),
 	},
 	{
 		.name = "active2",
 		.expected_active = BIT(0) | BIT(1),
-		.entries = (const struct xe_rtp_entry[]) {
+		.table = XE_RTP_TABLE(
 			{ XE_RTP_NAME("r1"),
 			  XE_RTP_RULES(FUNC(match_yes)),
 			},
 			{ XE_RTP_NAME("r2"),
 			  XE_RTP_RULES(FUNC(match_yes)),
 			},
-			{}
-		},
+		),
 	},
 	{
 		.name = "active-inactive",
 		.expected_active = BIT(0),
-		.entries = (const struct xe_rtp_entry[]) {
+		.table = XE_RTP_TABLE(
 			{ XE_RTP_NAME("r1"),
 			  XE_RTP_RULES(FUNC(match_yes)),
 			},
 			{ XE_RTP_NAME("r2"),
 			  XE_RTP_RULES(FUNC(match_no)),
 			},
-			{}
-		},
+		),
 	},
 	{
 		.name = "inactive-active",
 		.expected_active = BIT(1),
-		.entries = (const struct xe_rtp_entry[]) {
+		.table = XE_RTP_TABLE(
 			{ XE_RTP_NAME("r1"),
 			  XE_RTP_RULES(FUNC(match_no)),
 			},
 			{ XE_RTP_NAME("r2"),
 			  XE_RTP_RULES(FUNC(match_yes)),
 			},
-			{}
-		},
+		),
 	},
 	{
 		.name = "inactive-active-inactive",
 		.expected_active = BIT(1),
-		.entries = (const struct xe_rtp_entry[]) {
+		.table = XE_RTP_TABLE(
 			{ XE_RTP_NAME("r1"),
 			  XE_RTP_RULES(FUNC(match_no)),
 			},
@@ -593,13 +577,12 @@ static const struct rtp_test_case rtp_cases[] = {
 			{ XE_RTP_NAME("r3"),
 			  XE_RTP_RULES(FUNC(match_no)),
 			},
-			{}
-		},
+		),
 	},
 	{
 		.name = "inactive-inactive-inactive",
 		.expected_active = 0,
-		.entries = (const struct xe_rtp_entry[]) {
+		.table = XE_RTP_TABLE(
 			{ XE_RTP_NAME("r1"),
 			  XE_RTP_RULES(FUNC(match_no)),
 			},
@@ -609,8 +592,7 @@ static const struct rtp_test_case rtp_cases[] = {
 			{ XE_RTP_NAME("r3"),
 			  XE_RTP_RULES(FUNC(match_no)),
 			},
-			{}
-		},
+		),
 	},
 };
 
@@ -620,13 +602,10 @@ static void xe_rtp_process_tests(struct kunit *test)
 	struct xe_device *xe = test->priv;
 	struct xe_gt *gt = xe_device_get_root_tile(xe)->primary_gt;
 	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
-	unsigned long count_rtp_entries = 0, active = 0;
-
-	while (param->entries[count_rtp_entries].rules)
-		count_rtp_entries++;
+	unsigned long active = 0;
 
-	xe_rtp_process_ctx_enable_active_tracking(&ctx, &active, count_rtp_entries);
-	xe_rtp_process(&ctx, param->entries);
+	xe_rtp_process_ctx_enable_active_tracking(&ctx, &active, param->table.n_entries);
+	xe_rtp_process(&ctx, &param->table);
 
 	KUNIT_EXPECT_EQ(test, active, param->expected_active);
 }
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 8c66ff6f3d3c..98265293f2dc 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -346,7 +346,7 @@ hw_engine_setup_default_lrc_state(struct xe_hw_engine *hwe)
 	u32 blit_cctl_val = REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, mocs_write_idx) |
 			    REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, mocs_read_idx);
 	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
-	const struct xe_rtp_entry_sr lrc_setup[] = {
+	const struct xe_rtp_table_sr lrc_setup = XE_RTP_TABLE_SR(
 		/*
 		 * Some blitter commands do not have a field for MOCS, those
 		 * commands will use MOCS index pointed by BLIT_CCTL.
@@ -369,10 +369,9 @@ hw_engine_setup_default_lrc_state(struct xe_hw_engine *hwe)
 					   PREEMPT_GPGPU_THREAD_GROUP_LEVEL)),
 		  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE)
 		},
-	};
+	);
 
-	xe_rtp_process_to_sr(&ctx, lrc_setup, ARRAY_SIZE(lrc_setup),
-			     &hwe->reg_lrc, true);
+	xe_rtp_process_to_sr(&ctx, &lrc_setup, &hwe->reg_lrc, true);
 }
 
 void xe_hw_engine_setup_reg_lrc(struct xe_hw_engine *hwe)
@@ -408,7 +407,7 @@ hw_engine_setup_default_state(struct xe_hw_engine *hwe)
 	u32 ring_cmd_cctl_val = REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, mocs_write_idx) |
 				REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, mocs_read_idx);
 	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
-	const struct xe_rtp_entry_sr engine_entries[] = {
+	const struct xe_rtp_table_sr engine_sr = XE_RTP_TABLE_SR(
 		{ XE_RTP_NAME("RING_CMD_CCTL_default_MOCS"),
 		  XE_RTP_RULES(FUNC(xe_rtp_match_always)),
 		  XE_RTP_ACTIONS(FIELD_SET(RING_CMD_CCTL(0),
@@ -465,10 +464,9 @@ hw_engine_setup_default_state(struct xe_hw_engine *hwe)
 		  XE_RTP_ACTIONS(SET(GFX_MODE(0), GFX_MSIX_INTERRUPT_ENABLE,
 				     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
 		},
-	};
+	);
 
-	xe_rtp_process_to_sr(&ctx, engine_entries, ARRAY_SIZE(engine_entries),
-			     &hwe->reg_sr, false);
+	xe_rtp_process_to_sr(&ctx, &engine_sr, &hwe->reg_sr, false);
 }
 
 static const struct engine_info *find_engine_info(enum xe_engine_class class, int instance)
diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
index fb65940848d7..2e84b1c49f37 100644
--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
+++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
@@ -41,7 +41,7 @@ static bool match_multi_queue_class(const struct xe_device *xe,
 	return xe_gt_supports_multi_queue(gt, hwe->class);
 }
 
-static const struct xe_rtp_entry_sr register_whitelist[] = {
+static const struct xe_rtp_table_sr register_whitelist = XE_RTP_TABLE_SR(
 	{ XE_RTP_NAME("WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865"),
 	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
 	  XE_RTP_ACTIONS(WHITELIST(PS_INVOCATION_COUNT,
@@ -154,7 +154,7 @@ static const struct xe_rtp_entry_sr register_whitelist[] = {
 	  XE_RTP_RULES(FUNC(match_has_mert), ENGINE_CLASS(COPY)),
 	  XE_RTP_ACTIONS(WHITELIST_OA_MERT_MMIO_TRG)
 	},
-};
+);
 
 static void whitelist_apply_to_hwe(struct xe_hw_engine *hwe)
 {
@@ -202,8 +202,7 @@ void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe)
 {
 	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
 
-	xe_rtp_process_to_sr(&ctx, register_whitelist, ARRAY_SIZE(register_whitelist),
-			     &hwe->reg_whitelist, false);
+	xe_rtp_process_to_sr(&ctx, &register_whitelist, &hwe->reg_whitelist, false);
 	whitelist_apply_to_hwe(hwe);
 }
 
diff --git a/drivers/gpu/drm/xe/xe_rtp.c b/drivers/gpu/drm/xe/xe_rtp.c
index dec9d94e6fb0..83a40e1f9528 100644
--- a/drivers/gpu/drm/xe/xe_rtp.c
+++ b/drivers/gpu/drm/xe/xe_rtp.c
@@ -326,8 +326,7 @@ static void rtp_mark_active(struct xe_device *xe,
  * xe_rtp_process_to_sr - Process all rtp @entries, adding the matching ones to
  *                        the save-restore argument.
  * @ctx: The context for processing the table, with one of device, gt or hwe
- * @entries: Table with RTP definitions
- * @n_entries: Number of entries to process, usually ARRAY_SIZE(entries)
+ * @table: Table with RTP definitions
  * @sr: Save-restore struct where matching rules execute the action. This can be
  *      viewed as the "coalesced view" of multiple the tables. The bits for each
  *      register set are expected not to collide with previously added entries
@@ -339,12 +338,10 @@ static void rtp_mark_active(struct xe_device *xe,
  * used to calculate the right register offset
  */
 void xe_rtp_process_to_sr(struct xe_rtp_process_ctx *ctx,
-			  const struct xe_rtp_entry_sr *entries,
-			  size_t n_entries,
+			  const struct xe_rtp_table_sr *table,
 			  struct xe_reg_sr *sr,
 			  bool process_in_vf)
 {
-	const struct xe_rtp_entry_sr *entry;
 	struct xe_hw_engine *hwe = NULL;
 	struct xe_gt *gt = NULL;
 	struct xe_device *xe = NULL;
@@ -354,9 +351,10 @@ void xe_rtp_process_to_sr(struct xe_rtp_process_ctx *ctx,
 	if (!process_in_vf && IS_SRIOV_VF(xe))
 		return;
 
-	xe_assert(xe, entries);
+	xe_assert(xe, table->entries);
 
-	for (entry = entries; entry - entries < n_entries; entry++) {
+	for (size_t i = 0; i < table->n_entries; i++) {
+		const struct xe_rtp_entry_sr *entry = &table->entries[i];
 		bool match = false;
 
 		if (entry->flags & XE_RTP_ENTRY_FLAG_FOREACH_ENGINE) {
@@ -371,37 +369,40 @@ void xe_rtp_process_to_sr(struct xe_rtp_process_ctx *ctx,
 		}
 
 		if (match)
-			rtp_mark_active(xe, ctx, entry - entries);
+			rtp_mark_active(xe, ctx, i);
 	}
 }
 EXPORT_SYMBOL_IF_KUNIT(xe_rtp_process_to_sr);
 
 /**
- * xe_rtp_process - Process all rtp @entries, without running any action
+ * xe_rtp_process - Process all entries in rtp @table, without running any action
  * @ctx: The context for processing the table, with one of device, gt or hwe
- * @entries: Table with RTP definitions
+ * @table: Table with RTP definitions
  *
- * Walk the table pointed by @entries (with an empty sentinel), executing the
+ * Walk the table pointed by @table, executing the
  * rules. One difference from xe_rtp_process_to_sr(): there is no action
  * associated with each entry since this uses struct xe_rtp_entry. Its main use
  * is for marking active workarounds via
  * xe_rtp_process_ctx_enable_active_tracking().
  */
 void xe_rtp_process(struct xe_rtp_process_ctx *ctx,
-		    const struct xe_rtp_entry *entries)
+		    const struct xe_rtp_table *table)
 {
-	const struct xe_rtp_entry *entry;
 	struct xe_hw_engine *hwe;
 	struct xe_gt *gt;
 	struct xe_device *xe;
 
 	rtp_get_context(ctx, &hwe, &gt, &xe);
 
-	for (entry = entries; entry && entry->rules; entry++) {
+	xe_assert(xe, table->entries);
+
+	for (size_t i = 0; i < table->n_entries; i++) {
+		const struct xe_rtp_entry *entry = &table->entries[i];
+
 		if (!rule_matches(xe, gt, hwe, entry->rules, entry->n_rules))
 			continue;
 
-		rtp_mark_active(xe, ctx, entry - entries);
+		rtp_mark_active(xe, ctx, i);
 	}
 }
 EXPORT_SYMBOL_IF_KUNIT(xe_rtp_process);
diff --git a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h
index e4f1930ca1c3..4e3cfd69f922 100644
--- a/drivers/gpu/drm/xe/xe_rtp.h
+++ b/drivers/gpu/drm/xe/xe_rtp.h
@@ -461,6 +461,16 @@ struct xe_reg_sr;
 		XE_RTP_PASTE_FOREACH(ACTION_, COMMA, (__VA_ARGS__))	\
 	}
 
+#define XE_RTP_TABLE_SR(...) { \
+	.entries = (const struct xe_rtp_entry_sr[]){__VA_ARGS__}, \
+	.n_entries = ARRAY_SIZE(((const struct xe_rtp_entry_sr[]){__VA_ARGS__})), \
+}
+
+#define XE_RTP_TABLE(...) { \
+	.entries = (const struct xe_rtp_entry[]){__VA_ARGS__}, \
+	.n_entries = ARRAY_SIZE(((const struct xe_rtp_entry[]){__VA_ARGS__})), \
+}
+
 #define XE_RTP_PROCESS_CTX_INITIALIZER(arg__) _Generic((arg__),							\
 	struct xe_hw_engine * :	(struct xe_rtp_process_ctx){ { (void *)(arg__) }, XE_RTP_PROCESS_TYPE_ENGINE },	\
 	struct xe_gt * :	(struct xe_rtp_process_ctx){ { (void *)(arg__) }, XE_RTP_PROCESS_TYPE_GT },	\
@@ -471,12 +481,12 @@ void xe_rtp_process_ctx_enable_active_tracking(struct xe_rtp_process_ctx *ctx,
 					       size_t n_entries);
 
 void xe_rtp_process_to_sr(struct xe_rtp_process_ctx *ctx,
-			  const struct xe_rtp_entry_sr *entries,
-			  size_t n_entries, struct xe_reg_sr *sr,
+			  const struct xe_rtp_table_sr *table,
+			  struct xe_reg_sr *sr,
 			  bool process_in_vf);
 
 void xe_rtp_process(struct xe_rtp_process_ctx *ctx,
-		    const struct xe_rtp_entry *entries);
+		    const struct xe_rtp_table *table);
 
 /* Match functions to be used with XE_RTP_MATCH_FUNC */
 
diff --git a/drivers/gpu/drm/xe/xe_rtp_types.h b/drivers/gpu/drm/xe/xe_rtp_types.h
index 0265c16d2762..58018ae4f8cc 100644
--- a/drivers/gpu/drm/xe/xe_rtp_types.h
+++ b/drivers/gpu/drm/xe/xe_rtp_types.h
@@ -112,6 +112,16 @@ struct xe_rtp_entry {
 	u8 n_rules;
 };
 
+struct xe_rtp_table_sr {
+	const struct xe_rtp_entry_sr *entries;
+	size_t n_entries;
+};
+
+struct xe_rtp_table {
+	const struct xe_rtp_entry *entries;
+	size_t n_entries;
+};
+
 enum xe_rtp_process_type {
 	XE_RTP_PROCESS_TYPE_DEVICE,
 	XE_RTP_PROCESS_TYPE_GT,
diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
index 9a1b3862e192..bf3fad9cdbef 100644
--- a/drivers/gpu/drm/xe/xe_tuning.c
+++ b/drivers/gpu/drm/xe/xe_tuning.c
@@ -20,7 +20,7 @@
 #undef XE_REG_MCR
 #define XE_REG_MCR(...)     XE_REG(__VA_ARGS__, .mcr = 1)
 
-static const struct xe_rtp_entry_sr gt_tunings[] = {
+static const struct xe_rtp_table_sr gt_tunings = XE_RTP_TABLE_SR(
 	{ XE_RTP_NAME("Tuning: Blend Fill Caching Optimization Disable"),
 	  XE_RTP_RULES(PLATFORM(DG2)),
 	  XE_RTP_ACTIONS(SET(XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS))
@@ -100,9 +100,9 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
 	  XE_RTP_ACTIONS(FIELD_SET(GAMSTLB_CTRL, BANK_HASH_MODE,
 				   BANK_HASH_4KB_MODE))
 	},
-};
+);
 
-static const struct xe_rtp_entry_sr engine_tunings[] = {
+static const struct xe_rtp_table_sr engine_tunings = XE_RTP_TABLE_SR(
 	{ XE_RTP_NAME("Tuning: L3 Hashing Mask"),
 	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210),
 		       FUNC(xe_rtp_match_first_render_or_compute)),
@@ -129,9 +129,9 @@ static const struct xe_rtp_entry_sr engine_tunings[] = {
 		       FUNC(xe_rtp_match_first_render_or_compute)),
 	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN2, TILEY_LOCALID))
 	},
-};
+);
 
-static const struct xe_rtp_entry_sr lrc_tunings[] = {
+static const struct xe_rtp_table_sr lrc_tunings = XE_RTP_TABLE_SR(
 	{ XE_RTP_NAME("Tuning: Windower HW Filtering"),
 	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3599), ENGINE_CLASS(RENDER)),
 	  XE_RTP_ACTIONS(SET(XEHP_COMMON_SLICE_CHICKEN4, HW_FILTERING))
@@ -171,7 +171,7 @@ static const struct xe_rtp_entry_sr lrc_tunings[] = {
 	  XE_RTP_ACTIONS(FIELD_SET(FF_MODE, VS_HIT_MAX_VALUE_MASK,
 				   REG_FIELD_PREP(VS_HIT_MAX_VALUE_MASK, 0x3f)))
 	},
-};
+);
 
 /**
  * xe_tuning_init - initialize gt with tunings bookkeeping
@@ -185,9 +185,9 @@ int xe_tuning_init(struct xe_gt *gt)
 	size_t n_lrc, n_engine, n_gt, total;
 	unsigned long *p;
 
-	n_gt = BITS_TO_LONGS(ARRAY_SIZE(gt_tunings));
-	n_engine = BITS_TO_LONGS(ARRAY_SIZE(engine_tunings));
-	n_lrc = BITS_TO_LONGS(ARRAY_SIZE(lrc_tunings));
+	n_gt = BITS_TO_LONGS(gt_tunings.n_entries);
+	n_engine = BITS_TO_LONGS(engine_tunings.n_entries);
+	n_lrc = BITS_TO_LONGS(lrc_tunings.n_entries);
 	total = n_gt + n_engine + n_lrc;
 
 	p = drmm_kzalloc(&xe->drm, sizeof(*p) * total, GFP_KERNEL);
@@ -210,9 +210,8 @@ void xe_tuning_process_gt(struct xe_gt *gt)
 
 	xe_rtp_process_ctx_enable_active_tracking(&ctx,
 						  gt->tuning_active.gt,
-						  ARRAY_SIZE(gt_tunings));
-	xe_rtp_process_to_sr(&ctx, gt_tunings, ARRAY_SIZE(gt_tunings),
-			     &gt->reg_sr, false);
+						  gt_tunings.n_entries);
+	xe_rtp_process_to_sr(&ctx, &gt_tunings, &gt->reg_sr, false);
 }
 EXPORT_SYMBOL_IF_KUNIT(xe_tuning_process_gt);
 
@@ -222,9 +221,8 @@ void xe_tuning_process_engine(struct xe_hw_engine *hwe)
 
 	xe_rtp_process_ctx_enable_active_tracking(&ctx,
 						  hwe->gt->tuning_active.engine,
-						  ARRAY_SIZE(engine_tunings));
-	xe_rtp_process_to_sr(&ctx, engine_tunings, ARRAY_SIZE(engine_tunings),
-			     &hwe->reg_sr, false);
+						  engine_tunings.n_entries);
+	xe_rtp_process_to_sr(&ctx, &engine_tunings, &hwe->reg_sr, false);
 }
 EXPORT_SYMBOL_IF_KUNIT(xe_tuning_process_engine);
 
@@ -242,9 +240,8 @@ void xe_tuning_process_lrc(struct xe_hw_engine *hwe)
 
 	xe_rtp_process_ctx_enable_active_tracking(&ctx,
 						  hwe->gt->tuning_active.lrc,
-						  ARRAY_SIZE(lrc_tunings));
-	xe_rtp_process_to_sr(&ctx, lrc_tunings, ARRAY_SIZE(lrc_tunings),
-			     &hwe->reg_lrc, true);
+						  lrc_tunings.n_entries);
+	xe_rtp_process_to_sr(&ctx, &lrc_tunings, &hwe->reg_lrc, true);
 }
 
 /**
@@ -259,18 +256,18 @@ int xe_tuning_dump(struct xe_gt *gt, struct drm_printer *p)
 	size_t idx;
 
 	drm_printf(p, "GT Tunings\n");
-	for_each_set_bit(idx, gt->tuning_active.gt, ARRAY_SIZE(gt_tunings))
-		drm_printf_indent(p, 1, "%s\n", gt_tunings[idx].name);
+	for_each_set_bit(idx, gt->tuning_active.gt, gt_tunings.n_entries)
+		drm_printf_indent(p, 1, "%s\n", gt_tunings.entries[idx].name);
 
 	drm_puts(p, "\n");
 	drm_printf(p, "Engine Tunings\n");
-	for_each_set_bit(idx, gt->tuning_active.engine, ARRAY_SIZE(engine_tunings))
-		drm_printf_indent(p, 1, "%s\n", engine_tunings[idx].name);
+	for_each_set_bit(idx, gt->tuning_active.engine, engine_tunings.n_entries)
+		drm_printf_indent(p, 1, "%s\n", engine_tunings.entries[idx].name);
 
 	drm_puts(p, "\n");
 	drm_printf(p, "LRC Tunings\n");
-	for_each_set_bit(idx, gt->tuning_active.lrc, ARRAY_SIZE(lrc_tunings))
-		drm_printf_indent(p, 1, "%s\n", lrc_tunings[idx].name);
+	for_each_set_bit(idx, gt->tuning_active.lrc, lrc_tunings.n_entries)
+		drm_printf_indent(p, 1, "%s\n", lrc_tunings.entries[idx].name);
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index cb811f8a7781..b9d9fe0801aa 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -130,7 +130,7 @@
 __diag_push();
 __diag_ignore_all("-Woverride-init", "Allow field overrides in table");
 
-static const struct xe_rtp_entry_sr gt_was[] = {
+static const struct xe_rtp_table_sr gt_was = XE_RTP_TABLE_SR(
 	/* Workarounds applying over a range of IPs */
 
 	{ XE_RTP_NAME("14011060649"),
@@ -306,9 +306,9 @@ static const struct xe_rtp_entry_sr gt_was[] = {
 	  XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
 	  XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
 	},
-};
+);
 
-static const struct xe_rtp_entry_sr engine_was[] = {
+static const struct xe_rtp_table_sr engine_was = XE_RTP_TABLE_SR(
 	/* Workarounds applying over a range of IPs */
 
 	{ XE_RTP_NAME("22010931296, 18011464164, 14010919138"),
@@ -614,9 +614,9 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 		       FUNC(xe_rtp_match_first_render_or_compute)),
 	  XE_RTP_ACTIONS(SET(TDL_CHICKEN, BIT_APQ_OPT_DIS))
 	},
-};
+);
 
-static const struct xe_rtp_entry_sr lrc_was[] = {
+static const struct xe_rtp_table_sr lrc_was = XE_RTP_TABLE_SR(
 	{ XE_RTP_NAME("16011163337"),
 	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
 	  /* read verification is ignored due to 1608008084. */
@@ -794,21 +794,29 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
 		       ENGINE_CLASS(RENDER)),
 	  XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX))
 	},
-};
+);
 
-static __maybe_unused const struct xe_rtp_entry oob_was[] = {
+static const struct xe_rtp_entry oob_was_entries[] = {
 #include <generated/xe_wa_oob.c>
-	{}
 };
 
-static_assert(ARRAY_SIZE(oob_was) - 1 == _XE_WA_OOB_COUNT);
+static_assert(ARRAY_SIZE(oob_was_entries)  == _XE_WA_OOB_COUNT);
 
-static __maybe_unused const struct xe_rtp_entry device_oob_was[] = {
+static __maybe_unused const struct xe_rtp_table oob_was = {
+	.entries = oob_was_entries,
+	.n_entries = ARRAY_SIZE(oob_was_entries),
+};
+
+static const struct xe_rtp_entry device_oob_was_entries[] = {
 #include <generated/xe_device_wa_oob.c>
-	{}
 };
 
-static_assert(ARRAY_SIZE(device_oob_was) - 1 == _XE_DEVICE_WA_OOB_COUNT);
+static_assert(ARRAY_SIZE(device_oob_was_entries) == _XE_DEVICE_WA_OOB_COUNT);
+
+static __maybe_unused const struct xe_rtp_table device_oob_was = {
+	.entries = device_oob_was_entries,
+	.n_entries = ARRAY_SIZE(device_oob_was_entries),
+};
 
 __diag_pop();
 
@@ -824,10 +832,10 @@ void xe_wa_process_device_oob(struct xe_device *xe)
 {
 	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(xe);
 
-	xe_rtp_process_ctx_enable_active_tracking(&ctx, xe->wa_active.oob, ARRAY_SIZE(device_oob_was));
+	xe_rtp_process_ctx_enable_active_tracking(&ctx, xe->wa_active.oob, device_oob_was.n_entries);
 
 	xe->wa_active.oob_initialized = true;
-	xe_rtp_process(&ctx, device_oob_was);
+	xe_rtp_process(&ctx, &device_oob_was);
 }
 
 /**
@@ -842,9 +850,9 @@ void xe_wa_process_gt_oob(struct xe_gt *gt)
 	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
 
 	xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.oob,
-						  ARRAY_SIZE(oob_was));
+						  oob_was.n_entries);
 	gt->wa_active.oob_initialized = true;
-	xe_rtp_process(&ctx, oob_was);
+	xe_rtp_process(&ctx, &oob_was);
 }
 
 /**
@@ -859,9 +867,8 @@ void xe_wa_process_gt(struct xe_gt *gt)
 	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
 
 	xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.gt,
-						  ARRAY_SIZE(gt_was));
-	xe_rtp_process_to_sr(&ctx, gt_was, ARRAY_SIZE(gt_was),
-			     &gt->reg_sr, false);
+						  gt_was.n_entries);
+	xe_rtp_process_to_sr(&ctx, &gt_was, &gt->reg_sr, false);
 }
 EXPORT_SYMBOL_IF_KUNIT(xe_wa_process_gt);
 
@@ -878,9 +885,8 @@ void xe_wa_process_engine(struct xe_hw_engine *hwe)
 	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
 
 	xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.engine,
-						  ARRAY_SIZE(engine_was));
-	xe_rtp_process_to_sr(&ctx, engine_was, ARRAY_SIZE(engine_was),
-			     &hwe->reg_sr, false);
+						  engine_was.n_entries);
+	xe_rtp_process_to_sr(&ctx, &engine_was, &hwe->reg_sr, false);
 }
 
 /**
@@ -896,9 +902,8 @@ void xe_wa_process_lrc(struct xe_hw_engine *hwe)
 	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
 
 	xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.lrc,
-						  ARRAY_SIZE(lrc_was));
-	xe_rtp_process_to_sr(&ctx, lrc_was, ARRAY_SIZE(lrc_was),
-			     &hwe->reg_lrc, true);
+						  lrc_was.n_entries);
+	xe_rtp_process_to_sr(&ctx, &lrc_was, &hwe->reg_lrc, true);
 }
 
 /**
@@ -912,7 +917,7 @@ int xe_wa_device_init(struct xe_device *xe)
 	unsigned long *p;
 
 	p = drmm_kzalloc(&xe->drm,
-			 sizeof(*p) * BITS_TO_LONGS(ARRAY_SIZE(device_oob_was)),
+			 sizeof(*p) * BITS_TO_LONGS(device_oob_was.n_entries),
 			 GFP_KERNEL);
 
 	if (!p)
@@ -935,10 +940,10 @@ int xe_wa_gt_init(struct xe_gt *gt)
 	size_t n_oob, n_lrc, n_engine, n_gt, total;
 	unsigned long *p;
 
-	n_gt = BITS_TO_LONGS(ARRAY_SIZE(gt_was));
-	n_engine = BITS_TO_LONGS(ARRAY_SIZE(engine_was));
-	n_lrc = BITS_TO_LONGS(ARRAY_SIZE(lrc_was));
-	n_oob = BITS_TO_LONGS(ARRAY_SIZE(oob_was));
+	n_gt = BITS_TO_LONGS(gt_was.n_entries);
+	n_engine = BITS_TO_LONGS(engine_was.n_entries);
+	n_lrc = BITS_TO_LONGS(lrc_was.n_entries);
+	n_oob = BITS_TO_LONGS(oob_was.n_entries);
 	total = n_gt + n_engine + n_lrc + n_oob;
 
 	p = drmm_kzalloc(&xe->drm, sizeof(*p) * total, GFP_KERNEL);
@@ -962,9 +967,9 @@ void xe_wa_device_dump(struct xe_device *xe, struct drm_printer *p)
 	size_t idx;
 
 	drm_printf(p, "Device OOB Workarounds\n");
-	for_each_set_bit(idx, xe->wa_active.oob, ARRAY_SIZE(device_oob_was))
-		if (device_oob_was[idx].name)
-			drm_printf_indent(p, 1, "%s\n", device_oob_was[idx].name);
+	for_each_set_bit(idx, xe->wa_active.oob, device_oob_was.n_entries)
+		if (device_oob_was.entries[idx].name)
+			drm_printf_indent(p, 1, "%s\n", device_oob_was.entries[idx].name);
 }
 
 /**
@@ -979,24 +984,24 @@ int xe_wa_gt_dump(struct xe_gt *gt, struct drm_printer *p)
 	size_t idx;
 
 	drm_printf(p, "GT Workarounds\n");
-	for_each_set_bit(idx, gt->wa_active.gt, ARRAY_SIZE(gt_was))
-		drm_printf_indent(p, 1, "%s\n", gt_was[idx].name);
+	for_each_set_bit(idx, gt->wa_active.gt, gt_was.n_entries)
+		drm_printf_indent(p, 1, "%s\n", gt_was.entries[idx].name);
 
 	drm_puts(p, "\n");
 	drm_printf(p, "Engine Workarounds\n");
-	for_each_set_bit(idx, gt->wa_active.engine, ARRAY_SIZE(engine_was))
-		drm_printf_indent(p, 1, "%s\n", engine_was[idx].name);
+	for_each_set_bit(idx, gt->wa_active.engine, engine_was.n_entries)
+		drm_printf_indent(p, 1, "%s\n", engine_was.entries[idx].name);
 
 	drm_puts(p, "\n");
 	drm_printf(p, "LRC Workarounds\n");
-	for_each_set_bit(idx, gt->wa_active.lrc, ARRAY_SIZE(lrc_was))
-		drm_printf_indent(p, 1, "%s\n", lrc_was[idx].name);
+	for_each_set_bit(idx, gt->wa_active.lrc, lrc_was.n_entries)
+		drm_printf_indent(p, 1, "%s\n", lrc_was.entries[idx].name);
 
 	drm_puts(p, "\n");
 	drm_printf(p, "OOB Workarounds\n");
-	for_each_set_bit(idx, gt->wa_active.oob, ARRAY_SIZE(oob_was))
-		if (oob_was[idx].name)
-			drm_printf_indent(p, 1, "%s\n", oob_was[idx].name);
+	for_each_set_bit(idx, gt->wa_active.oob, oob_was.n_entries)
+		if (oob_was.entries[idx].name)
+			drm_printf_indent(p, 1, "%s\n", oob_was.entries[idx].name);
 	return 0;
 }
 
-- 
2.43.0

[PATCH v5 2/4] drm/xe/rtp: Ensure gt_was doesn't evaluate rules with engine types

[Violet Monti]

It is currently possible for a RTP rule, and subsequently a workaround,
to expect contexts that may not be present when the workaround is
applied. For example, the workarounds in the engine_was[] in drm/xe/xe_wa.c
expect an engine entity to be active. Conversely, the gt_was[] is not
depending on an engine entity to implement its workarounds. This kunit
test addition checks the gt_was[] workaround list for any workarounds
with XEP_RTP_ENGINE_CLASS() rules. If a workaround does have one of
these rules, the workaround is then checked for the "FOREACH_ENGINE" flag,
which ensures the workaround is implemented properly.

The result of this test is an expectation failure if a workaround has an
improper XE_RTP_ENGINE_CLASS() rule setup, and aims to prevent future
issues of gt_was workarounds being applied without proper contexts.

The gt_tunings[] RTP table has the same functional layout and
requirements as gt_was[], so it shares the same kunit test function,
minimizing excessive code.

v5:
    - Remove unnecessary headers from xe_rtp_table_test.c

v4:
    - No change

v3:
    - Removed "VISIBLE_IF_KUNIT" keyword from xe_wa.h
    - Added gt_tunings[] for testing
    - Reworked KUNIT_EXPECT_TRUE() for easier parsing of errors

v2:
    - Moved contents of xe_rtp_tables_test.h to .c and removed file
    - Renamed macro RTP_KUNIT_ARRAY_PARAM to RTP_TABLE_PARAM
    - Removed unnecessary functions and iterative components from
      generated _gen_params functions and implemented usage of table
      name and WA number as entry name
    - Condensed xe_rtp_table_gt_test() to use KUNIT_EXPECT_TRUE with no
      message statement
    - Removed xe_rtp_table_test_init() and xe_rtp_table_test_exit() as
      fake device initialization is not necessary

Signed-off-by: Violet Monti <violet.monti@intel.com>
---
 drivers/gpu/drm/xe/tests/Makefile             |  1 +
 drivers/gpu/drm/xe/tests/xe_rtp_tables_test.c | 53 +++++++++++++++++++
 drivers/gpu/drm/xe/xe_tuning.c                |  3 +-
 drivers/gpu/drm/xe/xe_tuning.h                |  6 +++
 drivers/gpu/drm/xe/xe_wa.c                    |  3 +-
 drivers/gpu/drm/xe/xe_wa.h                    |  5 ++
 6 files changed, 69 insertions(+), 2 deletions(-)
 create mode 100644 drivers/gpu/drm/xe/tests/xe_rtp_tables_test.c

diff --git a/drivers/gpu/drm/xe/tests/Makefile b/drivers/gpu/drm/xe/tests/Makefile
index 0e3408f4952c..f7aa47f11a36 100644
--- a/drivers/gpu/drm/xe/tests/Makefile
+++ b/drivers/gpu/drm/xe/tests/Makefile
@@ -9,5 +9,6 @@ obj-$(CONFIG_DRM_XE_KUNIT_TEST) += xe_test.o
 xe_test-y = xe_test_mod.o \
 	xe_args_test.o \
 	xe_pci_test.o \
+	xe_rtp_tables_test.o \
 	xe_rtp_test.o \
 	xe_wa_test.o
diff --git a/drivers/gpu/drm/xe/tests/xe_rtp_tables_test.c b/drivers/gpu/drm/xe/tests/xe_rtp_tables_test.c
new file mode 100644
index 000000000000..7dd77133bc42
--- /dev/null
+++ b/drivers/gpu/drm/xe/tests/xe_rtp_tables_test.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#include <kunit/test.h>
+
+#include "xe_rtp_types.h"
+#include "xe_tuning.h"
+#include "xe_wa.h"
+
+#define RTP_TABLE_PARAM(table)									\
+	static const void *table##_gen_params(struct kunit *test,				\
+					     const void *prev, char *desc)			\
+	{											\
+		typeof((table.entries)[0]) *__next = prev ?					\
+			((typeof(__next))prev) + 1 : (table.entries);				\
+		if (__next - table.entries < table.n_entries) {					\
+			scnprintf(desc, KUNIT_PARAM_DESC_SIZE, #table "/%s", __next->name);	\
+			return __next;								\
+		}										\
+		return NULL;									\
+	}
+
+static void xe_rtp_table_gt_test(struct kunit *test)
+{
+	const struct xe_rtp_entry_sr *entry = test->param_value;
+
+	for (int i = 0; i < entry->n_rules; i++) {
+		KUNIT_EXPECT_TRUE(test,
+				  entry->rules[i].match_type != XE_RTP_MATCH_ENGINE_CLASS ||
+				  entry->flags & XE_RTP_ENTRY_FLAG_FOREACH_ENGINE);
+		KUNIT_EXPECT_TRUE(test,
+				  entry->rules[i].match_type != XE_RTP_MATCH_NOT_ENGINE_CLASS ||
+				  entry->flags & XE_RTP_ENTRY_FLAG_FOREACH_ENGINE);
+	}
+}
+
+RTP_TABLE_PARAM(gt_was);
+RTP_TABLE_PARAM(gt_tunings);
+
+static struct kunit_case xe_rtp_table_tests[] = {
+	KUNIT_CASE_PARAM(xe_rtp_table_gt_test, gt_was_gen_params),
+	KUNIT_CASE_PARAM(xe_rtp_table_gt_test, gt_tunings_gen_params),
+	{}
+};
+
+static struct kunit_suite xe_rtp_tables_test_suite = {
+	.name = "xe_rtp_tables_test",
+	.test_cases = xe_rtp_table_tests,
+};
+
+kunit_test_suite(xe_rtp_tables_test_suite);
diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
index bf3fad9cdbef..bcec40ca2d35 100644
--- a/drivers/gpu/drm/xe/xe_tuning.c
+++ b/drivers/gpu/drm/xe/xe_tuning.c
@@ -20,7 +20,7 @@
 #undef XE_REG_MCR
 #define XE_REG_MCR(...)     XE_REG(__VA_ARGS__, .mcr = 1)
 
-static const struct xe_rtp_table_sr gt_tunings = XE_RTP_TABLE_SR(
+VISIBLE_IF_KUNIT const struct xe_rtp_table_sr gt_tunings = XE_RTP_TABLE_SR(
 	{ XE_RTP_NAME("Tuning: Blend Fill Caching Optimization Disable"),
 	  XE_RTP_RULES(PLATFORM(DG2)),
 	  XE_RTP_ACTIONS(SET(XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS))
@@ -101,6 +101,7 @@ static const struct xe_rtp_table_sr gt_tunings = XE_RTP_TABLE_SR(
 				   BANK_HASH_4KB_MODE))
 	},
 );
+EXPORT_SYMBOL_IF_KUNIT(gt_tunings);
 
 static const struct xe_rtp_table_sr engine_tunings = XE_RTP_TABLE_SR(
 	{ XE_RTP_NAME("Tuning: L3 Hashing Mask"),
diff --git a/drivers/gpu/drm/xe/xe_tuning.h b/drivers/gpu/drm/xe/xe_tuning.h
index d18e187debf6..869564e3e992 100644
--- a/drivers/gpu/drm/xe/xe_tuning.h
+++ b/drivers/gpu/drm/xe/xe_tuning.h
@@ -6,6 +6,8 @@
 #ifndef _XE_TUNING_H_
 #define _XE_TUNING_H_
 
+#include <kunit/visibility.h>
+
 struct drm_printer;
 struct xe_gt;
 struct xe_hw_engine;
@@ -16,4 +18,8 @@ void xe_tuning_process_engine(struct xe_hw_engine *hwe);
 void xe_tuning_process_lrc(struct xe_hw_engine *hwe);
 int xe_tuning_dump(struct xe_gt *gt, struct drm_printer *p);
 
+#if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
+extern const struct xe_rtp_table_sr gt_tunings;
+#endif
+
 #endif
diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index b9d9fe0801aa..1a1e04215f21 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -130,7 +130,7 @@
 __diag_push();
 __diag_ignore_all("-Woverride-init", "Allow field overrides in table");
 
-static const struct xe_rtp_table_sr gt_was = XE_RTP_TABLE_SR(
+VISIBLE_IF_KUNIT const struct xe_rtp_table_sr gt_was = XE_RTP_TABLE_SR(
 	/* Workarounds applying over a range of IPs */
 
 	{ XE_RTP_NAME("14011060649"),
@@ -307,6 +307,7 @@ static const struct xe_rtp_table_sr gt_was = XE_RTP_TABLE_SR(
 	  XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
 	},
 );
+EXPORT_SYMBOL_IF_KUNIT(gt_was);
 
 static const struct xe_rtp_table_sr engine_was = XE_RTP_TABLE_SR(
 	/* Workarounds applying over a range of IPs */
diff --git a/drivers/gpu/drm/xe/xe_wa.h b/drivers/gpu/drm/xe/xe_wa.h
index a5f7d33c1b32..8784b491dde7 100644
--- a/drivers/gpu/drm/xe/xe_wa.h
+++ b/drivers/gpu/drm/xe/xe_wa.h
@@ -6,6 +6,7 @@
 #ifndef _XE_WA_H_
 #define _XE_WA_H_
 
+#include <kunit/visibility.h>
 #include "xe_assert.h"
 
 struct drm_printer;
@@ -24,6 +25,10 @@ void xe_wa_apply_tile_workarounds(struct xe_tile *tile);
 void xe_wa_device_dump(struct xe_device *xe, struct drm_printer *p);
 int xe_wa_gt_dump(struct xe_gt *gt, struct drm_printer *p);
 
+#if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
+extern const struct xe_rtp_table_sr gt_was;
+#endif
+
 /**
  * XE_GT_WA - Out-of-band GT workarounds, to be queried and called as needed.
  * @gt__: gt instance
-- 
2.43.0

[PATCH v5 3/4] drm/xe/rtp: Ensure oob_was does not evaluate engine type rules

[Violet Monti]

This commit builds on the implementation of the GT WA testing, increasing
the scope of testing to include the OOB workaround list. The added test
checks for workarounds with XE_RTP_ENGINE_CLASS() rules and raises an
expectationfailure if any are found. Unlike the GT workarounds, there are
no flags within this workaround list, so all invalid rules will fail.

v5:
    - No change

v4:
    - No change

v3:
    - Removed VISIBLE_IF_KUNIT keyword from xe_wa.h
    - Reworked KUNIT_EXPECT_TRUE for easier decoding of errors

v2:
    - Changed xe_rtp_table_oob_test() to follow format of
      xe_rtp_table_gt_test
    - Changed oob_was generated params to follow format of gt_was
      generated params

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Violet Monti <violet.monti@intel.com>
---
 drivers/gpu/drm/xe/tests/xe_rtp_tables_test.c | 15 +++++++++++++++
 drivers/gpu/drm/xe/xe_wa.c                    |  3 ++-
 drivers/gpu/drm/xe/xe_wa.h                    |  1 +
 3 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/tests/xe_rtp_tables_test.c b/drivers/gpu/drm/xe/tests/xe_rtp_tables_test.c
index 7dd77133bc42..ff6ff2d49ad7 100644
--- a/drivers/gpu/drm/xe/tests/xe_rtp_tables_test.c
+++ b/drivers/gpu/drm/xe/tests/xe_rtp_tables_test.c
@@ -39,9 +39,24 @@ static void xe_rtp_table_gt_test(struct kunit *test)
 RTP_TABLE_PARAM(gt_was);
 RTP_TABLE_PARAM(gt_tunings);
 
+static void xe_rtp_table_oob_test(struct kunit *test)
+{
+	const struct xe_rtp_entry *entry = test->param_value;
+
+	for (int i = 0; i < entry->n_rules; i++) {
+		u8 match_type = entry->rules[i].match_type;
+
+		KUNIT_EXPECT_NE(test, match_type, XE_RTP_MATCH_ENGINE_CLASS);
+		KUNIT_EXPECT_NE(test, match_type, XE_RTP_MATCH_NOT_ENGINE_CLASS);
+	}
+}
+
+RTP_TABLE_PARAM(oob_was);
+
 static struct kunit_case xe_rtp_table_tests[] = {
 	KUNIT_CASE_PARAM(xe_rtp_table_gt_test, gt_was_gen_params),
 	KUNIT_CASE_PARAM(xe_rtp_table_gt_test, gt_tunings_gen_params),
+	KUNIT_CASE_PARAM(xe_rtp_table_oob_test, oob_was_gen_params),
 	{}
 };
 
diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 1a1e04215f21..410099545f4e 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -803,10 +803,11 @@ static const struct xe_rtp_entry oob_was_entries[] = {
 
 static_assert(ARRAY_SIZE(oob_was_entries)  == _XE_WA_OOB_COUNT);
 
-static __maybe_unused const struct xe_rtp_table oob_was = {
+VISIBLE_IF_KUNIT __maybe_unused const struct xe_rtp_table oob_was = {
 	.entries = oob_was_entries,
 	.n_entries = ARRAY_SIZE(oob_was_entries),
 };
+EXPORT_SYMBOL_IF_KUNIT(oob_was);
 
 static const struct xe_rtp_entry device_oob_was_entries[] = {
 #include <generated/xe_device_wa_oob.c>
diff --git a/drivers/gpu/drm/xe/xe_wa.h b/drivers/gpu/drm/xe/xe_wa.h
index 8784b491dde7..c5cc260621cd 100644
--- a/drivers/gpu/drm/xe/xe_wa.h
+++ b/drivers/gpu/drm/xe/xe_wa.h
@@ -27,6 +27,7 @@ int xe_wa_gt_dump(struct xe_gt *gt, struct drm_printer *p);
 
 #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
 extern const struct xe_rtp_table_sr gt_was;
+extern __maybe_unused const struct xe_rtp_table oob_was;
 #endif
 
 /**
-- 
2.43.0

[PATCH v5 4/4] drm/xe/rtp: Ensure device_oob_was only evaluates correct rules

[Violet Monti]

This commit builds on the implementation of the GT WA testing, increasing
the scope of testing to include the device OOB workaround list. As well
as checking for XE_RTP_ENGINE_CLASS(), this test also checks for rules
involving XE_RTP_GRAPHICS() and XE_RTP_MEDIA(), as well as their
derivatives.

This test will raise expectation fails for any workarounds in the
device_oob_was list that has an invalid rule type, preventing evaluation
or inclusion of rules that could be applied in the wrong context.

v5:
    - No change

v4:
    - No change

v3:
    - Removed "VISIBLE_IF_KUNIT" keyword from xe_wa.h
    - Heavily reworked rule checking within _dev_oob_test() function for
      easier understanding and interpreting of errors

v2:
    - Changed xe_rtp_table_dev_oob_test() to follow format of
      xe_rtp_table_gt_test
    - Changed device_oob_was generated params to follow format of
      gt_was

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Violet Monti <violet.monti@intel.com>
---
 drivers/gpu/drm/xe/tests/xe_rtp_tables_test.c | 23 +++++++++++++++++++
 drivers/gpu/drm/xe/xe_wa.c                    |  3 ++-
 drivers/gpu/drm/xe/xe_wa.h                    |  1 +
 3 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/tests/xe_rtp_tables_test.c b/drivers/gpu/drm/xe/tests/xe_rtp_tables_test.c
index ff6ff2d49ad7..ef379cbb6a86 100644
--- a/drivers/gpu/drm/xe/tests/xe_rtp_tables_test.c
+++ b/drivers/gpu/drm/xe/tests/xe_rtp_tables_test.c
@@ -53,10 +53,33 @@ static void xe_rtp_table_oob_test(struct kunit *test)
 
 RTP_TABLE_PARAM(oob_was);
 
+static void xe_rtp_table_dev_oob_test(struct kunit *test)
+{
+	const struct xe_rtp_entry *entry = test->param_value;
+
+	for (int i = 0; i < entry->n_rules; i++) {
+		u8 match_type = entry->rules[i].match_type;
+
+		KUNIT_EXPECT_NE(test, match_type, XE_RTP_MATCH_ENGINE_CLASS);
+		KUNIT_EXPECT_NE(test, match_type, XE_RTP_MATCH_NOT_ENGINE_CLASS);
+		KUNIT_EXPECT_NE(test, match_type, XE_RTP_MATCH_GRAPHICS_VERSION);
+		KUNIT_EXPECT_NE(test, match_type, XE_RTP_MATCH_GRAPHICS_VERSION_RANGE);
+		KUNIT_EXPECT_NE(test, match_type, XE_RTP_MATCH_GRAPHICS_VERSION_ANY_GT);
+		KUNIT_EXPECT_NE(test, match_type, XE_RTP_MATCH_GRAPHICS_STEP);
+		KUNIT_EXPECT_NE(test, match_type, XE_RTP_MATCH_MEDIA_VERSION);
+		KUNIT_EXPECT_NE(test, match_type, XE_RTP_MATCH_MEDIA_VERSION_RANGE);
+		KUNIT_EXPECT_NE(test, match_type, XE_RTP_MATCH_MEDIA_VERSION_ANY_GT);
+		KUNIT_EXPECT_NE(test, match_type, XE_RTP_MATCH_MEDIA_STEP);
+	}
+}
+
+RTP_TABLE_PARAM(device_oob_was);
+
 static struct kunit_case xe_rtp_table_tests[] = {
 	KUNIT_CASE_PARAM(xe_rtp_table_gt_test, gt_was_gen_params),
 	KUNIT_CASE_PARAM(xe_rtp_table_gt_test, gt_tunings_gen_params),
 	KUNIT_CASE_PARAM(xe_rtp_table_oob_test, oob_was_gen_params),
+	KUNIT_CASE_PARAM(xe_rtp_table_dev_oob_test, device_oob_was_gen_params),
 	{}
 };
 
diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 410099545f4e..635d5461f712 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -815,10 +815,11 @@ static const struct xe_rtp_entry device_oob_was_entries[] = {
 
 static_assert(ARRAY_SIZE(device_oob_was_entries) == _XE_DEVICE_WA_OOB_COUNT);
 
-static __maybe_unused const struct xe_rtp_table device_oob_was = {
+VISIBLE_IF_KUNIT __maybe_unused const struct xe_rtp_table device_oob_was = {
 	.entries = device_oob_was_entries,
 	.n_entries = ARRAY_SIZE(device_oob_was_entries),
 };
+EXPORT_SYMBOL_IF_KUNIT(device_oob_was);
 
 __diag_pop();
 
diff --git a/drivers/gpu/drm/xe/xe_wa.h b/drivers/gpu/drm/xe/xe_wa.h
index c5cc260621cd..f4da2b271396 100644
--- a/drivers/gpu/drm/xe/xe_wa.h
+++ b/drivers/gpu/drm/xe/xe_wa.h
@@ -28,6 +28,7 @@ int xe_wa_gt_dump(struct xe_gt *gt, struct drm_printer *p);
 #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
 extern const struct xe_rtp_table_sr gt_was;
 extern __maybe_unused const struct xe_rtp_table oob_was;
+extern __maybe_unused const struct xe_rtp_table device_oob_was;
 #endif
 
 /**
-- 
2.43.0

✗ CI.checkpatch: warning for drm/xe/rtp: WA table context testing

[Patchwork]

== Series Details ==

Series: drm/xe/rtp: WA table context testing
URL   : https://patchwork.freedesktop.org/series/167474/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
061140b9bc586ae7f40abc1249c97e1cc72d1b9d
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit bf58016cc091d76f5b22fb99c38bf539501b5a32
Author: Violet Monti <violet.monti@intel.com>
Date:   Thu May 28 09:35:35 2026 -0700

    drm/xe/rtp: Ensure device_oob_was only evaluates correct rules
    
    This commit builds on the implementation of the GT WA testing, increasing
    the scope of testing to include the device OOB workaround list. As well
    as checking for XE_RTP_ENGINE_CLASS(), this test also checks for rules
    involving XE_RTP_GRAPHICS() and XE_RTP_MEDIA(), as well as their
    derivatives.
    
    This test will raise expectation fails for any workarounds in the
    device_oob_was list that has an invalid rule type, preventing evaluation
    or inclusion of rules that could be applied in the wrong context.
    
    v5:
        - No change
    
    v4:
        - No change
    
    v3:
        - Removed "VISIBLE_IF_KUNIT" keyword from xe_wa.h
        - Heavily reworked rule checking within _dev_oob_test() function for
          easier understanding and interpreting of errors
    
    v2:
        - Changed xe_rtp_table_dev_oob_test() to follow format of
          xe_rtp_table_gt_test
        - Changed device_oob_was generated params to follow format of
          gt_was
    
    Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
    Signed-off-by: Violet Monti <violet.monti@intel.com>
+ /mt/dim checkpatch e19995339d7cc4965c37a6cf9f4c64793147b6f8 drm-intel
a0a614d40bce drm/xe/rtp: Add struct types for RTP tables
-:76: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#76: FILE: drivers/gpu/drm/xe/tests/xe_rtp_test.c:292:
+		.table = XE_RTP_TABLE_SR(

-:95: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#95: FILE: drivers/gpu/drm/xe/tests/xe_rtp_test.c:311:
+		.table = XE_RTP_TABLE_SR(

-:114: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#114: FILE: drivers/gpu/drm/xe/tests/xe_rtp_test.c:330:
+		.table = XE_RTP_TABLE_SR(

-:133: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#133: FILE: drivers/gpu/drm/xe/tests/xe_rtp_test.c:349:
+		.table = XE_RTP_TABLE_SR(

-:152: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#152: FILE: drivers/gpu/drm/xe/tests/xe_rtp_test.c:370:
+		.table = XE_RTP_TABLE_SR(

-:169: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#169: FILE: drivers/gpu/drm/xe/tests/xe_rtp_test.c:388:
+		.table = XE_RTP_TABLE_SR(

-:188: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#188: FILE: drivers/gpu/drm/xe/tests/xe_rtp_test.c:408:
+		.table = XE_RTP_TABLE_SR(

-:207: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#207: FILE: drivers/gpu/drm/xe/tests/xe_rtp_test.c:428:
+		.table = XE_RTP_TABLE_SR(

-:226: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#226: FILE: drivers/gpu/drm/xe/tests/xe_rtp_test.c:453:
+		.table = XE_RTP_TABLE_SR(

-:242: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#242: FILE: drivers/gpu/drm/xe/tests/xe_rtp_test.c:469:
+		.table = XE_RTP_TABLE_SR(

-:278: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#278: FILE: drivers/gpu/drm/xe/tests/xe_rtp_test.c:525:
+		.table = XE_RTP_TABLE(

-:290: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#290: FILE: drivers/gpu/drm/xe/tests/xe_rtp_test.c:534:
+		.table = XE_RTP_TABLE(

-:305: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#305: FILE: drivers/gpu/drm/xe/tests/xe_rtp_test.c:546:
+		.table = XE_RTP_TABLE(

-:320: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#320: FILE: drivers/gpu/drm/xe/tests/xe_rtp_test.c:558:
+		.table = XE_RTP_TABLE(

-:335: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#335: FILE: drivers/gpu/drm/xe/tests/xe_rtp_test.c:570:
+		.table = XE_RTP_TABLE(

-:351: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#351: FILE: drivers/gpu/drm/xe/tests/xe_rtp_test.c:585:
+		.table = XE_RTP_TABLE(

-:391: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#391: FILE: drivers/gpu/drm/xe/xe_hw_engine.c:349:
+	const struct xe_rtp_table_sr lrc_setup = XE_RTP_TABLE_SR(

-:413: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#413: FILE: drivers/gpu/drm/xe/xe_hw_engine.c:410:
+	const struct xe_rtp_table_sr engine_sr = XE_RTP_TABLE_SR(

-:439: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#439: FILE: drivers/gpu/drm/xe/xe_reg_whitelist.c:44:
+static const struct xe_rtp_table_sr register_whitelist = XE_RTP_TABLE_SR(

-:619: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#619: FILE: drivers/gpu/drm/xe/xe_tuning.c:23:
+static const struct xe_rtp_table_sr gt_tunings = XE_RTP_TABLE_SR(

-:631: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#631: FILE: drivers/gpu/drm/xe/xe_tuning.c:105:
+static const struct xe_rtp_table_sr engine_tunings = XE_RTP_TABLE_SR(

-:643: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#643: FILE: drivers/gpu/drm/xe/xe_tuning.c:134:
+static const struct xe_rtp_table_sr lrc_tunings = XE_RTP_TABLE_SR(

-:739: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#739: FILE: drivers/gpu/drm/xe/xe_wa.c:133:
+static const struct xe_rtp_table_sr gt_was = XE_RTP_TABLE_SR(

-:751: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#751: FILE: drivers/gpu/drm/xe/xe_wa.c:311:
+static const struct xe_rtp_table_sr engine_was = XE_RTP_TABLE_SR(

-:763: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#763: FILE: drivers/gpu/drm/xe/xe_wa.c:619:
+static const struct xe_rtp_table_sr lrc_was = XE_RTP_TABLE_SR(

-:809: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#809: FILE: drivers/gpu/drm/xe/xe_wa.c:835:
+	xe_rtp_process_ctx_enable_active_tracking(&ctx, xe->wa_active.oob, device_oob_was.n_entries);

total: 0 errors, 1 warnings, 25 checks, 794 lines checked
e48f3af92b91 drm/xe/rtp: Ensure gt_was doesn't evaluate rules with engine types
-:61: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#61: 
new file mode 100644

-:77: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'table' - possible side-effects?
#77: FILE: drivers/gpu/drm/xe/tests/xe_rtp_tables_test.c:12:
+#define RTP_TABLE_PARAM(table)									\
+	static const void *table##_gen_params(struct kunit *test,				\
+					     const void *prev, char *desc)			\
+	{											\
+		typeof((table.entries)[0]) *__next = prev ?					\
+			((typeof(__next))prev) + 1 : (table.entries);				\
+		if (__next - table.entries < table.n_entries) {					\
+			scnprintf(desc, KUNIT_PARAM_DESC_SIZE, #table "/%s", __next->name);	\
+			return __next;								\
+		}										\
+		return NULL;									\
+	}

-:81: CHECK:SPACING: spaces preferred around that '*' (ctx:WxV)
#81: FILE: drivers/gpu/drm/xe/tests/xe_rtp_tables_test.c:16:
+		typeof((table.entries)[0]) *__next = prev ?					\
 		                           ^

-:128: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#128: FILE: drivers/gpu/drm/xe/xe_tuning.c:23:
+VISIBLE_IF_KUNIT const struct xe_rtp_table_sr gt_tunings = XE_RTP_TABLE_SR(

-:171: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#171: FILE: drivers/gpu/drm/xe/xe_wa.c:133:
+VISIBLE_IF_KUNIT const struct xe_rtp_table_sr gt_was = XE_RTP_TABLE_SR(

total: 0 errors, 1 warnings, 4 checks, 122 lines checked
b04bbe6df927 drm/xe/rtp: Ensure oob_was does not evaluate engine type rules
bf58016cc091 drm/xe/rtp: Ensure device_oob_was only evaluates correct rules

✓ CI.KUnit: success for drm/xe/rtp: WA table context testing

[Patchwork]

== Series Details ==

Series: drm/xe/rtp: WA table context testing
URL   : https://patchwork.freedesktop.org/series/167474/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[16:44:05] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[16:44:10] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[16:44:41] Starting KUnit Kernel (1/1)...
[16:44:41] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[16:44:41] ================== guc_buf (11 subtests) ===================
[16:44:41] [PASSED] test_smallest
[16:44:41] [PASSED] test_largest
[16:44:41] [PASSED] test_granular
[16:44:41] [PASSED] test_unique
[16:44:41] [PASSED] test_overlap
[16:44:41] [PASSED] test_reusable
[16:44:41] [PASSED] test_too_big
[16:44:41] [PASSED] test_flush
[16:44:41] [PASSED] test_lookup
[16:44:41] [PASSED] test_data
[16:44:41] [PASSED] test_class
[16:44:41] ===================== [PASSED] guc_buf =====================
[16:44:41] =================== guc_dbm (7 subtests) ===================
[16:44:41] [PASSED] test_empty
[16:44:41] [PASSED] test_default
[16:44:41] ======================== test_size  ========================
[16:44:41] [PASSED] 4
[16:44:41] [PASSED] 8
[16:44:41] [PASSED] 32
[16:44:41] [PASSED] 256
[16:44:41] ==================== [PASSED] test_size ====================
[16:44:41] ======================= test_reuse  ========================
[16:44:41] [PASSED] 4
[16:44:41] [PASSED] 8
[16:44:41] [PASSED] 32
[16:44:41] [PASSED] 256
[16:44:41] =================== [PASSED] test_reuse ====================
[16:44:41] =================== test_range_overlap  ====================
[16:44:41] [PASSED] 4
[16:44:41] [PASSED] 8
[16:44:41] [PASSED] 32
[16:44:41] [PASSED] 256
[16:44:41] =============== [PASSED] test_range_overlap ================
[16:44:41] =================== test_range_compact  ====================
[16:44:41] [PASSED] 4
[16:44:41] [PASSED] 8
[16:44:41] [PASSED] 32
[16:44:41] [PASSED] 256
[16:44:41] =============== [PASSED] test_range_compact ================
[16:44:41] ==================== test_range_spare  =====================
[16:44:41] [PASSED] 4
[16:44:41] [PASSED] 8
[16:44:41] [PASSED] 32
[16:44:41] [PASSED] 256
[16:44:41] ================ [PASSED] test_range_spare =================
[16:44:41] ===================== [PASSED] guc_dbm =====================
[16:44:41] =================== guc_idm (6 subtests) ===================
[16:44:41] [PASSED] bad_init
[16:44:41] [PASSED] no_init
[16:44:41] [PASSED] init_fini
[16:44:41] [PASSED] check_used
[16:44:41] [PASSED] check_quota
[16:44:41] [PASSED] check_all
[16:44:41] ===================== [PASSED] guc_idm =====================
[16:44:41] ================== no_relay (3 subtests) ===================
[16:44:41] [PASSED] xe_drops_guc2pf_if_not_ready
[16:44:41] [PASSED] xe_drops_guc2vf_if_not_ready
[16:44:41] [PASSED] xe_rejects_send_if_not_ready
[16:44:41] ==================== [PASSED] no_relay =====================
[16:44:41] ================== pf_relay (14 subtests) ==================
[16:44:41] [PASSED] pf_rejects_guc2pf_too_short
[16:44:41] [PASSED] pf_rejects_guc2pf_too_long
[16:44:41] [PASSED] pf_rejects_guc2pf_no_payload
[16:44:41] [PASSED] pf_fails_no_payload
[16:44:41] [PASSED] pf_fails_bad_origin
[16:44:41] [PASSED] pf_fails_bad_type
[16:44:41] [PASSED] pf_txn_reports_error
[16:44:41] [PASSED] pf_txn_sends_pf2guc
[16:44:41] [PASSED] pf_sends_pf2guc
[16:44:41] [SKIPPED] pf_loopback_nop
[16:44:41] [SKIPPED] pf_loopback_echo
[16:44:41] [SKIPPED] pf_loopback_fail
[16:44:41] [SKIPPED] pf_loopback_busy
[16:44:41] [SKIPPED] pf_loopback_retry
[16:44:41] ==================== [PASSED] pf_relay =====================
[16:44:41] ================== vf_relay (3 subtests) ===================
[16:44:41] [PASSED] vf_rejects_guc2vf_too_short
[16:44:41] [PASSED] vf_rejects_guc2vf_too_long
[16:44:41] [PASSED] vf_rejects_guc2vf_no_payload
[16:44:41] ==================== [PASSED] vf_relay =====================
[16:44:41] ================ pf_gt_config (9 subtests) =================
[16:44:41] [PASSED] fair_contexts_1vf
[16:44:41] [PASSED] fair_doorbells_1vf
[16:44:41] [PASSED] fair_ggtt_1vf
[16:44:41] ====================== fair_vram_1vf  ======================
[16:44:41] [PASSED] 3.50 GiB
[16:44:41] [PASSED] 11.5 GiB
[16:44:41] [PASSED] 15.5 GiB
[16:44:41] [PASSED] 31.5 GiB
[16:44:41] [PASSED] 63.5 GiB
[16:44:41] [PASSED] 1.91 GiB
[16:44:41] ================== [PASSED] fair_vram_1vf ==================
[16:44:41] ================ fair_vram_1vf_admin_only  =================
[16:44:41] [PASSED] 3.50 GiB
[16:44:41] [PASSED] 11.5 GiB
[16:44:41] [PASSED] 15.5 GiB
[16:44:41] [PASSED] 31.5 GiB
[16:44:41] [PASSED] 63.5 GiB
[16:44:41] [PASSED] 1.91 GiB
[16:44:41] ============ [PASSED] fair_vram_1vf_admin_only =============
[16:44:41] ====================== fair_contexts  ======================
[16:44:41] [PASSED] 1 VF
[16:44:41] [PASSED] 2 VFs
[16:44:41] [PASSED] 3 VFs
[16:44:41] [PASSED] 4 VFs
[16:44:41] [PASSED] 5 VFs
[16:44:41] [PASSED] 6 VFs
[16:44:41] [PASSED] 7 VFs
[16:44:41] [PASSED] 8 VFs
[16:44:41] [PASSED] 9 VFs
[16:44:41] [PASSED] 10 VFs
[16:44:41] [PASSED] 11 VFs
[16:44:41] [PASSED] 12 VFs
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[16:44:41] [PASSED] 15 VFs
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[16:44:41] [PASSED] 44 VFs
[16:44:41] [PASSED] 45 VFs
[16:44:41] [PASSED] 46 VFs
[16:44:41] [PASSED] 47 VFs
[16:44:41] [PASSED] 48 VFs
[16:44:41] [PASSED] 49 VFs
[16:44:41] [PASSED] 50 VFs
[16:44:41] [PASSED] 51 VFs
[16:44:41] [PASSED] 52 VFs
[16:44:41] [PASSED] 53 VFs
[16:44:41] [PASSED] 54 VFs
[16:44:41] [PASSED] 55 VFs
[16:44:41] [PASSED] 56 VFs
[16:44:41] [PASSED] 57 VFs
[16:44:41] [PASSED] 58 VFs
[16:44:41] [PASSED] 59 VFs
[16:44:41] [PASSED] 60 VFs
[16:44:41] [PASSED] 61 VFs
[16:44:41] [PASSED] 62 VFs
[16:44:41] [PASSED] 63 VFs
[16:44:41] ================== [PASSED] fair_contexts ==================
[16:44:41] ===================== fair_doorbells  ======================
[16:44:41] [PASSED] 1 VF
[16:44:41] [PASSED] 2 VFs
[16:44:41] [PASSED] 3 VFs
[16:44:41] [PASSED] 4 VFs
[16:44:41] [PASSED] 5 VFs
[16:44:41] [PASSED] 6 VFs
[16:44:41] [PASSED] 7 VFs
[16:44:41] [PASSED] 8 VFs
[16:44:41] [PASSED] 9 VFs
[16:44:41] [PASSED] 10 VFs
[16:44:41] [PASSED] 11 VFs
[16:44:41] [PASSED] 12 VFs
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[16:44:41] [PASSED] 15 VFs
[16:44:41] [PASSED] 16 VFs
[16:44:41] [PASSED] 17 VFs
[16:44:41] [PASSED] 18 VFs
[16:44:41] [PASSED] 19 VFs
[16:44:41] [PASSED] 20 VFs
[16:44:41] [PASSED] 21 VFs
[16:44:41] [PASSED] 22 VFs
[16:44:41] [PASSED] 23 VFs
[16:44:41] [PASSED] 24 VFs
[16:44:41] [PASSED] 25 VFs
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[16:44:41] [PASSED] 27 VFs
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[16:44:41] [PASSED] 32 VFs
[16:44:41] [PASSED] 33 VFs
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[16:44:41] [PASSED] 35 VFs
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[16:44:41] [PASSED] 37 VFs
[16:44:41] [PASSED] 38 VFs
[16:44:42] [PASSED] 39 VFs
[16:44:42] [PASSED] 40 VFs
[16:44:42] [PASSED] 41 VFs
[16:44:42] [PASSED] 42 VFs
[16:44:42] [PASSED] 43 VFs
[16:44:42] [PASSED] 44 VFs
[16:44:42] [PASSED] 45 VFs
[16:44:42] [PASSED] 46 VFs
[16:44:42] [PASSED] 47 VFs
[16:44:42] [PASSED] 48 VFs
[16:44:42] [PASSED] 49 VFs
[16:44:42] [PASSED] 50 VFs
[16:44:42] [PASSED] 51 VFs
[16:44:42] [PASSED] 52 VFs
[16:44:42] [PASSED] 53 VFs
[16:44:42] [PASSED] 54 VFs
[16:44:42] [PASSED] 55 VFs
[16:44:42] [PASSED] 56 VFs
[16:44:42] [PASSED] 57 VFs
[16:44:42] [PASSED] 58 VFs
[16:44:42] [PASSED] 59 VFs
[16:44:42] [PASSED] 60 VFs
[16:44:42] [PASSED] 61 VFs
[16:44:42] [PASSED] 62 VFs
[16:44:42] [PASSED] 63 VFs
[16:44:42] ================= [PASSED] fair_doorbells ==================
[16:44:42] ======================== fair_ggtt  ========================
[16:44:42] [PASSED] 1 VF
[16:44:42] [PASSED] 2 VFs
[16:44:42] [PASSED] 3 VFs
[16:44:42] [PASSED] 4 VFs
[16:44:42] [PASSED] 5 VFs
[16:44:42] [PASSED] 6 VFs
[16:44:42] [PASSED] 7 VFs
[16:44:42] [PASSED] 8 VFs
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[16:44:42] [PASSED] 11 VFs
[16:44:42] [PASSED] 12 VFs
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[16:44:42] [PASSED] 38 VFs
[16:44:42] [PASSED] 39 VFs
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[16:44:42] [PASSED] 44 VFs
[16:44:42] [PASSED] 45 VFs
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[16:44:42] [PASSED] 49 VFs
[16:44:42] [PASSED] 50 VFs
[16:44:42] [PASSED] 51 VFs
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[16:44:42] [PASSED] 55 VFs
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[16:44:42] [PASSED] 60 VFs
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[16:44:42] [PASSED] 62 VFs
[16:44:42] [PASSED] 63 VFs
[16:44:42] ==================== [PASSED] fair_ggtt ====================
[16:44:42] ======================== fair_vram  ========================
[16:44:42] [PASSED] 1 VF
[16:44:42] [PASSED] 2 VFs
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[16:44:42] [PASSED] 48 VFs
[16:44:42] [PASSED] 49 VFs
[16:44:42] [PASSED] 50 VFs
[16:44:42] [PASSED] 51 VFs
[16:44:42] [PASSED] 52 VFs
[16:44:42] [PASSED] 53 VFs
[16:44:42] [PASSED] 54 VFs
[16:44:42] [PASSED] 55 VFs
[16:44:42] [PASSED] 56 VFs
[16:44:42] [PASSED] 57 VFs
[16:44:42] [PASSED] 58 VFs
[16:44:42] [PASSED] 59 VFs
[16:44:42] [PASSED] 60 VFs
[16:44:42] [PASSED] 61 VFs
[16:44:42] [PASSED] 62 VFs
[16:44:42] [PASSED] 63 VFs
[16:44:42] ==================== [PASSED] fair_vram ====================
[16:44:42] ================== [PASSED] pf_gt_config ===================
[16:44:42] ===================== lmtt (1 subtest) =====================
[16:44:42] ======================== test_ops  =========================
[16:44:42] [PASSED] 2-level
[16:44:42] [PASSED] multi-level
[16:44:42] ==================== [PASSED] test_ops =====================
[16:44:42] ====================== [PASSED] lmtt =======================
[16:44:42] ================= pf_service (11 subtests) =================
[16:44:42] [PASSED] pf_negotiate_any
[16:44:42] [PASSED] pf_negotiate_base_match
[16:44:42] [PASSED] pf_negotiate_base_newer
[16:44:42] [PASSED] pf_negotiate_base_next
[16:44:42] [SKIPPED] pf_negotiate_base_older
[16:44:42] [PASSED] pf_negotiate_base_prev
[16:44:42] [PASSED] pf_negotiate_latest_match
[16:44:42] [PASSED] pf_negotiate_latest_newer
[16:44:42] [PASSED] pf_negotiate_latest_next
[16:44:42] [SKIPPED] pf_negotiate_latest_older
[16:44:42] [SKIPPED] pf_negotiate_latest_prev
[16:44:42] =================== [PASSED] pf_service ====================
[16:44:42] ================= xe_guc_g2g (2 subtests) ==================
[16:44:42] ============== xe_live_guc_g2g_kunit_default  ==============
[16:44:42] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[16:44:42] ============== xe_live_guc_g2g_kunit_allmem  ===============
[16:44:42] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[16:44:42] =================== [SKIPPED] xe_guc_g2g ===================
[16:44:42] =================== xe_mocs (2 subtests) ===================
[16:44:42] ================ xe_live_mocs_kernel_kunit  ================
[16:44:42] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[16:44:42] ================ xe_live_mocs_reset_kunit  =================
[16:44:42] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[16:44:42] ==================== [SKIPPED] xe_mocs =====================
[16:44:42] ================= xe_migrate (2 subtests) ==================
[16:44:42] ================= xe_migrate_sanity_kunit  =================
[16:44:42] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[16:44:42] ================== xe_validate_ccs_kunit  ==================
[16:44:42] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[16:44:42] =================== [SKIPPED] xe_migrate ===================
[16:44:42] ================== xe_dma_buf (1 subtest) ==================
[16:44:42] ==================== xe_dma_buf_kunit  =====================
[16:44:42] ================ [SKIPPED] xe_dma_buf_kunit ================
[16:44:42] =================== [SKIPPED] xe_dma_buf ===================
[16:44:42] ================= xe_bo_shrink (1 subtest) =================
[16:44:42] =================== xe_bo_shrink_kunit  ====================
[16:44:42] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[16:44:42] ================== [SKIPPED] xe_bo_shrink ==================
[16:44:42] ==================== xe_bo (2 subtests) ====================
[16:44:42] ================== xe_ccs_migrate_kunit  ===================
[16:44:42] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[16:44:42] ==================== xe_bo_evict_kunit  ====================
[16:44:42] =============== [SKIPPED] xe_bo_evict_kunit ================
[16:44:42] ===================== [SKIPPED] xe_bo ======================
[16:44:42] ==================== args (13 subtests) ====================
[16:44:42] [PASSED] count_args_test
[16:44:42] [PASSED] call_args_example
[16:44:42] [PASSED] call_args_test
[16:44:42] [PASSED] drop_first_arg_example
[16:44:42] [PASSED] drop_first_arg_test
[16:44:42] [PASSED] first_arg_example
[16:44:42] [PASSED] first_arg_test
[16:44:42] [PASSED] last_arg_example
[16:44:42] [PASSED] last_arg_test
[16:44:42] [PASSED] pick_arg_example
[16:44:42] [PASSED] if_args_example
[16:44:42] [PASSED] if_args_test
[16:44:42] [PASSED] sep_comma_example
[16:44:42] ====================== [PASSED] args =======================
[16:44:42] =================== xe_pci (3 subtests) ====================
[16:44:42] ==================== check_graphics_ip  ====================
[16:44:42] [PASSED] 12.00 Xe_LP
[16:44:42] [PASSED] 12.10 Xe_LP+
[16:44:42] [PASSED] 12.55 Xe_HPG
[16:44:42] [PASSED] 12.60 Xe_HPC
[16:44:42] [PASSED] 12.70 Xe_LPG
[16:44:42] [PASSED] 12.71 Xe_LPG
[16:44:42] [PASSED] 12.74 Xe_LPG+
[16:44:42] [PASSED] 20.01 Xe2_HPG
[16:44:42] [PASSED] 20.02 Xe2_HPG
[16:44:42] [PASSED] 20.04 Xe2_LPG
[16:44:42] [PASSED] 30.00 Xe3_LPG
[16:44:42] [PASSED] 30.01 Xe3_LPG
[16:44:42] [PASSED] 30.03 Xe3_LPG
[16:44:42] [PASSED] 30.04 Xe3_LPG
[16:44:42] [PASSED] 30.05 Xe3_LPG
[16:44:42] [PASSED] 35.10 Xe3p_LPG
[16:44:42] [PASSED] 35.11 Xe3p_XPC
[16:44:42] ================ [PASSED] check_graphics_ip ================
[16:44:42] ===================== check_media_ip  ======================
[16:44:42] [PASSED] 12.00 Xe_M
[16:44:42] [PASSED] 12.55 Xe_HPM
[16:44:42] [PASSED] 13.00 Xe_LPM+
[16:44:42] [PASSED] 13.01 Xe2_HPM
[16:44:42] [PASSED] 20.00 Xe2_LPM
[16:44:42] [PASSED] 30.00 Xe3_LPM
[16:44:42] [PASSED] 30.02 Xe3_LPM
[16:44:42] [PASSED] 35.00 Xe3p_LPM
[16:44:42] [PASSED] 35.03 Xe3p_HPM
[16:44:42] ================= [PASSED] check_media_ip ==================
[16:44:42] =================== check_platform_desc  ===================
[16:44:42] [PASSED] 0x9A60 (TIGERLAKE)
[16:44:42] [PASSED] 0x9A68 (TIGERLAKE)
[16:44:42] [PASSED] 0x9A70 (TIGERLAKE)
[16:44:42] [PASSED] 0x9A40 (TIGERLAKE)
[16:44:42] [PASSED] 0x9A49 (TIGERLAKE)
[16:44:42] [PASSED] 0x9A59 (TIGERLAKE)
[16:44:42] [PASSED] 0x9A78 (TIGERLAKE)
[16:44:42] [PASSED] 0x9AC0 (TIGERLAKE)
[16:44:42] [PASSED] 0x9AC9 (TIGERLAKE)
[16:44:42] [PASSED] 0x9AD9 (TIGERLAKE)
[16:44:42] [PASSED] 0x9AF8 (TIGERLAKE)
[16:44:42] [PASSED] 0x4C80 (ROCKETLAKE)
[16:44:42] [PASSED] 0x4C8A (ROCKETLAKE)
[16:44:42] [PASSED] 0x4C8B (ROCKETLAKE)
[16:44:42] [PASSED] 0x4C8C (ROCKETLAKE)
[16:44:42] [PASSED] 0x4C90 (ROCKETLAKE)
[16:44:42] [PASSED] 0x4C9A (ROCKETLAKE)
[16:44:42] [PASSED] 0x4680 (ALDERLAKE_S)
[16:44:42] [PASSED] 0x4682 (ALDERLAKE_S)
[16:44:42] [PASSED] 0x4688 (ALDERLAKE_S)
[16:44:42] [PASSED] 0x468A (ALDERLAKE_S)
[16:44:42] [PASSED] 0x468B (ALDERLAKE_S)
[16:44:42] [PASSED] 0x4690 (ALDERLAKE_S)
[16:44:42] [PASSED] 0x4692 (ALDERLAKE_S)
[16:44:42] [PASSED] 0x4693 (ALDERLAKE_S)
[16:44:42] [PASSED] 0x46A0 (ALDERLAKE_P)
[16:44:42] [PASSED] 0x46A1 (ALDERLAKE_P)
[16:44:42] [PASSED] 0x46A2 (ALDERLAKE_P)
[16:44:42] [PASSED] 0x46A3 (ALDERLAKE_P)
[16:44:42] [PASSED] 0x46A6 (ALDERLAKE_P)
[16:44:42] [PASSED] 0x46A8 (ALDERLAKE_P)
[16:44:42] [PASSED] 0x46AA (ALDERLAKE_P)
[16:44:42] [PASSED] 0x462A (ALDERLAKE_P)
[16:44:42] [PASSED] 0x4626 (ALDERLAKE_P)
[16:44:42] [PASSED] 0x4628 (ALDERLAKE_P)
[16:44:42] [PASSED] 0x46B0 (ALDERLAKE_P)
[16:44:42] [PASSED] 0x46B1 (ALDERLAKE_P)
[16:44:42] [PASSED] 0x46B2 (ALDERLAKE_P)
[16:44:42] [PASSED] 0x46B3 (ALDERLAKE_P)
[16:44:42] [PASSED] 0x46C0 (ALDERLAKE_P)
[16:44:42] [PASSED] 0x46C1 (ALDERLAKE_P)
[16:44:42] [PASSED] 0x46C2 (ALDERLAKE_P)
[16:44:42] [PASSED] 0x46C3 (ALDERLAKE_P)
[16:44:42] [PASSED] 0x46D0 (ALDERLAKE_N)
[16:44:42] [PASSED] 0x46D1 (ALDERLAKE_N)
[16:44:42] [PASSED] 0x46D2 (ALDERLAKE_N)
[16:44:42] [PASSED] 0x46D3 (ALDERLAKE_N)
[16:44:42] [PASSED] 0x46D4 (ALDERLAKE_N)
[16:44:42] [PASSED] 0xA721 (ALDERLAKE_P)
[16:44:42] [PASSED] 0xA7A1 (ALDERLAKE_P)
[16:44:42] [PASSED] 0xA7A9 (ALDERLAKE_P)
[16:44:42] [PASSED] 0xA7AC (ALDERLAKE_P)
[16:44:42] [PASSED] 0xA7AD (ALDERLAKE_P)
[16:44:42] [PASSED] 0xA720 (ALDERLAKE_P)
[16:44:42] [PASSED] 0xA7A0 (ALDERLAKE_P)
[16:44:42] [PASSED] 0xA7A8 (ALDERLAKE_P)
[16:44:42] [PASSED] 0xA7AA (ALDERLAKE_P)
[16:44:42] [PASSED] 0xA7AB (ALDERLAKE_P)
[16:44:42] [PASSED] 0xA780 (ALDERLAKE_S)
[16:44:42] [PASSED] 0xA781 (ALDERLAKE_S)
[16:44:42] [PASSED] 0xA782 (ALDERLAKE_S)
[16:44:42] [PASSED] 0xA783 (ALDERLAKE_S)
[16:44:42] [PASSED] 0xA788 (ALDERLAKE_S)
[16:44:42] [PASSED] 0xA789 (ALDERLAKE_S)
[16:44:42] [PASSED] 0xA78A (ALDERLAKE_S)
[16:44:42] [PASSED] 0xA78B (ALDERLAKE_S)
[16:44:42] [PASSED] 0x4905 (DG1)
[16:44:42] [PASSED] 0x4906 (DG1)
[16:44:42] [PASSED] 0x4907 (DG1)
[16:44:42] [PASSED] 0x4908 (DG1)
[16:44:42] [PASSED] 0x4909 (DG1)
[16:44:42] [PASSED] 0x56C0 (DG2)
[16:44:42] [PASSED] 0x56C2 (DG2)
[16:44:42] [PASSED] 0x56C1 (DG2)
[16:44:42] [PASSED] 0x7D51 (METEORLAKE)
[16:44:42] [PASSED] 0x7DD1 (METEORLAKE)
[16:44:42] [PASSED] 0x7D41 (METEORLAKE)
[16:44:42] [PASSED] 0x7D67 (METEORLAKE)
[16:44:42] [PASSED] 0xB640 (METEORLAKE)
[16:44:42] [PASSED] 0x56A0 (DG2)
[16:44:42] [PASSED] 0x56A1 (DG2)
[16:44:42] [PASSED] 0x56A2 (DG2)
[16:44:42] [PASSED] 0x56BE (DG2)
[16:44:42] [PASSED] 0x56BF (DG2)
[16:44:42] [PASSED] 0x5690 (DG2)
[16:44:42] [PASSED] 0x5691 (DG2)
[16:44:42] [PASSED] 0x5692 (DG2)
[16:44:42] [PASSED] 0x56A5 (DG2)
[16:44:42] [PASSED] 0x56A6 (DG2)
[16:44:42] [PASSED] 0x56B0 (DG2)
[16:44:42] [PASSED] 0x56B1 (DG2)
[16:44:42] [PASSED] 0x56BA (DG2)
[16:44:42] [PASSED] 0x56BB (DG2)
[16:44:42] [PASSED] 0x56BC (DG2)
[16:44:42] [PASSED] 0x56BD (DG2)
[16:44:42] [PASSED] 0x5693 (DG2)
[16:44:42] [PASSED] 0x5694 (DG2)
[16:44:42] [PASSED] 0x5695 (DG2)
[16:44:42] [PASSED] 0x56A3 (DG2)
[16:44:42] [PASSED] 0x56A4 (DG2)
[16:44:42] [PASSED] 0x56B2 (DG2)
[16:44:42] [PASSED] 0x56B3 (DG2)
[16:44:42] [PASSED] 0x5696 (DG2)
[16:44:42] [PASSED] 0x5697 (DG2)
[16:44:42] [PASSED] 0xB69 (PVC)
[16:44:42] [PASSED] 0xB6E (PVC)
[16:44:42] [PASSED] 0xBD4 (PVC)
[16:44:42] [PASSED] 0xBD5 (PVC)
[16:44:42] [PASSED] 0xBD6 (PVC)
[16:44:42] [PASSED] 0xBD7 (PVC)
[16:44:42] [PASSED] 0xBD8 (PVC)
[16:44:42] [PASSED] 0xBD9 (PVC)
[16:44:42] [PASSED] 0xBDA (PVC)
[16:44:42] [PASSED] 0xBDB (PVC)
[16:44:42] [PASSED] 0xBE0 (PVC)
[16:44:42] [PASSED] 0xBE1 (PVC)
[16:44:42] [PASSED] 0xBE5 (PVC)
[16:44:42] [PASSED] 0x7D40 (METEORLAKE)
[16:44:42] [PASSED] 0x7D45 (METEORLAKE)
[16:44:42] [PASSED] 0x7D55 (METEORLAKE)
[16:44:42] [PASSED] 0x7D60 (METEORLAKE)
[16:44:42] [PASSED] 0x7DD5 (METEORLAKE)
[16:44:42] [PASSED] 0x6420 (LUNARLAKE)
[16:44:42] [PASSED] 0x64A0 (LUNARLAKE)
[16:44:42] [PASSED] 0x64B0 (LUNARLAKE)
[16:44:42] [PASSED] 0xE202 (BATTLEMAGE)
[16:44:42] [PASSED] 0xE209 (BATTLEMAGE)
[16:44:42] [PASSED] 0xE20B (BATTLEMAGE)
[16:44:42] [PASSED] 0xE20C (BATTLEMAGE)
[16:44:42] [PASSED] 0xE20D (BATTLEMAGE)
[16:44:42] [PASSED] 0xE210 (BATTLEMAGE)
[16:44:42] [PASSED] 0xE211 (BATTLEMAGE)
[16:44:42] [PASSED] 0xE212 (BATTLEMAGE)
[16:44:42] [PASSED] 0xE216 (BATTLEMAGE)
[16:44:42] [PASSED] 0xE220 (BATTLEMAGE)
[16:44:42] [PASSED] 0xE221 (BATTLEMAGE)
[16:44:42] [PASSED] 0xE222 (BATTLEMAGE)
[16:44:42] [PASSED] 0xE223 (BATTLEMAGE)
[16:44:42] [PASSED] 0xB080 (PANTHERLAKE)
[16:44:42] [PASSED] 0xB081 (PANTHERLAKE)
[16:44:42] [PASSED] 0xB082 (PANTHERLAKE)
[16:44:42] [PASSED] 0xB083 (PANTHERLAKE)
[16:44:42] [PASSED] 0xB084 (PANTHERLAKE)
[16:44:42] [PASSED] 0xB085 (PANTHERLAKE)
[16:44:42] [PASSED] 0xB086 (PANTHERLAKE)
[16:44:42] [PASSED] 0xB087 (PANTHERLAKE)
[16:44:42] [PASSED] 0xB08F (PANTHERLAKE)
[16:44:42] [PASSED] 0xB090 (PANTHERLAKE)
[16:44:42] [PASSED] 0xB0A0 (PANTHERLAKE)
[16:44:42] [PASSED] 0xB0B0 (PANTHERLAKE)
[16:44:42] [PASSED] 0xFD80 (PANTHERLAKE)
[16:44:42] [PASSED] 0xFD81 (PANTHERLAKE)
[16:44:42] [PASSED] 0xD740 (NOVALAKE_S)
[16:44:42] [PASSED] 0xD741 (NOVALAKE_S)
[16:44:42] [PASSED] 0xD742 (NOVALAKE_S)
[16:44:42] [PASSED] 0xD743 (NOVALAKE_S)
[16:44:42] [PASSED] 0xD744 (NOVALAKE_S)
[16:44:42] [PASSED] 0xD745 (NOVALAKE_S)
[16:44:42] [PASSED] 0x674C (CRESCENTISLAND)
[16:44:42] [PASSED] 0x674D (CRESCENTISLAND)
[16:44:42] [PASSED] 0x674E (CRESCENTISLAND)
[16:44:42] [PASSED] 0x674F (CRESCENTISLAND)
[16:44:42] [PASSED] 0x6750 (CRESCENTISLAND)
[16:44:42] [PASSED] 0xD750 (NOVALAKE_P)
[16:44:42] [PASSED] 0xD751 (NOVALAKE_P)
[16:44:42] [PASSED] 0xD752 (NOVALAKE_P)
[16:44:42] [PASSED] 0xD753 (NOVALAKE_P)
[16:44:42] [PASSED] 0xD754 (NOVALAKE_P)
[16:44:42] [PASSED] 0xD755 (NOVALAKE_P)
[16:44:42] [PASSED] 0xD756 (NOVALAKE_P)
[16:44:42] [PASSED] 0xD757 (NOVALAKE_P)
[16:44:42] [PASSED] 0xD75F (NOVALAKE_P)
[16:44:42] =============== [PASSED] check_platform_desc ===============
[16:44:42] ===================== [PASSED] xe_pci ======================
[16:44:42] ============= xe_rtp_tables_test (4 subtests) ==============
[16:44:42] ================== xe_rtp_table_gt_test  ===================
[16:44:42] [PASSED] gt_was/14011060649
[16:44:42] [PASSED] gt_was/14011059788
[16:44:42] [PASSED] gt_was/14015795083
[16:44:42] [PASSED] gt_was/16021867713
[16:44:42] [PASSED] gt_was/14019449301
[16:44:42] [PASSED] gt_was/16028005424
[16:44:42] [PASSED] gt_was/14026578760
[16:44:42] [PASSED] gt_was/1409420604
[16:44:42] [PASSED] gt_was/1408615072
[16:44:42] [PASSED] gt_was/22010523718
[16:44:42] [PASSED] gt_was/14011006942
[16:44:42] [PASSED] gt_was/14014830051
[16:44:42] [PASSED] gt_was/18018781329
[16:44:42] [PASSED] gt_was/1509235366
[16:44:42] [PASSED] gt_was/18018781329
[16:44:42] [PASSED] gt_was/16016694945
[16:44:42] [PASSED] gt_was/14018575942
[16:44:42] [PASSED] gt_was/22016670082
[16:44:42] [PASSED] gt_was/22016670082
[16:44:42] [PASSED] gt_was/14017421178
[16:44:42] [PASSED] gt_was/16025250150
[16:44:42] [PASSED] gt_was/14021871409
[16:44:42] [PASSED] gt_was/16021865536
[16:44:42] [PASSED] gt_was/14021486841
[16:44:42] [PASSED] gt_was/14025160223
[16:44:42] [PASSED] gt_was/14026144927, 16029437861
[16:44:42] [PASSED] gt_was/14025635424
[16:44:42] [PASSED] gt_was/16028005424
[16:44:42] ============== [PASSED] xe_rtp_table_gt_test ===============
[16:44:42] ================== xe_rtp_table_gt_test  ===================
[16:44:42] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[16:44:42] [PASSED] gt_tunings/Tuning: 32B Access Enable
[16:44:42] [PASSED] gt_tunings/Tuning: L3 cache
[16:44:42] [PASSED] gt_tunings/Tuning: L3 cache - media
[16:44:42] [PASSED] gt_tunings/Tuning: Compression Overfetch
[16:44:42] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[16:44:42] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[16:44:42] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[16:44:42] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[16:44:42] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[16:44:42] [PASSED] gt_tunings/Tuning: Stateless compression control
[16:44:42] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[16:44:42] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[16:44:42] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[16:44:42] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[16:44:42] ============== [PASSED] xe_rtp_table_gt_test ===============
[16:44:42] ================== xe_rtp_table_oob_test  ==================
[16:44:42] [PASSED] oob_was/1607983814
[16:44:42] [PASSED] oob_was/16010904313
[16:44:42] [PASSED] oob_was/18022495364
[16:44:42] [PASSED] oob_was/22012773006
[16:44:42] [PASSED] oob_was/14014475959
[16:44:42] [PASSED] oob_was/22011391025
[16:44:42] [PASSED] oob_was/22012727170
[16:44:42] [PASSED] oob_was/22012727685
[16:44:42] [PASSED] oob_was/22016596838
[16:44:42] [PASSED] oob_was/18020744125
[16:44:42] [PASSED] oob_was/1409600907
[16:44:42] [PASSED] oob_was/22014953428
[16:44:42] [PASSED] oob_was/16017236439
[16:44:42] [PASSED] oob_was/14019821291
[16:44:42] [PASSED] oob_was/14015076503
[16:44:42] [PASSED] oob_was/14018913170
[16:44:42] [PASSED] oob_was/14018094691
[16:44:42] [PASSED] oob_was/18024947630
[16:44:42] [PASSED] oob_was/16022287689
[16:44:42] [PASSED] oob_was/13011645652
[16:44:42] [PASSED] oob_was/14022293748
[16:44:42] [PASSED] oob_was/22019794406
[16:44:42] [PASSED] oob_was/22019338487
[16:44:42] [PASSED] oob_was/16023588340
[16:44:42] [PASSED] oob_was/14019789679
[16:44:42] [PASSED] oob_was/14022866841
[16:44:42] [PASSED] oob_was/16021333562
[16:44:42] [PASSED] oob_was/14016712196
[16:44:42] [PASSED] oob_was/14015568240
[16:44:42] [PASSED] oob_was/18013179988
[16:44:42] [PASSED] oob_was/1508761755
[16:44:42] [PASSED] oob_was/16023105232
[16:44:42] [PASSED] oob_was/16026508708
[16:44:42] [PASSED] oob_was/14020001231
[16:44:42] [PASSED] oob_was/16023683509
[16:44:42] [PASSED] oob_was/14025515070
[16:44:42] [PASSED] oob_was/15015404425_disable
[16:44:42] [PASSED] oob_was/16026007364
[16:44:42] [PASSED] oob_was/14020316580
[16:44:42] [PASSED] oob_was/14025883347
[16:44:42] ============== [PASSED] xe_rtp_table_oob_test ==============
[16:44:42] ================ xe_rtp_table_dev_oob_test  ================
[16:44:42] [PASSED] device_oob_was/22010954014
[16:44:42] [PASSED] device_oob_was/15015404425
[16:44:42] [PASSED] device_oob_was/22019338487_display
[16:44:42] [PASSED] device_oob_was/14022085890
[16:44:42] [PASSED] device_oob_was/14026539277
[16:44:42] [PASSED] device_oob_was/14026633728
[16:44:42] [PASSED] device_oob_was/14026746987
[16:44:42] [PASSED] device_oob_was/14026779378
[16:44:42] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[16:44:42] =============== [PASSED] xe_rtp_tables_test ================
[16:44:42] =================== xe_rtp (3 subtests) ====================
[16:44:42] =================== xe_rtp_rules_tests  ====================
[16:44:42] [PASSED] no
[16:44:42] [PASSED] yes
[16:44:42] [PASSED] no-and-no
[16:44:42] [PASSED] no-and-yes
[16:44:42] [PASSED] yes-and-no
[16:44:42] [PASSED] yes-and-yes
[16:44:42] [PASSED] no-or-no
[16:44:42] [PASSED] no-or-yes
[16:44:42] [PASSED] yes-or-no
[16:44:42] [PASSED] yes-or-yes
[16:44:42] [PASSED] no-yes-or-yes-no
[16:44:42] [PASSED] no-yes-or-yes-yes
[16:44:42] [PASSED] yes-yes-or-no-yes
[16:44:42] [PASSED] yes-yes-or-yes-yes
[16:44:42] [PASSED] no-no-or-yes-or-no
[16:44:42] [PASSED] or
[16:44:42] [PASSED] or-yes
[16:44:42] [PASSED] or-no
[16:44:42] [PASSED] yes-or
[16:44:42] [PASSED] no-or
[16:44:42] [PASSED] no-or-or-yes
[16:44:42] [PASSED] yes-or-or-no
[16:44:42] [PASSED] no-or-or-no
[16:44:42] [PASSED] missing-context-engine-class
[16:44:42] [PASSED] missing-context-engine-class-or-yes
[16:44:42] [PASSED] missing-context-engine-class-or-or-yes
[16:44:42] =============== [PASSED] xe_rtp_rules_tests ================
[16:44:42] =============== xe_rtp_process_to_sr_tests  ================
[16:44:42] [PASSED] coalesce-same-reg
[16:44:42] [PASSED] no-match-no-add
[16:44:42] [PASSED] two-regs-two-entries
[16:44:42] [PASSED] clr-one-set-other
[16:44:42] [PASSED] set-field
[16:44:42] [PASSED] conflict-duplicate
[16:44:42] [PASSED] conflict-not-disjoint
[16:44:42] [PASSED] conflict-reg-type
[16:44:42] [PASSED] bad-mcr-reg-forced-to-regular
[16:44:42] [PASSED] bad-regular-reg-forced-to-mcr
[16:44:42] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[16:44:42] ================== xe_rtp_process_tests  ===================
[16:44:42] [PASSED] active1
[16:44:42] [PASSED] active2
[16:44:42] [PASSED] active-inactive
[16:44:42] [PASSED] inactive-active
[16:44:42] [PASSED] inactive-active-inactive
[16:44:42] [PASSED] inactive-inactive-inactive
[16:44:42] ============== [PASSED] xe_rtp_process_tests ===============
[16:44:42] ===================== [PASSED] xe_rtp ======================
[16:44:42] ==================== xe_wa (1 subtest) =====================
[16:44:42] ======================== xe_wa_gt  =========================
[16:44:42] [PASSED] TIGERLAKE B0
[16:44:42] [PASSED] DG1 A0
[16:44:42] [PASSED] DG1 B0
[16:44:42] [PASSED] ALDERLAKE_S A0
[16:44:42] [PASSED] ALDERLAKE_S B0
[16:44:42] [PASSED] ALDERLAKE_S C0
[16:44:42] [PASSED] ALDERLAKE_S D0
[16:44:42] [PASSED] ALDERLAKE_P A0
[16:44:42] [PASSED] ALDERLAKE_P B0
[16:44:42] [PASSED] ALDERLAKE_P C0
[16:44:42] [PASSED] ALDERLAKE_S RPLS D0
[16:44:42] [PASSED] ALDERLAKE_P RPLU E0
[16:44:42] [PASSED] DG2 G10 C0
[16:44:42] [PASSED] DG2 G11 B1
[16:44:42] [PASSED] DG2 G12 A1
[16:44:42] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[16:44:42] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[16:44:42] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[16:44:42] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[16:44:42] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[16:44:42] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[16:44:42] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[16:44:42] ==================== [PASSED] xe_wa_gt =====================
[16:44:42] ====================== [PASSED] xe_wa ======================
[16:44:42] ============================================================
[16:44:42] Testing complete. Ran 715 tests: passed: 697, skipped: 18
[16:44:42] Elapsed time: 36.291s total, 4.291s configuring, 31.333s building, 0.648s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[16:44:42] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[16:44:44] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[16:45:08] Starting KUnit Kernel (1/1)...
[16:45:08] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[16:45:08] ============ drm_test_pick_cmdline (2 subtests) ============
[16:45:08] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[16:45:08] =============== drm_test_pick_cmdline_named  ===============
[16:45:08] [PASSED] NTSC
[16:45:08] [PASSED] NTSC-J
[16:45:08] [PASSED] PAL
[16:45:08] [PASSED] PAL-M
[16:45:08] =========== [PASSED] drm_test_pick_cmdline_named ===========
[16:45:08] ============== [PASSED] drm_test_pick_cmdline ==============
[16:45:08] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[16:45:08] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[16:45:08] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[16:45:08] =========== drm_validate_clone_mode (2 subtests) ===========
[16:45:08] ============== drm_test_check_in_clone_mode  ===============
[16:45:08] [PASSED] in_clone_mode
[16:45:08] [PASSED] not_in_clone_mode
[16:45:08] ========== [PASSED] drm_test_check_in_clone_mode ===========
[16:45:08] =============== drm_test_check_valid_clones  ===============
[16:45:08] [PASSED] not_in_clone_mode
[16:45:08] [PASSED] valid_clone
[16:45:08] [PASSED] invalid_clone
[16:45:08] =========== [PASSED] drm_test_check_valid_clones ===========
[16:45:08] ============= [PASSED] drm_validate_clone_mode =============
[16:45:08] ============= drm_validate_modeset (1 subtest) =============
[16:45:08] [PASSED] drm_test_check_connector_changed_modeset
[16:45:08] ============== [PASSED] drm_validate_modeset ===============
[16:45:08] ====== drm_test_bridge_get_current_state (2 subtests) ======
[16:45:08] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[16:45:08] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[16:45:08] ======== [PASSED] drm_test_bridge_get_current_state ========
[16:45:08] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[16:45:08] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[16:45:08] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[16:45:08] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[16:45:08] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[16:45:08] ============== drm_bridge_alloc (2 subtests) ===============
[16:45:08] [PASSED] drm_test_drm_bridge_alloc_basic
[16:45:08] [PASSED] drm_test_drm_bridge_alloc_get_put
[16:45:08] ================ [PASSED] drm_bridge_alloc =================
[16:45:08] ============= drm_cmdline_parser (40 subtests) =============
[16:45:08] [PASSED] drm_test_cmdline_force_d_only
[16:45:08] [PASSED] drm_test_cmdline_force_D_only_dvi
[16:45:08] [PASSED] drm_test_cmdline_force_D_only_hdmi
[16:45:08] [PASSED] drm_test_cmdline_force_D_only_not_digital
[16:45:08] [PASSED] drm_test_cmdline_force_e_only
[16:45:08] [PASSED] drm_test_cmdline_res
[16:45:08] [PASSED] drm_test_cmdline_res_vesa
[16:45:08] [PASSED] drm_test_cmdline_res_vesa_rblank
[16:45:08] [PASSED] drm_test_cmdline_res_rblank
[16:45:08] [PASSED] drm_test_cmdline_res_bpp
[16:45:08] [PASSED] drm_test_cmdline_res_refresh
[16:45:08] [PASSED] drm_test_cmdline_res_bpp_refresh
[16:45:08] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[16:45:08] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[16:45:08] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[16:45:08] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[16:45:08] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[16:45:08] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[16:45:08] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[16:45:08] [PASSED] drm_test_cmdline_res_margins_force_on
[16:45:08] [PASSED] drm_test_cmdline_res_vesa_margins
[16:45:08] [PASSED] drm_test_cmdline_name
[16:45:08] [PASSED] drm_test_cmdline_name_bpp
[16:45:08] [PASSED] drm_test_cmdline_name_option
[16:45:08] [PASSED] drm_test_cmdline_name_bpp_option
[16:45:08] [PASSED] drm_test_cmdline_rotate_0
[16:45:08] [PASSED] drm_test_cmdline_rotate_90
[16:45:08] [PASSED] drm_test_cmdline_rotate_180
[16:45:08] [PASSED] drm_test_cmdline_rotate_270
[16:45:08] [PASSED] drm_test_cmdline_hmirror
[16:45:08] [PASSED] drm_test_cmdline_vmirror
[16:45:08] [PASSED] drm_test_cmdline_margin_options
[16:45:08] [PASSED] drm_test_cmdline_multiple_options
[16:45:08] [PASSED] drm_test_cmdline_bpp_extra_and_option
[16:45:08] [PASSED] drm_test_cmdline_extra_and_option
[16:45:08] [PASSED] drm_test_cmdline_freestanding_options
[16:45:08] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[16:45:08] [PASSED] drm_test_cmdline_panel_orientation
[16:45:08] ================ drm_test_cmdline_invalid  =================
[16:45:08] [PASSED] margin_only
[16:45:08] [PASSED] interlace_only
[16:45:08] [PASSED] res_missing_x
[16:45:08] [PASSED] res_missing_y
[16:45:08] [PASSED] res_bad_y
[16:45:08] [PASSED] res_missing_y_bpp
[16:45:08] [PASSED] res_bad_bpp
[16:45:08] [PASSED] res_bad_refresh
[16:45:08] [PASSED] res_bpp_refresh_force_on_off
[16:45:08] [PASSED] res_invalid_mode
[16:45:08] [PASSED] res_bpp_wrong_place_mode
[16:45:08] [PASSED] name_bpp_refresh
[16:45:08] [PASSED] name_refresh
[16:45:08] [PASSED] name_refresh_wrong_mode
[16:45:08] [PASSED] name_refresh_invalid_mode
[16:45:08] [PASSED] rotate_multiple
[16:45:08] [PASSED] rotate_invalid_val
[16:45:08] [PASSED] rotate_truncated
[16:45:08] [PASSED] invalid_option
[16:45:08] [PASSED] invalid_tv_option
[16:45:08] [PASSED] truncated_tv_option
[16:45:08] ============ [PASSED] drm_test_cmdline_invalid =============
[16:45:08] =============== drm_test_cmdline_tv_options  ===============
[16:45:08] [PASSED] NTSC
[16:45:08] [PASSED] NTSC_443
[16:45:08] [PASSED] NTSC_J
[16:45:08] [PASSED] PAL
[16:45:08] [PASSED] PAL_M
[16:45:08] [PASSED] PAL_N
[16:45:08] [PASSED] SECAM
[16:45:08] [PASSED] MONO_525
[16:45:08] [PASSED] MONO_625
[16:45:08] =========== [PASSED] drm_test_cmdline_tv_options ===========
[16:45:08] =============== [PASSED] drm_cmdline_parser ================
[16:45:08] ========== drmm_connector_hdmi_init (20 subtests) ==========
[16:45:08] [PASSED] drm_test_connector_hdmi_init_valid
[16:45:08] [PASSED] drm_test_connector_hdmi_init_bpc_8
[16:45:08] [PASSED] drm_test_connector_hdmi_init_bpc_10
[16:45:08] [PASSED] drm_test_connector_hdmi_init_bpc_12
[16:45:08] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[16:45:08] [PASSED] drm_test_connector_hdmi_init_bpc_null
[16:45:08] [PASSED] drm_test_connector_hdmi_init_formats_empty
[16:45:08] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[16:45:08] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[16:45:08] [PASSED] supported_formats=0x9 yuv420_allowed=1
[16:45:08] [PASSED] supported_formats=0x9 yuv420_allowed=0
[16:45:08] [PASSED] supported_formats=0x5 yuv420_allowed=1
[16:45:08] [PASSED] supported_formats=0x5 yuv420_allowed=0
[16:45:08] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[16:45:08] [PASSED] drm_test_connector_hdmi_init_null_ddc
[16:45:08] [PASSED] drm_test_connector_hdmi_init_null_product
[16:45:08] [PASSED] drm_test_connector_hdmi_init_null_vendor
[16:45:08] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[16:45:08] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[16:45:08] [PASSED] drm_test_connector_hdmi_init_product_valid
[16:45:08] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[16:45:08] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[16:45:08] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[16:45:08] ========= drm_test_connector_hdmi_init_type_valid  =========
[16:45:08] [PASSED] HDMI-A
[16:45:08] [PASSED] HDMI-B
[16:45:08] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[16:45:08] ======== drm_test_connector_hdmi_init_type_invalid  ========
[16:45:08] [PASSED] Unknown
[16:45:08] [PASSED] VGA
[16:45:08] [PASSED] DVI-I
[16:45:08] [PASSED] DVI-D
[16:45:08] [PASSED] DVI-A
[16:45:08] [PASSED] Composite
[16:45:08] [PASSED] SVIDEO
[16:45:08] [PASSED] LVDS
[16:45:08] [PASSED] Component
[16:45:08] [PASSED] DIN
[16:45:08] [PASSED] DP
[16:45:08] [PASSED] TV
[16:45:08] [PASSED] eDP
[16:45:08] [PASSED] Virtual
[16:45:08] [PASSED] DSI
[16:45:08] [PASSED] DPI
[16:45:08] [PASSED] Writeback
[16:45:08] [PASSED] SPI
[16:45:08] [PASSED] USB
[16:45:08] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[16:45:08] ============ [PASSED] drmm_connector_hdmi_init =============
[16:45:08] ============= drmm_connector_init (3 subtests) =============
[16:45:08] [PASSED] drm_test_drmm_connector_init
[16:45:08] [PASSED] drm_test_drmm_connector_init_null_ddc
[16:45:08] ========= drm_test_drmm_connector_init_type_valid  =========
[16:45:08] [PASSED] Unknown
[16:45:08] [PASSED] VGA
[16:45:08] [PASSED] DVI-I
[16:45:08] [PASSED] DVI-D
[16:45:08] [PASSED] DVI-A
[16:45:08] [PASSED] Composite
[16:45:08] [PASSED] SVIDEO
[16:45:08] [PASSED] LVDS
[16:45:08] [PASSED] Component
[16:45:08] [PASSED] DIN
[16:45:08] [PASSED] DP
[16:45:08] [PASSED] HDMI-A
[16:45:08] [PASSED] HDMI-B
[16:45:08] [PASSED] TV
[16:45:08] [PASSED] eDP
[16:45:08] [PASSED] Virtual
[16:45:08] [PASSED] DSI
[16:45:08] [PASSED] DPI
[16:45:08] [PASSED] Writeback
[16:45:08] [PASSED] SPI
[16:45:08] [PASSED] USB
[16:45:08] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[16:45:08] =============== [PASSED] drmm_connector_init ===============
[16:45:08] ========= drm_connector_dynamic_init (6 subtests) ==========
[16:45:08] [PASSED] drm_test_drm_connector_dynamic_init
[16:45:08] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[16:45:08] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[16:45:08] [PASSED] drm_test_drm_connector_dynamic_init_properties
[16:45:08] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[16:45:08] [PASSED] Unknown
[16:45:08] [PASSED] VGA
[16:45:08] [PASSED] DVI-I
[16:45:08] [PASSED] DVI-D
[16:45:08] [PASSED] DVI-A
[16:45:08] [PASSED] Composite
[16:45:08] [PASSED] SVIDEO
[16:45:08] [PASSED] LVDS
[16:45:08] [PASSED] Component
[16:45:08] [PASSED] DIN
[16:45:08] [PASSED] DP
[16:45:08] [PASSED] HDMI-A
[16:45:08] [PASSED] HDMI-B
[16:45:08] [PASSED] TV
[16:45:08] [PASSED] eDP
[16:45:08] [PASSED] Virtual
[16:45:08] [PASSED] DSI
[16:45:08] [PASSED] DPI
[16:45:08] [PASSED] Writeback
[16:45:08] [PASSED] SPI
[16:45:08] [PASSED] USB
[16:45:08] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[16:45:08] ======== drm_test_drm_connector_dynamic_init_name  =========
[16:45:08] [PASSED] Unknown
[16:45:08] [PASSED] VGA
[16:45:08] [PASSED] DVI-I
[16:45:08] [PASSED] DVI-D
[16:45:08] [PASSED] DVI-A
[16:45:08] [PASSED] Composite
[16:45:08] [PASSED] SVIDEO
[16:45:08] [PASSED] LVDS
[16:45:08] [PASSED] Component
[16:45:08] [PASSED] DIN
[16:45:08] [PASSED] DP
[16:45:08] [PASSED] HDMI-A
[16:45:08] [PASSED] HDMI-B
[16:45:08] [PASSED] TV
[16:45:08] [PASSED] eDP
[16:45:08] [PASSED] Virtual
[16:45:08] [PASSED] DSI
[16:45:08] [PASSED] DPI
[16:45:08] [PASSED] Writeback
[16:45:08] [PASSED] SPI
[16:45:08] [PASSED] USB
[16:45:08] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[16:45:08] =========== [PASSED] drm_connector_dynamic_init ============
[16:45:08] ==== drm_connector_dynamic_register_early (4 subtests) =====
[16:45:08] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[16:45:08] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[16:45:08] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[16:45:08] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[16:45:08] ====== [PASSED] drm_connector_dynamic_register_early =======
[16:45:08] ======= drm_connector_dynamic_register (7 subtests) ========
[16:45:08] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[16:45:08] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[16:45:08] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[16:45:08] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[16:45:08] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[16:45:08] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[16:45:08] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[16:45:08] ========= [PASSED] drm_connector_dynamic_register ==========
[16:45:08] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[16:45:08] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[16:45:08] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[16:45:08] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[16:45:08] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[16:45:08] ========== drm_test_get_tv_mode_from_name_valid  ===========
[16:45:08] [PASSED] NTSC
[16:45:08] [PASSED] NTSC-443
[16:45:08] [PASSED] NTSC-J
[16:45:08] [PASSED] PAL
[16:45:08] [PASSED] PAL-M
[16:45:08] [PASSED] PAL-N
[16:45:08] [PASSED] SECAM
[16:45:08] [PASSED] Mono
[16:45:08] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[16:45:08] [PASSED] drm_test_get_tv_mode_from_name_truncated
[16:45:08] ============ [PASSED] drm_get_tv_mode_from_name ============
[16:45:08] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[16:45:08] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[16:45:08] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[16:45:08] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[16:45:08] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[16:45:08] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[16:45:08] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[16:45:08] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[16:45:08] [PASSED] VIC 96
[16:45:08] [PASSED] VIC 97
[16:45:08] [PASSED] VIC 101
[16:45:08] [PASSED] VIC 102
[16:45:08] [PASSED] VIC 106
[16:45:08] [PASSED] VIC 107
[16:45:08] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[16:45:08] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[16:45:08] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[16:45:08] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[16:45:08] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[16:45:08] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[16:45:08] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[16:45:08] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[16:45:08] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[16:45:08] [PASSED] Automatic
[16:45:08] [PASSED] Full
[16:45:08] [PASSED] Limited 16:235
[16:45:08] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[16:45:08] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[16:45:08] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[16:45:08] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[16:45:08] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[16:45:08] [PASSED] RGB
[16:45:08] [PASSED] YUV 4:2:0
[16:45:08] [PASSED] YUV 4:2:2
[16:45:08] [PASSED] YUV 4:4:4
[16:45:08] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[16:45:08] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[16:45:08] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[16:45:08] ============= drm_damage_helper (21 subtests) ==============
[16:45:08] [PASSED] drm_test_damage_iter_no_damage
[16:45:08] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[16:45:08] [PASSED] drm_test_damage_iter_no_damage_src_moved
[16:45:08] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[16:45:08] [PASSED] drm_test_damage_iter_no_damage_not_visible
[16:45:08] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[16:45:08] [PASSED] drm_test_damage_iter_no_damage_no_fb
[16:45:08] [PASSED] drm_test_damage_iter_simple_damage
[16:45:08] [PASSED] drm_test_damage_iter_single_damage
[16:45:08] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[16:45:08] [PASSED] drm_test_damage_iter_single_damage_outside_src
[16:45:08] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[16:45:08] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[16:45:08] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[16:45:08] [PASSED] drm_test_damage_iter_single_damage_src_moved
[16:45:08] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[16:45:08] [PASSED] drm_test_damage_iter_damage
[16:45:08] [PASSED] drm_test_damage_iter_damage_one_intersect
[16:45:08] [PASSED] drm_test_damage_iter_damage_one_outside
[16:45:08] [PASSED] drm_test_damage_iter_damage_src_moved
[16:45:08] [PASSED] drm_test_damage_iter_damage_not_visible
[16:45:08] ================ [PASSED] drm_damage_helper ================
[16:45:08] ============== drm_dp_mst_helper (3 subtests) ==============
[16:45:08] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[16:45:08] [PASSED] Clock 154000 BPP 30 DSC disabled
[16:45:08] [PASSED] Clock 234000 BPP 30 DSC disabled
[16:45:08] [PASSED] Clock 297000 BPP 24 DSC disabled
[16:45:08] [PASSED] Clock 332880 BPP 24 DSC enabled
[16:45:08] [PASSED] Clock 324540 BPP 24 DSC enabled
[16:45:08] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[16:45:08] ============== drm_test_dp_mst_calc_pbn_div  ===============
[16:45:08] [PASSED] Link rate 2000000 lane count 4
[16:45:08] [PASSED] Link rate 2000000 lane count 2
[16:45:08] [PASSED] Link rate 2000000 lane count 1
[16:45:08] [PASSED] Link rate 1350000 lane count 4
[16:45:08] [PASSED] Link rate 1350000 lane count 2
[16:45:08] [PASSED] Link rate 1350000 lane count 1
[16:45:08] [PASSED] Link rate 1000000 lane count 4
[16:45:08] [PASSED] Link rate 1000000 lane count 2
[16:45:08] [PASSED] Link rate 1000000 lane count 1
[16:45:08] [PASSED] Link rate 810000 lane count 4
[16:45:08] [PASSED] Link rate 810000 lane count 2
[16:45:08] [PASSED] Link rate 810000 lane count 1
[16:45:08] [PASSED] Link rate 540000 lane count 4
[16:45:08] [PASSED] Link rate 540000 lane count 2
[16:45:08] [PASSED] Link rate 540000 lane count 1
[16:45:08] [PASSED] Link rate 270000 lane count 4
[16:45:08] [PASSED] Link rate 270000 lane count 2
[16:45:08] [PASSED] Link rate 270000 lane count 1
[16:45:08] [PASSED] Link rate 162000 lane count 4
[16:45:08] [PASSED] Link rate 162000 lane count 2
[16:45:08] [PASSED] Link rate 162000 lane count 1
[16:45:08] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[16:45:08] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[16:45:08] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[16:45:08] [PASSED] DP_POWER_UP_PHY with port number
[16:45:08] [PASSED] DP_POWER_DOWN_PHY with port number
[16:45:08] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[16:45:08] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[16:45:08] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[16:45:08] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[16:45:08] [PASSED] DP_QUERY_PAYLOAD with port number
[16:45:08] [PASSED] DP_QUERY_PAYLOAD with VCPI
[16:45:08] [PASSED] DP_REMOTE_DPCD_READ with port number
[16:45:08] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[16:45:08] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[16:45:08] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[16:45:08] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[16:45:08] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[16:45:08] [PASSED] DP_REMOTE_I2C_READ with port number
[16:45:08] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[16:45:08] [PASSED] DP_REMOTE_I2C_READ with transactions array
[16:45:08] [PASSED] DP_REMOTE_I2C_WRITE with port number
[16:45:08] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[16:45:08] [PASSED] DP_REMOTE_I2C_WRITE with data array
[16:45:08] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[16:45:08] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[16:45:08] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[16:45:08] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[16:45:08] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[16:45:08] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[16:45:08] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[16:45:08] ================ [PASSED] drm_dp_mst_helper ================
[16:45:08] ================== drm_exec (7 subtests) ===================
[16:45:08] [PASSED] sanitycheck
[16:45:08] [PASSED] test_lock
[16:45:08] [PASSED] test_lock_unlock
[16:45:08] [PASSED] test_duplicates
[16:45:08] [PASSED] test_prepare
[16:45:08] [PASSED] test_prepare_array
[16:45:08] [PASSED] test_multiple_loops
[16:45:08] ==================== [PASSED] drm_exec =====================
[16:45:08] =========== drm_format_helper_test (17 subtests) ===========
[16:45:08] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[16:45:08] [PASSED] single_pixel_source_buffer
[16:45:08] [PASSED] single_pixel_clip_rectangle
[16:45:08] [PASSED] well_known_colors
[16:45:08] [PASSED] destination_pitch
[16:45:08] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[16:45:08] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[16:45:08] [PASSED] single_pixel_source_buffer
[16:45:08] [PASSED] single_pixel_clip_rectangle
[16:45:08] [PASSED] well_known_colors
[16:45:08] [PASSED] destination_pitch
[16:45:08] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[16:45:08] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[16:45:08] [PASSED] single_pixel_source_buffer
[16:45:08] [PASSED] single_pixel_clip_rectangle
[16:45:08] [PASSED] well_known_colors
[16:45:08] [PASSED] destination_pitch
[16:45:08] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[16:45:08] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[16:45:08] [PASSED] single_pixel_source_buffer
[16:45:08] [PASSED] single_pixel_clip_rectangle
[16:45:08] [PASSED] well_known_colors
[16:45:08] [PASSED] destination_pitch
[16:45:08] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[16:45:08] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[16:45:08] [PASSED] single_pixel_source_buffer
[16:45:08] [PASSED] single_pixel_clip_rectangle
[16:45:08] [PASSED] well_known_colors
[16:45:08] [PASSED] destination_pitch
[16:45:08] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[16:45:08] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[16:45:08] [PASSED] single_pixel_source_buffer
[16:45:08] [PASSED] single_pixel_clip_rectangle
[16:45:08] [PASSED] well_known_colors
[16:45:08] [PASSED] destination_pitch
[16:45:08] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[16:45:08] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[16:45:08] [PASSED] single_pixel_source_buffer
[16:45:08] [PASSED] single_pixel_clip_rectangle
[16:45:08] [PASSED] well_known_colors
[16:45:08] [PASSED] destination_pitch
[16:45:08] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[16:45:08] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[16:45:08] [PASSED] single_pixel_source_buffer
[16:45:08] [PASSED] single_pixel_clip_rectangle
[16:45:08] [PASSED] well_known_colors
[16:45:08] [PASSED] destination_pitch
[16:45:08] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[16:45:08] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[16:45:08] [PASSED] single_pixel_source_buffer
[16:45:08] [PASSED] single_pixel_clip_rectangle
[16:45:08] [PASSED] well_known_colors
[16:45:08] [PASSED] destination_pitch
[16:45:08] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[16:45:08] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[16:45:08] [PASSED] single_pixel_source_buffer
[16:45:08] [PASSED] single_pixel_clip_rectangle
[16:45:08] [PASSED] well_known_colors
[16:45:08] [PASSED] destination_pitch
[16:45:08] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[16:45:08] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[16:45:08] [PASSED] single_pixel_source_buffer
[16:45:08] [PASSED] single_pixel_clip_rectangle
[16:45:08] [PASSED] well_known_colors
[16:45:08] [PASSED] destination_pitch
[16:45:08] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[16:45:08] ============== drm_test_fb_xrgb8888_to_mono  ===============
[16:45:08] [PASSED] single_pixel_source_buffer
[16:45:08] [PASSED] single_pixel_clip_rectangle
[16:45:08] [PASSED] well_known_colors
[16:45:08] [PASSED] destination_pitch
[16:45:08] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[16:45:08] ==================== drm_test_fb_swab  =====================
[16:45:08] [PASSED] single_pixel_source_buffer
[16:45:08] [PASSED] single_pixel_clip_rectangle
[16:45:08] [PASSED] well_known_colors
[16:45:08] [PASSED] destination_pitch
[16:45:08] ================ [PASSED] drm_test_fb_swab =================
[16:45:08] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[16:45:08] [PASSED] single_pixel_source_buffer
[16:45:08] [PASSED] single_pixel_clip_rectangle
[16:45:08] [PASSED] well_known_colors
[16:45:08] [PASSED] destination_pitch
[16:45:08] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[16:45:08] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[16:45:08] [PASSED] single_pixel_source_buffer
[16:45:08] [PASSED] single_pixel_clip_rectangle
[16:45:08] [PASSED] well_known_colors
[16:45:08] [PASSED] destination_pitch
[16:45:08] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[16:45:08] ================= drm_test_fb_clip_offset  =================
[16:45:08] [PASSED] pass through
[16:45:08] [PASSED] horizontal offset
[16:45:08] [PASSED] vertical offset
[16:45:08] [PASSED] horizontal and vertical offset
[16:45:08] [PASSED] horizontal offset (custom pitch)
[16:45:08] [PASSED] vertical offset (custom pitch)
[16:45:08] [PASSED] horizontal and vertical offset (custom pitch)
[16:45:08] ============= [PASSED] drm_test_fb_clip_offset =============
[16:45:08] =================== drm_test_fb_memcpy  ====================
[16:45:08] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[16:45:08] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[16:45:08] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[16:45:08] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[16:45:08] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[16:45:08] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[16:45:08] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[16:45:08] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[16:45:08] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[16:45:08] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[16:45:08] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[16:45:08] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[16:45:08] =============== [PASSED] drm_test_fb_memcpy ================
[16:45:08] ============= [PASSED] drm_format_helper_test ==============
[16:45:08] ================= drm_format (18 subtests) =================
[16:45:08] [PASSED] drm_test_format_block_width_invalid
[16:45:08] [PASSED] drm_test_format_block_width_one_plane
[16:45:08] [PASSED] drm_test_format_block_width_two_plane
[16:45:08] [PASSED] drm_test_format_block_width_three_plane
[16:45:08] [PASSED] drm_test_format_block_width_tiled
[16:45:08] [PASSED] drm_test_format_block_height_invalid
[16:45:08] [PASSED] drm_test_format_block_height_one_plane
[16:45:08] [PASSED] drm_test_format_block_height_two_plane
[16:45:08] [PASSED] drm_test_format_block_height_three_plane
[16:45:08] [PASSED] drm_test_format_block_height_tiled
[16:45:08] [PASSED] drm_test_format_min_pitch_invalid
[16:45:08] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[16:45:08] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[16:45:08] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[16:45:08] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[16:45:08] [PASSED] drm_test_format_min_pitch_two_plane
[16:45:08] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[16:45:08] [PASSED] drm_test_format_min_pitch_tiled
[16:45:08] =================== [PASSED] drm_format ====================
[16:45:08] ============== drm_framebuffer (10 subtests) ===============
[16:45:08] ========== drm_test_framebuffer_check_src_coords  ==========
[16:45:08] [PASSED] Success: source fits into fb
[16:45:08] [PASSED] Fail: overflowing fb with x-axis coordinate
[16:45:08] [PASSED] Fail: overflowing fb with y-axis coordinate
[16:45:08] [PASSED] Fail: overflowing fb with source width
[16:45:08] [PASSED] Fail: overflowing fb with source height
[16:45:08] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[16:45:08] [PASSED] drm_test_framebuffer_cleanup
[16:45:08] =============== drm_test_framebuffer_create  ===============
[16:45:08] [PASSED] ABGR8888 normal sizes
[16:45:08] [PASSED] ABGR8888 max sizes
[16:45:08] [PASSED] ABGR8888 pitch greater than min required
[16:45:08] [PASSED] ABGR8888 pitch less than min required
[16:45:08] [PASSED] ABGR8888 Invalid width
[16:45:08] [PASSED] ABGR8888 Invalid buffer handle
[16:45:08] [PASSED] No pixel format
[16:45:08] [PASSED] ABGR8888 Width 0
[16:45:08] [PASSED] ABGR8888 Height 0
[16:45:08] [PASSED] ABGR8888 Out of bound height * pitch combination
[16:45:08] [PASSED] ABGR8888 Large buffer offset
[16:45:08] [PASSED] ABGR8888 Buffer offset for inexistent plane
[16:45:08] [PASSED] ABGR8888 Invalid flag
[16:45:08] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[16:45:08] [PASSED] ABGR8888 Valid buffer modifier
[16:45:08] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[16:45:08] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[16:45:08] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[16:45:08] [PASSED] NV12 Normal sizes
[16:45:08] [PASSED] NV12 Max sizes
[16:45:08] [PASSED] NV12 Invalid pitch
[16:45:08] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[16:45:08] [PASSED] NV12 different  modifier per-plane
[16:45:08] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[16:45:08] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[16:45:08] [PASSED] NV12 Modifier for inexistent plane
[16:45:08] [PASSED] NV12 Handle for inexistent plane
[16:45:08] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[16:45:08] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[16:45:08] [PASSED] YVU420 Normal sizes
[16:45:08] [PASSED] YVU420 Max sizes
[16:45:08] [PASSED] YVU420 Invalid pitch
[16:45:08] [PASSED] YVU420 Different pitches
[16:45:08] [PASSED] YVU420 Different buffer offsets/pitches
[16:45:08] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[16:45:08] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[16:45:08] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[16:45:08] [PASSED] YVU420 Valid modifier
[16:45:08] [PASSED] YVU420 Different modifiers per plane
[16:45:08] [PASSED] YVU420 Modifier for inexistent plane
[16:45:08] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[16:45:08] [PASSED] X0L2 Normal sizes
[16:45:08] [PASSED] X0L2 Max sizes
[16:45:08] [PASSED] X0L2 Invalid pitch
[16:45:08] [PASSED] X0L2 Pitch greater than minimum required
[16:45:08] [PASSED] X0L2 Handle for inexistent plane
[16:45:08] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[16:45:08] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[16:45:08] [PASSED] X0L2 Valid modifier
[16:45:08] [PASSED] X0L2 Modifier for inexistent plane
[16:45:08] =========== [PASSED] drm_test_framebuffer_create ===========
[16:45:08] [PASSED] drm_test_framebuffer_free
[16:45:08] [PASSED] drm_test_framebuffer_init
[16:45:08] [PASSED] drm_test_framebuffer_init_bad_format
[16:45:08] [PASSED] drm_test_framebuffer_init_dev_mismatch
[16:45:08] [PASSED] drm_test_framebuffer_lookup
[16:45:08] [PASSED] drm_test_framebuffer_lookup_inexistent
[16:45:08] [PASSED] drm_test_framebuffer_modifiers_not_supported
[16:45:08] ================= [PASSED] drm_framebuffer =================
[16:45:08] ================ drm_gem_shmem (8 subtests) ================
[16:45:08] [PASSED] drm_gem_shmem_test_obj_create
[16:45:08] [PASSED] drm_gem_shmem_test_obj_create_private
[16:45:08] [PASSED] drm_gem_shmem_test_pin_pages
[16:45:08] [PASSED] drm_gem_shmem_test_vmap
[16:45:08] [PASSED] drm_gem_shmem_test_get_sg_table
[16:45:08] [PASSED] drm_gem_shmem_test_get_pages_sgt
[16:45:08] [PASSED] drm_gem_shmem_test_madvise
[16:45:08] [PASSED] drm_gem_shmem_test_purge
[16:45:08] ================== [PASSED] drm_gem_shmem ==================
[16:45:08] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[16:45:08] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[16:45:08] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[16:45:08] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[16:45:08] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[16:45:08] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[16:45:08] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[16:45:08] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[16:45:08] [PASSED] Automatic
[16:45:08] [PASSED] Full
[16:45:08] [PASSED] Limited 16:235
[16:45:08] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[16:45:08] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[16:45:08] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[16:45:08] [PASSED] drm_test_check_disable_connector
[16:45:08] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[16:45:08] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[16:45:08] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[16:45:08] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[16:45:08] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[16:45:08] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[16:45:08] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[16:45:08] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[16:45:08] [PASSED] drm_test_check_output_bpc_dvi
[16:45:08] [PASSED] drm_test_check_output_bpc_format_vic_1
[16:45:08] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[16:45:08] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[16:45:08] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[16:45:08] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[16:45:08] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[16:45:08] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[16:45:08] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[16:45:08] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[16:45:08] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[16:45:08] [PASSED] drm_test_check_broadcast_rgb_value
[16:45:08] [PASSED] drm_test_check_bpc_8_value
[16:45:08] [PASSED] drm_test_check_bpc_10_value
[16:45:08] [PASSED] drm_test_check_bpc_12_value
[16:45:08] [PASSED] drm_test_check_format_value
[16:45:08] [PASSED] drm_test_check_tmds_char_value
[16:45:08] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[16:45:08] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[16:45:08] [PASSED] drm_test_check_mode_valid
[16:45:08] [PASSED] drm_test_check_mode_valid_reject
[16:45:08] [PASSED] drm_test_check_mode_valid_reject_rate
[16:45:08] [PASSED] drm_test_check_mode_valid_reject_max_clock
[16:45:08] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[16:45:08] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[16:45:08] [PASSED] drm_test_check_infoframes
[16:45:08] [PASSED] drm_test_check_reject_avi_infoframe
[16:45:08] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[16:45:08] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[16:45:08] [PASSED] drm_test_check_reject_audio_infoframe
[16:45:08] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[16:45:08] ================= drm_managed (2 subtests) =================
[16:45:08] [PASSED] drm_test_managed_release_action
[16:45:08] [PASSED] drm_test_managed_run_action
[16:45:08] =================== [PASSED] drm_managed ===================
[16:45:08] =================== drm_mm (6 subtests) ====================
[16:45:08] [PASSED] drm_test_mm_init
[16:45:08] [PASSED] drm_test_mm_debug
[16:45:08] [PASSED] drm_test_mm_align32
[16:45:08] [PASSED] drm_test_mm_align64
[16:45:08] [PASSED] drm_test_mm_lowest
[16:45:08] [PASSED] drm_test_mm_highest
[16:45:08] ===================== [PASSED] drm_mm ======================
[16:45:08] ============= drm_modes_analog_tv (5 subtests) =============
[16:45:08] [PASSED] drm_test_modes_analog_tv_mono_576i
[16:45:08] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[16:45:08] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[16:45:08] [PASSED] drm_test_modes_analog_tv_pal_576i
[16:45:08] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[16:45:08] =============== [PASSED] drm_modes_analog_tv ===============
[16:45:08] ============== drm_plane_helper (2 subtests) ===============
[16:45:08] =============== drm_test_check_plane_state  ================
[16:45:08] [PASSED] clipping_simple
[16:45:08] [PASSED] clipping_rotate_reflect
[16:45:08] [PASSED] positioning_simple
[16:45:08] [PASSED] upscaling
[16:45:08] [PASSED] downscaling
[16:45:08] [PASSED] rounding1
[16:45:08] [PASSED] rounding2
[16:45:08] [PASSED] rounding3
[16:45:08] [PASSED] rounding4
[16:45:08] =========== [PASSED] drm_test_check_plane_state ============
[16:45:08] =========== drm_test_check_invalid_plane_state  ============
[16:45:08] [PASSED] positioning_invalid
[16:45:08] [PASSED] upscaling_invalid
[16:45:08] [PASSED] downscaling_invalid
[16:45:08] ======= [PASSED] drm_test_check_invalid_plane_state ========
[16:45:08] ================ [PASSED] drm_plane_helper =================
[16:45:08] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[16:45:08] ====== drm_test_connector_helper_tv_get_modes_check  =======
[16:45:08] [PASSED] None
[16:45:08] [PASSED] PAL
[16:45:08] [PASSED] NTSC
[16:45:08] [PASSED] Both, NTSC Default
[16:45:08] [PASSED] Both, PAL Default
[16:45:08] [PASSED] Both, NTSC Default, with PAL on command-line
[16:45:08] [PASSED] Both, PAL Default, with NTSC on command-line
[16:45:08] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[16:45:08] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[16:45:08] ================== drm_rect (9 subtests) ===================
[16:45:08] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[16:45:08] [PASSED] drm_test_rect_clip_scaled_not_clipped
[16:45:08] [PASSED] drm_test_rect_clip_scaled_clipped
[16:45:08] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[16:45:08] ================= drm_test_rect_intersect  =================
[16:45:08] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[16:45:08] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[16:45:08] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[16:45:08] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[16:45:08] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[16:45:08] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[16:45:08] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[16:45:08] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[16:45:08] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[16:45:08] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[16:45:08] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[16:45:08] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[16:45:08] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[16:45:08] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[16:45:08] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[16:45:08] ============= [PASSED] drm_test_rect_intersect =============
[16:45:08] ================ drm_test_rect_calc_hscale  ================
[16:45:08] [PASSED] normal use
[16:45:08] [PASSED] out of max range
[16:45:08] [PASSED] out of min range
[16:45:08] [PASSED] zero dst
[16:45:08] [PASSED] negative src
[16:45:08] [PASSED] negative dst
[16:45:08] ============ [PASSED] drm_test_rect_calc_hscale ============
[16:45:08] ================ drm_test_rect_calc_vscale  ================
[16:45:08] [PASSED] normal use
[16:45:08] [PASSED] out of max range
[16:45:08] [PASSED] out of min range
[16:45:08] [PASSED] zero dst
[16:45:08] [PASSED] negative src
[16:45:08] [PASSED] negative dst
[16:45:08] ============ [PASSED] drm_test_rect_calc_vscale ============
[16:45:08] ================== drm_test_rect_rotate  ===================
[16:45:08] [PASSED] reflect-x
[16:45:08] [PASSED] reflect-y
[16:45:08] [PASSED] rotate-0
[16:45:08] [PASSED] rotate-90
[16:45:08] [PASSED] rotate-180
[16:45:08] [PASSED] rotate-270
[16:45:08] ============== [PASSED] drm_test_rect_rotate ===============
[16:45:08] ================ drm_test_rect_rotate_inv  =================
[16:45:08] [PASSED] reflect-x
[16:45:08] [PASSED] reflect-y
[16:45:08] [PASSED] rotate-0
[16:45:08] [PASSED] rotate-90
[16:45:08] [PASSED] rotate-180
[16:45:08] [PASSED] rotate-270
[16:45:08] ============ [PASSED] drm_test_rect_rotate_inv =============
[16:45:08] ==================== [PASSED] drm_rect =====================
[16:45:08] ============ drm_sysfb_modeset_test (1 subtest) ============
[16:45:08] ============ drm_test_sysfb_build_fourcc_list  =============
[16:45:08] [PASSED] no native formats
[16:45:08] [PASSED] XRGB8888 as native format
[16:45:08] [PASSED] remove duplicates
[16:45:08] [PASSED] convert alpha formats
[16:45:08] [PASSED] random formats
[16:45:08] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[16:45:08] ============= [PASSED] drm_sysfb_modeset_test ==============
[16:45:08] ================== drm_fixp (2 subtests) ===================
[16:45:08] [PASSED] drm_test_int2fixp
[16:45:08] [PASSED] drm_test_sm2fixp
[16:45:08] ==================== [PASSED] drm_fixp =====================
[16:45:08] ============================================================
[16:45:08] Testing complete. Ran 621 tests: passed: 621
[16:45:08] Elapsed time: 26.213s total, 1.727s configuring, 24.318s building, 0.134s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[16:45:08] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[16:45:10] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[16:45:20] Starting KUnit Kernel (1/1)...
[16:45:20] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[16:45:20] ================= ttm_device (5 subtests) ==================
[16:45:20] [PASSED] ttm_device_init_basic
[16:45:20] [PASSED] ttm_device_init_multiple
[16:45:20] [PASSED] ttm_device_fini_basic
[16:45:20] [PASSED] ttm_device_init_no_vma_man
[16:45:20] ================== ttm_device_init_pools  ==================
[16:45:20] [PASSED] No DMA allocations, no DMA32 required
[16:45:20] [PASSED] DMA allocations, DMA32 required
[16:45:20] [PASSED] No DMA allocations, DMA32 required
[16:45:20] [PASSED] DMA allocations, no DMA32 required
[16:45:20] ============== [PASSED] ttm_device_init_pools ==============
[16:45:20] =================== [PASSED] ttm_device ====================
[16:45:20] ================== ttm_pool (8 subtests) ===================
[16:45:20] ================== ttm_pool_alloc_basic  ===================
[16:45:20] [PASSED] One page
[16:45:20] [PASSED] More than one page
[16:45:20] [PASSED] Above the allocation limit
[16:45:20] [PASSED] One page, with coherent DMA mappings enabled
[16:45:20] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[16:45:20] ============== [PASSED] ttm_pool_alloc_basic ===============
[16:45:20] ============== ttm_pool_alloc_basic_dma_addr  ==============
[16:45:20] [PASSED] One page
[16:45:20] [PASSED] More than one page
[16:45:20] [PASSED] Above the allocation limit
[16:45:20] [PASSED] One page, with coherent DMA mappings enabled
[16:45:20] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[16:45:20] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[16:45:20] [PASSED] ttm_pool_alloc_order_caching_match
[16:45:20] [PASSED] ttm_pool_alloc_caching_mismatch
[16:45:20] [PASSED] ttm_pool_alloc_order_mismatch
[16:45:20] [PASSED] ttm_pool_free_dma_alloc
[16:45:20] [PASSED] ttm_pool_free_no_dma_alloc
[16:45:20] [PASSED] ttm_pool_fini_basic
[16:45:20] ==================== [PASSED] ttm_pool =====================
[16:45:20] ================ ttm_resource (8 subtests) =================
[16:45:20] ================= ttm_resource_init_basic  =================
[16:45:20] [PASSED] Init resource in TTM_PL_SYSTEM
[16:45:20] [PASSED] Init resource in TTM_PL_VRAM
[16:45:20] [PASSED] Init resource in a private placement
[16:45:20] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[16:45:20] ============= [PASSED] ttm_resource_init_basic =============
[16:45:20] [PASSED] ttm_resource_init_pinned
[16:45:20] [PASSED] ttm_resource_fini_basic
[16:45:20] [PASSED] ttm_resource_manager_init_basic
[16:45:20] [PASSED] ttm_resource_manager_usage_basic
[16:45:20] [PASSED] ttm_resource_manager_set_used_basic
[16:45:20] [PASSED] ttm_sys_man_alloc_basic
[16:45:20] [PASSED] ttm_sys_man_free_basic
[16:45:20] ================== [PASSED] ttm_resource ===================
[16:45:20] =================== ttm_tt (15 subtests) ===================
[16:45:20] ==================== ttm_tt_init_basic  ====================
[16:45:20] [PASSED] Page-aligned size
[16:45:20] [PASSED] Extra pages requested
[16:45:20] ================ [PASSED] ttm_tt_init_basic ================
[16:45:20] [PASSED] ttm_tt_init_misaligned
[16:45:20] [PASSED] ttm_tt_fini_basic
[16:45:20] [PASSED] ttm_tt_fini_sg
[16:45:20] [PASSED] ttm_tt_fini_shmem
[16:45:20] [PASSED] ttm_tt_create_basic
[16:45:20] [PASSED] ttm_tt_create_invalid_bo_type
[16:45:20] [PASSED] ttm_tt_create_ttm_exists
[16:45:20] [PASSED] ttm_tt_create_failed
[16:45:20] [PASSED] ttm_tt_destroy_basic
[16:45:20] [PASSED] ttm_tt_populate_null_ttm
[16:45:20] [PASSED] ttm_tt_populate_populated_ttm
[16:45:20] [PASSED] ttm_tt_unpopulate_basic
[16:45:20] [PASSED] ttm_tt_unpopulate_empty_ttm
[16:45:20] [PASSED] ttm_tt_swapin_basic
[16:45:20] ===================== [PASSED] ttm_tt ======================
[16:45:20] =================== ttm_bo (14 subtests) ===================
[16:45:20] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[16:45:20] [PASSED] Cannot be interrupted and sleeps
[16:45:20] [PASSED] Cannot be interrupted, locks straight away
[16:45:20] [PASSED] Can be interrupted, sleeps
[16:45:20] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[16:45:20] [PASSED] ttm_bo_reserve_locked_no_sleep
[16:45:20] [PASSED] ttm_bo_reserve_no_wait_ticket
[16:45:20] [PASSED] ttm_bo_reserve_double_resv
[16:45:20] [PASSED] ttm_bo_reserve_interrupted
[16:45:20] [PASSED] ttm_bo_reserve_deadlock
[16:45:20] [PASSED] ttm_bo_unreserve_basic
[16:45:20] [PASSED] ttm_bo_unreserve_pinned
[16:45:20] [PASSED] ttm_bo_unreserve_bulk
[16:45:20] [PASSED] ttm_bo_fini_basic
[16:45:20] [PASSED] ttm_bo_fini_shared_resv
[16:45:20] [PASSED] ttm_bo_pin_basic
[16:45:20] [PASSED] ttm_bo_pin_unpin_resource
[16:45:20] [PASSED] ttm_bo_multiple_pin_one_unpin
[16:45:20] ===================== [PASSED] ttm_bo ======================
[16:45:20] ============== ttm_bo_validate (22 subtests) ===============
[16:45:20] ============== ttm_bo_init_reserved_sys_man  ===============
[16:45:20] [PASSED] Buffer object for userspace
[16:45:20] [PASSED] Kernel buffer object
[16:45:20] [PASSED] Shared buffer object
[16:45:20] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[16:45:20] ============== ttm_bo_init_reserved_mock_man  ==============
[16:45:20] [PASSED] Buffer object for userspace
[16:45:20] [PASSED] Kernel buffer object
[16:45:20] [PASSED] Shared buffer object
[16:45:20] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[16:45:20] [PASSED] ttm_bo_init_reserved_resv
[16:45:20] ================== ttm_bo_validate_basic  ==================
[16:45:20] [PASSED] Buffer object for userspace
[16:45:20] [PASSED] Kernel buffer object
[16:45:20] [PASSED] Shared buffer object
[16:45:20] ============== [PASSED] ttm_bo_validate_basic ==============
[16:45:20] [PASSED] ttm_bo_validate_invalid_placement
[16:45:20] ============= ttm_bo_validate_same_placement  ==============
[16:45:20] [PASSED] System manager
[16:45:20] [PASSED] VRAM manager
[16:45:20] ========= [PASSED] ttm_bo_validate_same_placement ==========
[16:45:20] [PASSED] ttm_bo_validate_failed_alloc
[16:45:20] [PASSED] ttm_bo_validate_pinned
[16:45:20] [PASSED] ttm_bo_validate_busy_placement
[16:45:20] ================ ttm_bo_validate_multihop  =================
[16:45:20] [PASSED] Buffer object for userspace
[16:45:20] [PASSED] Kernel buffer object
[16:45:20] [PASSED] Shared buffer object
[16:45:20] ============ [PASSED] ttm_bo_validate_multihop =============
[16:45:20] ========== ttm_bo_validate_no_placement_signaled  ==========
[16:45:20] [PASSED] Buffer object in system domain, no page vector
[16:45:20] [PASSED] Buffer object in system domain with an existing page vector
[16:45:20] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[16:45:20] ======== ttm_bo_validate_no_placement_not_signaled  ========
[16:45:20] [PASSED] Buffer object for userspace
[16:45:20] [PASSED] Kernel buffer object
[16:45:20] [PASSED] Shared buffer object
[16:45:20] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[16:45:20] [PASSED] ttm_bo_validate_move_fence_signaled
[16:45:20] ========= ttm_bo_validate_move_fence_not_signaled  =========
[16:45:20] [PASSED] Waits for GPU
[16:45:20] [PASSED] Tries to lock straight away
[16:45:20] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[16:45:20] [PASSED] ttm_bo_validate_swapout
[16:45:20] [PASSED] ttm_bo_validate_happy_evict
[16:45:20] [PASSED] ttm_bo_validate_all_pinned_evict
[16:45:20] [PASSED] ttm_bo_validate_allowed_only_evict
[16:45:20] [PASSED] ttm_bo_validate_deleted_evict
[16:45:20] [PASSED] ttm_bo_validate_busy_domain_evict
[16:45:20] [PASSED] ttm_bo_validate_evict_gutting
[16:45:20] [PASSED] ttm_bo_validate_recrusive_evict
[16:45:20] ================= [PASSED] ttm_bo_validate =================
[16:45:20] ============================================================
[16:45:20] Testing complete. Ran 102 tests: passed: 102
[16:45:20] Elapsed time: 11.664s total, 1.753s configuring, 9.696s building, 0.185s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

Re: [PATCH v5 1/4] drm/xe/rtp: Add struct types for RTP tables

[Gustavo Sousa]

Violet Monti <violet.monti@intel.com> writes:

> From: Gustavo Sousa <gustavo.sousa@intel.com>
>
> We currently have a mixture of styles for our RTP tables with respect of
> how we define the number of entries:
>
>   * xe_rtp_process_to_sr() expects to receive the number of entries as
>     arguments;
>   * xe_rtp_process() expects the array to have a sentinel at the end of
>     the array;
>   * in xe_rtp_test.c, even though xe_rtp_process_to_sr() does not
>     require a sentinel value, we need to rely on that technique to be
>     able to count xe_rtp_entry_sr entries because simply using
>     ARRAY_SIZE() is not possible.
>
> The style used by xe_rtp_process_to_sr() makes it hard to share the
> tables with other compilation units (e.g. kunit tests), since the number
> of entries is calculated with ARRAY_SIZE(), which is done at compile
> time.
>
> Since we use the size of the tables to create some bitmasks, using a
> sentinel style doesn't seem great either.
>
> A way to reconcile things into a single style is to have a struct type
> that would hold the entries array and the number of entries.  Since we
> have xe_rtp_entry and xe_rtp_entry_sr, we would have one type for each.
>
> The advantage of the proposed approach is that now we have a nice way to
> share the tables directly to kunit tests with information about their
> size.
>
> v5:
>     - Remove added code from conflict resolution issues
>
> v4:
>     - Removed conflicts with main branch
>
> v3:
>     - No changes
>
> v2:
>     - Add compatibility with new xe_rtp_table_sr format for
>       "bad-mcr-reg-forced-to-regular" and
>       "bad-regular-reg-forced-to-mcr"
>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Violet Monti <violet.monti@intel.com>

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>

> ---
>  drivers/gpu/drm/xe/tests/xe_rtp_test.c | 101 ++++++++++---------------
>  drivers/gpu/drm/xe/xe_hw_engine.c      |  14 ++--
>  drivers/gpu/drm/xe/xe_reg_whitelist.c  |   7 +-
>  drivers/gpu/drm/xe/xe_rtp.c            |  31 ++++----
>  drivers/gpu/drm/xe/xe_rtp.h            |  16 +++-
>  drivers/gpu/drm/xe/xe_rtp_types.h      |  10 +++
>  drivers/gpu/drm/xe/xe_tuning.c         |  45 +++++------
>  drivers/gpu/drm/xe/xe_wa.c             |  89 ++++++++++++----------
>  8 files changed, 156 insertions(+), 157 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/tests/xe_rtp_test.c b/drivers/gpu/drm/xe/tests/xe_rtp_test.c
> index 642f6e090ad0..16bf85033c0c 100644
> --- a/drivers/gpu/drm/xe/tests/xe_rtp_test.c
> +++ b/drivers/gpu/drm/xe/tests/xe_rtp_test.c
> @@ -54,13 +54,13 @@ struct rtp_to_sr_test_case {
>  	unsigned long expected_count_sr_entries;
>  	unsigned int expected_sr_errors;
>  	unsigned long expected_active;
> -	const struct xe_rtp_entry_sr *entries;
> +	const struct xe_rtp_table_sr table;
>  };
>  
>  struct rtp_test_case {
>  	const char *name;
>  	unsigned long expected_active;
> -	const struct xe_rtp_entry *entries;
> +	const struct xe_rtp_table table;
>  };
>  
>  static bool fake_xe_gt_mcr_check_reg(struct xe_gt *gt, struct xe_reg reg)
> @@ -289,7 +289,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  		.expected_active = BIT(0) | BIT(1),
>  		.expected_count_sr_entries = 1,
>  		/* Different bits on the same register: create a single entry */
> -		.entries = (const struct xe_rtp_entry_sr[]) {
> +		.table = XE_RTP_TABLE_SR(
>  			{ XE_RTP_NAME("basic-1"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
> @@ -298,8 +298,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1)))
>  			},
> -			{}
> -		},
> +		),
>  	},
>  	{
>  		.name = "no-match-no-add",
> @@ -309,7 +308,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  		.expected_active = BIT(0),
>  		.expected_count_sr_entries = 1,
>  		/* Don't coalesce second entry since rules don't match */
> -		.entries = (const struct xe_rtp_entry_sr[]) {
> +		.table = XE_RTP_TABLE_SR(
>  			{ XE_RTP_NAME("basic-1"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
> @@ -318,8 +317,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  			  XE_RTP_RULES(FUNC(match_no)),
>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1)))
>  			},
> -			{}
> -		},
> +		),
>  	},
>  	{
>  		.name = "two-regs-two-entries",
> @@ -329,7 +327,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  		.expected_active = BIT(0) | BIT(1),
>  		.expected_count_sr_entries = 2,
>  		/* Same bits on different registers are not coalesced */
> -		.entries = (const struct xe_rtp_entry_sr[]) {
> +		.table = XE_RTP_TABLE_SR(
>  			{ XE_RTP_NAME("basic-1"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
> @@ -338,8 +336,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(SET(REGULAR_REG2, REG_BIT(0)))
>  			},
> -			{}
> -		},
> +		),
>  	},
>  	{
>  		.name = "clr-one-set-other",
> @@ -349,7 +346,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  		.expected_active = BIT(0) | BIT(1),
>  		.expected_count_sr_entries = 1,
>  		/* Check clr vs set actions on different bits */
> -		.entries = (const struct xe_rtp_entry_sr[]) {
> +		.table = XE_RTP_TABLE_SR(
>  			{ XE_RTP_NAME("basic-1"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
> @@ -358,8 +355,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(CLR(REGULAR_REG1, REG_BIT(1)))
>  			},
> -			{}
> -		},
> +		),
>  	},
>  	{
>  #define TEMP_MASK	REG_GENMASK(10, 8)
> @@ -371,14 +367,13 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  		.expected_active = BIT(0),
>  		.expected_count_sr_entries = 1,
>  		/* Check FIELD_SET works */
> -		.entries = (const struct xe_rtp_entry_sr[]) {
> +		.table = XE_RTP_TABLE_SR(
>  			{ XE_RTP_NAME("basic-1"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(FIELD_SET(REGULAR_REG1,
>  						   TEMP_MASK, TEMP_FIELD))
>  			},
> -			{}
> -		},
> +		),
>  #undef TEMP_MASK
>  #undef TEMP_FIELD
>  	},
> @@ -390,7 +385,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  		.expected_active = BIT(0) | BIT(1),
>  		.expected_count_sr_entries = 1,
>  		.expected_sr_errors = 1,
> -		.entries = (const struct xe_rtp_entry_sr[]) {
> +		.table = XE_RTP_TABLE_SR(
>  			{ XE_RTP_NAME("basic-1"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
> @@ -400,8 +395,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
>  			},
> -			{}
> -		},
> +		),
>  	},
>  	{
>  		.name = "conflict-not-disjoint",
> @@ -411,7 +405,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  		.expected_active = BIT(0) | BIT(1),
>  		.expected_count_sr_entries = 1,
>  		.expected_sr_errors = 1,
> -		.entries = (const struct xe_rtp_entry_sr[]) {
> +		.table = XE_RTP_TABLE_SR(
>  			{ XE_RTP_NAME("basic-1"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
> @@ -421,8 +415,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(CLR(REGULAR_REG1, REG_GENMASK(1, 0)))
>  			},
> -			{}
> -		},
> +		),
>  	},
>  	{
>  		.name = "conflict-reg-type",
> @@ -432,7 +425,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  		.expected_active = BIT(0) | BIT(1) | BIT(2),
>  		.expected_count_sr_entries = 1,
>  		.expected_sr_errors = 2,
> -		.entries = (const struct xe_rtp_entry_sr[]) {
> +		.table = XE_RTP_TABLE_SR(
>  			{ XE_RTP_NAME("basic-1"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
> @@ -447,8 +440,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(SET(MASKED_REG1, REG_BIT(0)))
>  			},
> -			{}
> -		},
> +		),
>  	},
>  	{
>  		.name = "bad-mcr-reg-forced-to-regular",
> @@ -458,13 +450,13 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  		.expected_active = BIT(0),
>  		.expected_count_sr_entries = 1,
>  		.expected_sr_errors = 1,
> -		.entries = (const struct xe_rtp_entry_sr[]) {
> +		.table = XE_RTP_TABLE_SR(
>  			{ XE_RTP_NAME("bad-mcr-regular-reg"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(SET(BAD_MCR_REG4, REG_BIT(0)))
>  			},
>  			{}
> -		},
> +		),
>  	},
>  	{
>  		.name = "bad-regular-reg-forced-to-mcr",
> @@ -474,13 +466,13 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  		.expected_active = BIT(0),
>  		.expected_count_sr_entries = 1,
>  		.expected_sr_errors = 1,
> -		.entries = (const struct xe_rtp_entry_sr[]) {
> +		.table = XE_RTP_TABLE_SR(
>  			{ XE_RTP_NAME("bad-regular-reg"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(SET(BAD_REGULAR_REG5, REG_BIT(0)))
>  			},
>  			{}
> -		},
> +		),
>  	},
>  };
>  
> @@ -492,16 +484,12 @@ static void xe_rtp_process_to_sr_tests(struct kunit *test)
>  	struct xe_reg_sr *reg_sr = &gt->reg_sr;
>  	const struct xe_reg_sr_entry *sre, *sr_entry = NULL;
>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
> -	unsigned long idx, count_sr_entries = 0, count_rtp_entries = 0, active = 0;
> +	unsigned long idx, count_sr_entries = 0, active = 0;
>  
>  	xe_reg_sr_init(reg_sr, "xe_rtp_to_sr_tests", xe);
>  
> -	while (param->entries[count_rtp_entries].rules)
> -		count_rtp_entries++;
> -
> -	xe_rtp_process_ctx_enable_active_tracking(&ctx, &active, count_rtp_entries);
> -	xe_rtp_process_to_sr(&ctx, param->entries, count_rtp_entries,
> -			     reg_sr, false);
> +	xe_rtp_process_ctx_enable_active_tracking(&ctx, &active, param->table.n_entries);
> +	xe_rtp_process_to_sr(&ctx, &param->table, reg_sr, false);
>  
>  	xa_for_each(&reg_sr->xa, idx, sre) {
>  		if (idx == param->expected_reg.addr)
> @@ -534,56 +522,52 @@ static const struct rtp_test_case rtp_cases[] = {
>  	{
>  		.name = "active1",
>  		.expected_active = BIT(0),
> -		.entries = (const struct xe_rtp_entry[]) {
> +		.table = XE_RTP_TABLE(
>  			{ XE_RTP_NAME("r1"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			},
> -			{}
> -		},
> +		),
>  	},
>  	{
>  		.name = "active2",
>  		.expected_active = BIT(0) | BIT(1),
> -		.entries = (const struct xe_rtp_entry[]) {
> +		.table = XE_RTP_TABLE(
>  			{ XE_RTP_NAME("r1"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			},
>  			{ XE_RTP_NAME("r2"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			},
> -			{}
> -		},
> +		),
>  	},
>  	{
>  		.name = "active-inactive",
>  		.expected_active = BIT(0),
> -		.entries = (const struct xe_rtp_entry[]) {
> +		.table = XE_RTP_TABLE(
>  			{ XE_RTP_NAME("r1"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			},
>  			{ XE_RTP_NAME("r2"),
>  			  XE_RTP_RULES(FUNC(match_no)),
>  			},
> -			{}
> -		},
> +		),
>  	},
>  	{
>  		.name = "inactive-active",
>  		.expected_active = BIT(1),
> -		.entries = (const struct xe_rtp_entry[]) {
> +		.table = XE_RTP_TABLE(
>  			{ XE_RTP_NAME("r1"),
>  			  XE_RTP_RULES(FUNC(match_no)),
>  			},
>  			{ XE_RTP_NAME("r2"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			},
> -			{}
> -		},
> +		),
>  	},
>  	{
>  		.name = "inactive-active-inactive",
>  		.expected_active = BIT(1),
> -		.entries = (const struct xe_rtp_entry[]) {
> +		.table = XE_RTP_TABLE(
>  			{ XE_RTP_NAME("r1"),
>  			  XE_RTP_RULES(FUNC(match_no)),
>  			},
> @@ -593,13 +577,12 @@ static const struct rtp_test_case rtp_cases[] = {
>  			{ XE_RTP_NAME("r3"),
>  			  XE_RTP_RULES(FUNC(match_no)),
>  			},
> -			{}
> -		},
> +		),
>  	},
>  	{
>  		.name = "inactive-inactive-inactive",
>  		.expected_active = 0,
> -		.entries = (const struct xe_rtp_entry[]) {
> +		.table = XE_RTP_TABLE(
>  			{ XE_RTP_NAME("r1"),
>  			  XE_RTP_RULES(FUNC(match_no)),
>  			},
> @@ -609,8 +592,7 @@ static const struct rtp_test_case rtp_cases[] = {
>  			{ XE_RTP_NAME("r3"),
>  			  XE_RTP_RULES(FUNC(match_no)),
>  			},
> -			{}
> -		},
> +		),
>  	},
>  };
>  
> @@ -620,13 +602,10 @@ static void xe_rtp_process_tests(struct kunit *test)
>  	struct xe_device *xe = test->priv;
>  	struct xe_gt *gt = xe_device_get_root_tile(xe)->primary_gt;
>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
> -	unsigned long count_rtp_entries = 0, active = 0;
> -
> -	while (param->entries[count_rtp_entries].rules)
> -		count_rtp_entries++;
> +	unsigned long active = 0;
>  
> -	xe_rtp_process_ctx_enable_active_tracking(&ctx, &active, count_rtp_entries);
> -	xe_rtp_process(&ctx, param->entries);
> +	xe_rtp_process_ctx_enable_active_tracking(&ctx, &active, param->table.n_entries);
> +	xe_rtp_process(&ctx, &param->table);
>  
>  	KUNIT_EXPECT_EQ(test, active, param->expected_active);
>  }
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index 8c66ff6f3d3c..98265293f2dc 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -346,7 +346,7 @@ hw_engine_setup_default_lrc_state(struct xe_hw_engine *hwe)
>  	u32 blit_cctl_val = REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, mocs_write_idx) |
>  			    REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, mocs_read_idx);
>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
> -	const struct xe_rtp_entry_sr lrc_setup[] = {
> +	const struct xe_rtp_table_sr lrc_setup = XE_RTP_TABLE_SR(
>  		/*
>  		 * Some blitter commands do not have a field for MOCS, those
>  		 * commands will use MOCS index pointed by BLIT_CCTL.
> @@ -369,10 +369,9 @@ hw_engine_setup_default_lrc_state(struct xe_hw_engine *hwe)
>  					   PREEMPT_GPGPU_THREAD_GROUP_LEVEL)),
>  		  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE)
>  		},
> -	};
> +	);
>  
> -	xe_rtp_process_to_sr(&ctx, lrc_setup, ARRAY_SIZE(lrc_setup),
> -			     &hwe->reg_lrc, true);
> +	xe_rtp_process_to_sr(&ctx, &lrc_setup, &hwe->reg_lrc, true);
>  }
>  
>  void xe_hw_engine_setup_reg_lrc(struct xe_hw_engine *hwe)
> @@ -408,7 +407,7 @@ hw_engine_setup_default_state(struct xe_hw_engine *hwe)
>  	u32 ring_cmd_cctl_val = REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, mocs_write_idx) |
>  				REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, mocs_read_idx);
>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
> -	const struct xe_rtp_entry_sr engine_entries[] = {
> +	const struct xe_rtp_table_sr engine_sr = XE_RTP_TABLE_SR(
>  		{ XE_RTP_NAME("RING_CMD_CCTL_default_MOCS"),
>  		  XE_RTP_RULES(FUNC(xe_rtp_match_always)),
>  		  XE_RTP_ACTIONS(FIELD_SET(RING_CMD_CCTL(0),
> @@ -465,10 +464,9 @@ hw_engine_setup_default_state(struct xe_hw_engine *hwe)
>  		  XE_RTP_ACTIONS(SET(GFX_MODE(0), GFX_MSIX_INTERRUPT_ENABLE,
>  				     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
>  		},
> -	};
> +	);
>  
> -	xe_rtp_process_to_sr(&ctx, engine_entries, ARRAY_SIZE(engine_entries),
> -			     &hwe->reg_sr, false);
> +	xe_rtp_process_to_sr(&ctx, &engine_sr, &hwe->reg_sr, false);
>  }
>  
>  static const struct engine_info *find_engine_info(enum xe_engine_class class, int instance)
> diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> index fb65940848d7..2e84b1c49f37 100644
> --- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
> +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> @@ -41,7 +41,7 @@ static bool match_multi_queue_class(const struct xe_device *xe,
>  	return xe_gt_supports_multi_queue(gt, hwe->class);
>  }
>  
> -static const struct xe_rtp_entry_sr register_whitelist[] = {
> +static const struct xe_rtp_table_sr register_whitelist = XE_RTP_TABLE_SR(
>  	{ XE_RTP_NAME("WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865"),
>  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
>  	  XE_RTP_ACTIONS(WHITELIST(PS_INVOCATION_COUNT,
> @@ -154,7 +154,7 @@ static const struct xe_rtp_entry_sr register_whitelist[] = {
>  	  XE_RTP_RULES(FUNC(match_has_mert), ENGINE_CLASS(COPY)),
>  	  XE_RTP_ACTIONS(WHITELIST_OA_MERT_MMIO_TRG)
>  	},
> -};
> +);
>  
>  static void whitelist_apply_to_hwe(struct xe_hw_engine *hwe)
>  {
> @@ -202,8 +202,7 @@ void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe)
>  {
>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
>  
> -	xe_rtp_process_to_sr(&ctx, register_whitelist, ARRAY_SIZE(register_whitelist),
> -			     &hwe->reg_whitelist, false);
> +	xe_rtp_process_to_sr(&ctx, &register_whitelist, &hwe->reg_whitelist, false);
>  	whitelist_apply_to_hwe(hwe);
>  }
>  
> diff --git a/drivers/gpu/drm/xe/xe_rtp.c b/drivers/gpu/drm/xe/xe_rtp.c
> index dec9d94e6fb0..83a40e1f9528 100644
> --- a/drivers/gpu/drm/xe/xe_rtp.c
> +++ b/drivers/gpu/drm/xe/xe_rtp.c
> @@ -326,8 +326,7 @@ static void rtp_mark_active(struct xe_device *xe,
>   * xe_rtp_process_to_sr - Process all rtp @entries, adding the matching ones to
>   *                        the save-restore argument.
>   * @ctx: The context for processing the table, with one of device, gt or hwe
> - * @entries: Table with RTP definitions
> - * @n_entries: Number of entries to process, usually ARRAY_SIZE(entries)
> + * @table: Table with RTP definitions
>   * @sr: Save-restore struct where matching rules execute the action. This can be
>   *      viewed as the "coalesced view" of multiple the tables. The bits for each
>   *      register set are expected not to collide with previously added entries
> @@ -339,12 +338,10 @@ static void rtp_mark_active(struct xe_device *xe,
>   * used to calculate the right register offset
>   */
>  void xe_rtp_process_to_sr(struct xe_rtp_process_ctx *ctx,
> -			  const struct xe_rtp_entry_sr *entries,
> -			  size_t n_entries,
> +			  const struct xe_rtp_table_sr *table,
>  			  struct xe_reg_sr *sr,
>  			  bool process_in_vf)
>  {
> -	const struct xe_rtp_entry_sr *entry;
>  	struct xe_hw_engine *hwe = NULL;
>  	struct xe_gt *gt = NULL;
>  	struct xe_device *xe = NULL;
> @@ -354,9 +351,10 @@ void xe_rtp_process_to_sr(struct xe_rtp_process_ctx *ctx,
>  	if (!process_in_vf && IS_SRIOV_VF(xe))
>  		return;
>  
> -	xe_assert(xe, entries);
> +	xe_assert(xe, table->entries);
>  
> -	for (entry = entries; entry - entries < n_entries; entry++) {
> +	for (size_t i = 0; i < table->n_entries; i++) {
> +		const struct xe_rtp_entry_sr *entry = &table->entries[i];
>  		bool match = false;
>  
>  		if (entry->flags & XE_RTP_ENTRY_FLAG_FOREACH_ENGINE) {
> @@ -371,37 +369,40 @@ void xe_rtp_process_to_sr(struct xe_rtp_process_ctx *ctx,
>  		}
>  
>  		if (match)
> -			rtp_mark_active(xe, ctx, entry - entries);
> +			rtp_mark_active(xe, ctx, i);
>  	}
>  }
>  EXPORT_SYMBOL_IF_KUNIT(xe_rtp_process_to_sr);
>  
>  /**
> - * xe_rtp_process - Process all rtp @entries, without running any action
> + * xe_rtp_process - Process all entries in rtp @table, without running any action
>   * @ctx: The context for processing the table, with one of device, gt or hwe
> - * @entries: Table with RTP definitions
> + * @table: Table with RTP definitions
>   *
> - * Walk the table pointed by @entries (with an empty sentinel), executing the
> + * Walk the table pointed by @table, executing the
>   * rules. One difference from xe_rtp_process_to_sr(): there is no action
>   * associated with each entry since this uses struct xe_rtp_entry. Its main use
>   * is for marking active workarounds via
>   * xe_rtp_process_ctx_enable_active_tracking().
>   */
>  void xe_rtp_process(struct xe_rtp_process_ctx *ctx,
> -		    const struct xe_rtp_entry *entries)
> +		    const struct xe_rtp_table *table)
>  {
> -	const struct xe_rtp_entry *entry;
>  	struct xe_hw_engine *hwe;
>  	struct xe_gt *gt;
>  	struct xe_device *xe;
>  
>  	rtp_get_context(ctx, &hwe, &gt, &xe);
>  
> -	for (entry = entries; entry && entry->rules; entry++) {
> +	xe_assert(xe, table->entries);
> +
> +	for (size_t i = 0; i < table->n_entries; i++) {
> +		const struct xe_rtp_entry *entry = &table->entries[i];
> +
>  		if (!rule_matches(xe, gt, hwe, entry->rules, entry->n_rules))
>  			continue;
>  
> -		rtp_mark_active(xe, ctx, entry - entries);
> +		rtp_mark_active(xe, ctx, i);
>  	}
>  }
>  EXPORT_SYMBOL_IF_KUNIT(xe_rtp_process);
> diff --git a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h
> index e4f1930ca1c3..4e3cfd69f922 100644
> --- a/drivers/gpu/drm/xe/xe_rtp.h
> +++ b/drivers/gpu/drm/xe/xe_rtp.h
> @@ -461,6 +461,16 @@ struct xe_reg_sr;
>  		XE_RTP_PASTE_FOREACH(ACTION_, COMMA, (__VA_ARGS__))	\
>  	}
>  
> +#define XE_RTP_TABLE_SR(...) { \
> +	.entries = (const struct xe_rtp_entry_sr[]){__VA_ARGS__}, \
> +	.n_entries = ARRAY_SIZE(((const struct xe_rtp_entry_sr[]){__VA_ARGS__})), \
> +}
> +
> +#define XE_RTP_TABLE(...) { \
> +	.entries = (const struct xe_rtp_entry[]){__VA_ARGS__}, \
> +	.n_entries = ARRAY_SIZE(((const struct xe_rtp_entry[]){__VA_ARGS__})), \
> +}
> +
>  #define XE_RTP_PROCESS_CTX_INITIALIZER(arg__) _Generic((arg__),							\
>  	struct xe_hw_engine * :	(struct xe_rtp_process_ctx){ { (void *)(arg__) }, XE_RTP_PROCESS_TYPE_ENGINE },	\
>  	struct xe_gt * :	(struct xe_rtp_process_ctx){ { (void *)(arg__) }, XE_RTP_PROCESS_TYPE_GT },	\
> @@ -471,12 +481,12 @@ void xe_rtp_process_ctx_enable_active_tracking(struct xe_rtp_process_ctx *ctx,
>  					       size_t n_entries);
>  
>  void xe_rtp_process_to_sr(struct xe_rtp_process_ctx *ctx,
> -			  const struct xe_rtp_entry_sr *entries,
> -			  size_t n_entries, struct xe_reg_sr *sr,
> +			  const struct xe_rtp_table_sr *table,
> +			  struct xe_reg_sr *sr,
>  			  bool process_in_vf);
>  
>  void xe_rtp_process(struct xe_rtp_process_ctx *ctx,
> -		    const struct xe_rtp_entry *entries);
> +		    const struct xe_rtp_table *table);
>  
>  /* Match functions to be used with XE_RTP_MATCH_FUNC */
>  
> diff --git a/drivers/gpu/drm/xe/xe_rtp_types.h b/drivers/gpu/drm/xe/xe_rtp_types.h
> index 0265c16d2762..58018ae4f8cc 100644
> --- a/drivers/gpu/drm/xe/xe_rtp_types.h
> +++ b/drivers/gpu/drm/xe/xe_rtp_types.h
> @@ -112,6 +112,16 @@ struct xe_rtp_entry {
>  	u8 n_rules;
>  };
>  
> +struct xe_rtp_table_sr {
> +	const struct xe_rtp_entry_sr *entries;
> +	size_t n_entries;
> +};
> +
> +struct xe_rtp_table {
> +	const struct xe_rtp_entry *entries;
> +	size_t n_entries;
> +};
> +
>  enum xe_rtp_process_type {
>  	XE_RTP_PROCESS_TYPE_DEVICE,
>  	XE_RTP_PROCESS_TYPE_GT,
> diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
> index 9a1b3862e192..bf3fad9cdbef 100644
> --- a/drivers/gpu/drm/xe/xe_tuning.c
> +++ b/drivers/gpu/drm/xe/xe_tuning.c
> @@ -20,7 +20,7 @@
>  #undef XE_REG_MCR
>  #define XE_REG_MCR(...)     XE_REG(__VA_ARGS__, .mcr = 1)
>  
> -static const struct xe_rtp_entry_sr gt_tunings[] = {
> +static const struct xe_rtp_table_sr gt_tunings = XE_RTP_TABLE_SR(
>  	{ XE_RTP_NAME("Tuning: Blend Fill Caching Optimization Disable"),
>  	  XE_RTP_RULES(PLATFORM(DG2)),
>  	  XE_RTP_ACTIONS(SET(XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS))
> @@ -100,9 +100,9 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
>  	  XE_RTP_ACTIONS(FIELD_SET(GAMSTLB_CTRL, BANK_HASH_MODE,
>  				   BANK_HASH_4KB_MODE))
>  	},
> -};
> +);
>  
> -static const struct xe_rtp_entry_sr engine_tunings[] = {
> +static const struct xe_rtp_table_sr engine_tunings = XE_RTP_TABLE_SR(
>  	{ XE_RTP_NAME("Tuning: L3 Hashing Mask"),
>  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210),
>  		       FUNC(xe_rtp_match_first_render_or_compute)),
> @@ -129,9 +129,9 @@ static const struct xe_rtp_entry_sr engine_tunings[] = {
>  		       FUNC(xe_rtp_match_first_render_or_compute)),
>  	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN2, TILEY_LOCALID))
>  	},
> -};
> +);
>  
> -static const struct xe_rtp_entry_sr lrc_tunings[] = {
> +static const struct xe_rtp_table_sr lrc_tunings = XE_RTP_TABLE_SR(
>  	{ XE_RTP_NAME("Tuning: Windower HW Filtering"),
>  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3599), ENGINE_CLASS(RENDER)),
>  	  XE_RTP_ACTIONS(SET(XEHP_COMMON_SLICE_CHICKEN4, HW_FILTERING))
> @@ -171,7 +171,7 @@ static const struct xe_rtp_entry_sr lrc_tunings[] = {
>  	  XE_RTP_ACTIONS(FIELD_SET(FF_MODE, VS_HIT_MAX_VALUE_MASK,
>  				   REG_FIELD_PREP(VS_HIT_MAX_VALUE_MASK, 0x3f)))
>  	},
> -};
> +);
>  
>  /**
>   * xe_tuning_init - initialize gt with tunings bookkeeping
> @@ -185,9 +185,9 @@ int xe_tuning_init(struct xe_gt *gt)
>  	size_t n_lrc, n_engine, n_gt, total;
>  	unsigned long *p;
>  
> -	n_gt = BITS_TO_LONGS(ARRAY_SIZE(gt_tunings));
> -	n_engine = BITS_TO_LONGS(ARRAY_SIZE(engine_tunings));
> -	n_lrc = BITS_TO_LONGS(ARRAY_SIZE(lrc_tunings));
> +	n_gt = BITS_TO_LONGS(gt_tunings.n_entries);
> +	n_engine = BITS_TO_LONGS(engine_tunings.n_entries);
> +	n_lrc = BITS_TO_LONGS(lrc_tunings.n_entries);
>  	total = n_gt + n_engine + n_lrc;
>  
>  	p = drmm_kzalloc(&xe->drm, sizeof(*p) * total, GFP_KERNEL);
> @@ -210,9 +210,8 @@ void xe_tuning_process_gt(struct xe_gt *gt)
>  
>  	xe_rtp_process_ctx_enable_active_tracking(&ctx,
>  						  gt->tuning_active.gt,
> -						  ARRAY_SIZE(gt_tunings));
> -	xe_rtp_process_to_sr(&ctx, gt_tunings, ARRAY_SIZE(gt_tunings),
> -			     &gt->reg_sr, false);
> +						  gt_tunings.n_entries);
> +	xe_rtp_process_to_sr(&ctx, &gt_tunings, &gt->reg_sr, false);
>  }
>  EXPORT_SYMBOL_IF_KUNIT(xe_tuning_process_gt);
>  
> @@ -222,9 +221,8 @@ void xe_tuning_process_engine(struct xe_hw_engine *hwe)
>  
>  	xe_rtp_process_ctx_enable_active_tracking(&ctx,
>  						  hwe->gt->tuning_active.engine,
> -						  ARRAY_SIZE(engine_tunings));
> -	xe_rtp_process_to_sr(&ctx, engine_tunings, ARRAY_SIZE(engine_tunings),
> -			     &hwe->reg_sr, false);
> +						  engine_tunings.n_entries);
> +	xe_rtp_process_to_sr(&ctx, &engine_tunings, &hwe->reg_sr, false);
>  }
>  EXPORT_SYMBOL_IF_KUNIT(xe_tuning_process_engine);
>  
> @@ -242,9 +240,8 @@ void xe_tuning_process_lrc(struct xe_hw_engine *hwe)
>  
>  	xe_rtp_process_ctx_enable_active_tracking(&ctx,
>  						  hwe->gt->tuning_active.lrc,
> -						  ARRAY_SIZE(lrc_tunings));
> -	xe_rtp_process_to_sr(&ctx, lrc_tunings, ARRAY_SIZE(lrc_tunings),
> -			     &hwe->reg_lrc, true);
> +						  lrc_tunings.n_entries);
> +	xe_rtp_process_to_sr(&ctx, &lrc_tunings, &hwe->reg_lrc, true);
>  }
>  
>  /**
> @@ -259,18 +256,18 @@ int xe_tuning_dump(struct xe_gt *gt, struct drm_printer *p)
>  	size_t idx;
>  
>  	drm_printf(p, "GT Tunings\n");
> -	for_each_set_bit(idx, gt->tuning_active.gt, ARRAY_SIZE(gt_tunings))
> -		drm_printf_indent(p, 1, "%s\n", gt_tunings[idx].name);
> +	for_each_set_bit(idx, gt->tuning_active.gt, gt_tunings.n_entries)
> +		drm_printf_indent(p, 1, "%s\n", gt_tunings.entries[idx].name);
>  
>  	drm_puts(p, "\n");
>  	drm_printf(p, "Engine Tunings\n");
> -	for_each_set_bit(idx, gt->tuning_active.engine, ARRAY_SIZE(engine_tunings))
> -		drm_printf_indent(p, 1, "%s\n", engine_tunings[idx].name);
> +	for_each_set_bit(idx, gt->tuning_active.engine, engine_tunings.n_entries)
> +		drm_printf_indent(p, 1, "%s\n", engine_tunings.entries[idx].name);
>  
>  	drm_puts(p, "\n");
>  	drm_printf(p, "LRC Tunings\n");
> -	for_each_set_bit(idx, gt->tuning_active.lrc, ARRAY_SIZE(lrc_tunings))
> -		drm_printf_indent(p, 1, "%s\n", lrc_tunings[idx].name);
> +	for_each_set_bit(idx, gt->tuning_active.lrc, lrc_tunings.n_entries)
> +		drm_printf_indent(p, 1, "%s\n", lrc_tunings.entries[idx].name);
>  
>  	return 0;
>  }
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index cb811f8a7781..b9d9fe0801aa 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -130,7 +130,7 @@
>  __diag_push();
>  __diag_ignore_all("-Woverride-init", "Allow field overrides in table");
>  
> -static const struct xe_rtp_entry_sr gt_was[] = {
> +static const struct xe_rtp_table_sr gt_was = XE_RTP_TABLE_SR(
>  	/* Workarounds applying over a range of IPs */
>  
>  	{ XE_RTP_NAME("14011060649"),
> @@ -306,9 +306,9 @@ static const struct xe_rtp_entry_sr gt_was[] = {
>  	  XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
>  	  XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
>  	},
> -};
> +);
>  
> -static const struct xe_rtp_entry_sr engine_was[] = {
> +static const struct xe_rtp_table_sr engine_was = XE_RTP_TABLE_SR(
>  	/* Workarounds applying over a range of IPs */
>  
>  	{ XE_RTP_NAME("22010931296, 18011464164, 14010919138"),
> @@ -614,9 +614,9 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  		       FUNC(xe_rtp_match_first_render_or_compute)),
>  	  XE_RTP_ACTIONS(SET(TDL_CHICKEN, BIT_APQ_OPT_DIS))
>  	},
> -};
> +);
>  
> -static const struct xe_rtp_entry_sr lrc_was[] = {
> +static const struct xe_rtp_table_sr lrc_was = XE_RTP_TABLE_SR(
>  	{ XE_RTP_NAME("16011163337"),
>  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
>  	  /* read verification is ignored due to 1608008084. */
> @@ -794,21 +794,29 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
>  		       ENGINE_CLASS(RENDER)),
>  	  XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX))
>  	},
> -};
> +);
>  
> -static __maybe_unused const struct xe_rtp_entry oob_was[] = {
> +static const struct xe_rtp_entry oob_was_entries[] = {
>  #include <generated/xe_wa_oob.c>
> -	{}
>  };
>  
> -static_assert(ARRAY_SIZE(oob_was) - 1 == _XE_WA_OOB_COUNT);
> +static_assert(ARRAY_SIZE(oob_was_entries)  == _XE_WA_OOB_COUNT);
>  
> -static __maybe_unused const struct xe_rtp_entry device_oob_was[] = {
> +static __maybe_unused const struct xe_rtp_table oob_was = {
> +	.entries = oob_was_entries,
> +	.n_entries = ARRAY_SIZE(oob_was_entries),
> +};
> +
> +static const struct xe_rtp_entry device_oob_was_entries[] = {
>  #include <generated/xe_device_wa_oob.c>
> -	{}
>  };
>  
> -static_assert(ARRAY_SIZE(device_oob_was) - 1 == _XE_DEVICE_WA_OOB_COUNT);
> +static_assert(ARRAY_SIZE(device_oob_was_entries) == _XE_DEVICE_WA_OOB_COUNT);
> +
> +static __maybe_unused const struct xe_rtp_table device_oob_was = {
> +	.entries = device_oob_was_entries,
> +	.n_entries = ARRAY_SIZE(device_oob_was_entries),
> +};
>  
>  __diag_pop();
>  
> @@ -824,10 +832,10 @@ void xe_wa_process_device_oob(struct xe_device *xe)
>  {
>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(xe);
>  
> -	xe_rtp_process_ctx_enable_active_tracking(&ctx, xe->wa_active.oob, ARRAY_SIZE(device_oob_was));
> +	xe_rtp_process_ctx_enable_active_tracking(&ctx, xe->wa_active.oob, device_oob_was.n_entries);
>  
>  	xe->wa_active.oob_initialized = true;
> -	xe_rtp_process(&ctx, device_oob_was);
> +	xe_rtp_process(&ctx, &device_oob_was);
>  }
>  
>  /**
> @@ -842,9 +850,9 @@ void xe_wa_process_gt_oob(struct xe_gt *gt)
>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
>  
>  	xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.oob,
> -						  ARRAY_SIZE(oob_was));
> +						  oob_was.n_entries);
>  	gt->wa_active.oob_initialized = true;
> -	xe_rtp_process(&ctx, oob_was);
> +	xe_rtp_process(&ctx, &oob_was);
>  }
>  
>  /**
> @@ -859,9 +867,8 @@ void xe_wa_process_gt(struct xe_gt *gt)
>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
>  
>  	xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.gt,
> -						  ARRAY_SIZE(gt_was));
> -	xe_rtp_process_to_sr(&ctx, gt_was, ARRAY_SIZE(gt_was),
> -			     &gt->reg_sr, false);
> +						  gt_was.n_entries);
> +	xe_rtp_process_to_sr(&ctx, &gt_was, &gt->reg_sr, false);
>  }
>  EXPORT_SYMBOL_IF_KUNIT(xe_wa_process_gt);
>  
> @@ -878,9 +885,8 @@ void xe_wa_process_engine(struct xe_hw_engine *hwe)
>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
>  
>  	xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.engine,
> -						  ARRAY_SIZE(engine_was));
> -	xe_rtp_process_to_sr(&ctx, engine_was, ARRAY_SIZE(engine_was),
> -			     &hwe->reg_sr, false);
> +						  engine_was.n_entries);
> +	xe_rtp_process_to_sr(&ctx, &engine_was, &hwe->reg_sr, false);
>  }
>  
>  /**
> @@ -896,9 +902,8 @@ void xe_wa_process_lrc(struct xe_hw_engine *hwe)
>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
>  
>  	xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.lrc,
> -						  ARRAY_SIZE(lrc_was));
> -	xe_rtp_process_to_sr(&ctx, lrc_was, ARRAY_SIZE(lrc_was),
> -			     &hwe->reg_lrc, true);
> +						  lrc_was.n_entries);
> +	xe_rtp_process_to_sr(&ctx, &lrc_was, &hwe->reg_lrc, true);
>  }
>  
>  /**
> @@ -912,7 +917,7 @@ int xe_wa_device_init(struct xe_device *xe)
>  	unsigned long *p;
>  
>  	p = drmm_kzalloc(&xe->drm,
> -			 sizeof(*p) * BITS_TO_LONGS(ARRAY_SIZE(device_oob_was)),
> +			 sizeof(*p) * BITS_TO_LONGS(device_oob_was.n_entries),
>  			 GFP_KERNEL);
>  
>  	if (!p)
> @@ -935,10 +940,10 @@ int xe_wa_gt_init(struct xe_gt *gt)
>  	size_t n_oob, n_lrc, n_engine, n_gt, total;
>  	unsigned long *p;
>  
> -	n_gt = BITS_TO_LONGS(ARRAY_SIZE(gt_was));
> -	n_engine = BITS_TO_LONGS(ARRAY_SIZE(engine_was));
> -	n_lrc = BITS_TO_LONGS(ARRAY_SIZE(lrc_was));
> -	n_oob = BITS_TO_LONGS(ARRAY_SIZE(oob_was));
> +	n_gt = BITS_TO_LONGS(gt_was.n_entries);
> +	n_engine = BITS_TO_LONGS(engine_was.n_entries);
> +	n_lrc = BITS_TO_LONGS(lrc_was.n_entries);
> +	n_oob = BITS_TO_LONGS(oob_was.n_entries);
>  	total = n_gt + n_engine + n_lrc + n_oob;
>  
>  	p = drmm_kzalloc(&xe->drm, sizeof(*p) * total, GFP_KERNEL);
> @@ -962,9 +967,9 @@ void xe_wa_device_dump(struct xe_device *xe, struct drm_printer *p)
>  	size_t idx;
>  
>  	drm_printf(p, "Device OOB Workarounds\n");
> -	for_each_set_bit(idx, xe->wa_active.oob, ARRAY_SIZE(device_oob_was))
> -		if (device_oob_was[idx].name)
> -			drm_printf_indent(p, 1, "%s\n", device_oob_was[idx].name);
> +	for_each_set_bit(idx, xe->wa_active.oob, device_oob_was.n_entries)
> +		if (device_oob_was.entries[idx].name)
> +			drm_printf_indent(p, 1, "%s\n", device_oob_was.entries[idx].name);
>  }
>  
>  /**
> @@ -979,24 +984,24 @@ int xe_wa_gt_dump(struct xe_gt *gt, struct drm_printer *p)
>  	size_t idx;
>  
>  	drm_printf(p, "GT Workarounds\n");
> -	for_each_set_bit(idx, gt->wa_active.gt, ARRAY_SIZE(gt_was))
> -		drm_printf_indent(p, 1, "%s\n", gt_was[idx].name);
> +	for_each_set_bit(idx, gt->wa_active.gt, gt_was.n_entries)
> +		drm_printf_indent(p, 1, "%s\n", gt_was.entries[idx].name);
>  
>  	drm_puts(p, "\n");
>  	drm_printf(p, "Engine Workarounds\n");
> -	for_each_set_bit(idx, gt->wa_active.engine, ARRAY_SIZE(engine_was))
> -		drm_printf_indent(p, 1, "%s\n", engine_was[idx].name);
> +	for_each_set_bit(idx, gt->wa_active.engine, engine_was.n_entries)
> +		drm_printf_indent(p, 1, "%s\n", engine_was.entries[idx].name);
>  
>  	drm_puts(p, "\n");
>  	drm_printf(p, "LRC Workarounds\n");
> -	for_each_set_bit(idx, gt->wa_active.lrc, ARRAY_SIZE(lrc_was))
> -		drm_printf_indent(p, 1, "%s\n", lrc_was[idx].name);
> +	for_each_set_bit(idx, gt->wa_active.lrc, lrc_was.n_entries)
> +		drm_printf_indent(p, 1, "%s\n", lrc_was.entries[idx].name);
>  
>  	drm_puts(p, "\n");
>  	drm_printf(p, "OOB Workarounds\n");
> -	for_each_set_bit(idx, gt->wa_active.oob, ARRAY_SIZE(oob_was))
> -		if (oob_was[idx].name)
> -			drm_printf_indent(p, 1, "%s\n", oob_was[idx].name);
> +	for_each_set_bit(idx, gt->wa_active.oob, oob_was.n_entries)
> +		if (oob_was.entries[idx].name)
> +			drm_printf_indent(p, 1, "%s\n", oob_was.entries[idx].name);
>  	return 0;
>  }
>  
> -- 
> 2.43.0

✓ Xe.CI.BAT: success for drm/xe/rtp: WA table context testing

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1088 bytes --]

== Series Details ==

Series: drm/xe/rtp: WA table context testing
URL   : https://patchwork.freedesktop.org/series/167474/
State : success

== Summary ==

CI Bug Log - changes from xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b_BAT -> xe-pw-167474v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 13)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * IGT: IGT_8940 -> IGT_8941
  * Linux: xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b -> xe-pw-167474v1

  IGT_8940: 656294e257ae4a63e41dbd9d4c11c17ad2543210 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  IGT_8941: 0e365bfe5ccc6d1f7607db10bc21c72d30292cea @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b: ad585773b42ab96a2706dc82478e2021fec1a53b
  xe-pw-167474v1: 167474v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/index.html

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Re: [PATCH v5 1/4] drm/xe/rtp: Add struct types for RTP tables

[Gustavo Sousa]

Gustavo Sousa <gustavo.sousa@intel.com> writes:

> Violet Monti <violet.monti@intel.com> writes:
>
>> From: Gustavo Sousa <gustavo.sousa@intel.com>
>>
>> We currently have a mixture of styles for our RTP tables with respect of
>> how we define the number of entries:
>>
>>   * xe_rtp_process_to_sr() expects to receive the number of entries as
>>     arguments;
>>   * xe_rtp_process() expects the array to have a sentinel at the end of
>>     the array;
>>   * in xe_rtp_test.c, even though xe_rtp_process_to_sr() does not
>>     require a sentinel value, we need to rely on that technique to be
>>     able to count xe_rtp_entry_sr entries because simply using
>>     ARRAY_SIZE() is not possible.
>>
>> The style used by xe_rtp_process_to_sr() makes it hard to share the
>> tables with other compilation units (e.g. kunit tests), since the number
>> of entries is calculated with ARRAY_SIZE(), which is done at compile
>> time.
>>
>> Since we use the size of the tables to create some bitmasks, using a
>> sentinel style doesn't seem great either.
>>
>> A way to reconcile things into a single style is to have a struct type
>> that would hold the entries array and the number of entries.  Since we
>> have xe_rtp_entry and xe_rtp_entry_sr, we would have one type for each.
>>
>> The advantage of the proposed approach is that now we have a nice way to
>> share the tables directly to kunit tests with information about their
>> size.
>>
>> v5:
>>     - Remove added code from conflict resolution issues
>>
>> v4:
>>     - Removed conflicts with main branch
>>
>> v3:
>>     - No changes
>>
>> v2:
>>     - Add compatibility with new xe_rtp_table_sr format for
>>       "bad-mcr-reg-forced-to-regular" and
>>       "bad-regular-reg-forced-to-mcr"
>>
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> Signed-off-by: Violet Monti <violet.monti@intel.com>
>
> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>

Oops... Please dismiss this. The r-b was meant for patch #2. Sorry for
the noise.

--
Gustavo Sousa

>
>> ---
>>  drivers/gpu/drm/xe/tests/xe_rtp_test.c | 101 ++++++++++---------------
>>  drivers/gpu/drm/xe/xe_hw_engine.c      |  14 ++--
>>  drivers/gpu/drm/xe/xe_reg_whitelist.c  |   7 +-
>>  drivers/gpu/drm/xe/xe_rtp.c            |  31 ++++----
>>  drivers/gpu/drm/xe/xe_rtp.h            |  16 +++-
>>  drivers/gpu/drm/xe/xe_rtp_types.h      |  10 +++
>>  drivers/gpu/drm/xe/xe_tuning.c         |  45 +++++------
>>  drivers/gpu/drm/xe/xe_wa.c             |  89 ++++++++++++----------
>>  8 files changed, 156 insertions(+), 157 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/tests/xe_rtp_test.c b/drivers/gpu/drm/xe/tests/xe_rtp_test.c
>> index 642f6e090ad0..16bf85033c0c 100644
>> --- a/drivers/gpu/drm/xe/tests/xe_rtp_test.c
>> +++ b/drivers/gpu/drm/xe/tests/xe_rtp_test.c
>> @@ -54,13 +54,13 @@ struct rtp_to_sr_test_case {
>>  	unsigned long expected_count_sr_entries;
>>  	unsigned int expected_sr_errors;
>>  	unsigned long expected_active;
>> -	const struct xe_rtp_entry_sr *entries;
>> +	const struct xe_rtp_table_sr table;
>>  };
>>  
>>  struct rtp_test_case {
>>  	const char *name;
>>  	unsigned long expected_active;
>> -	const struct xe_rtp_entry *entries;
>> +	const struct xe_rtp_table table;
>>  };
>>  
>>  static bool fake_xe_gt_mcr_check_reg(struct xe_gt *gt, struct xe_reg reg)
>> @@ -289,7 +289,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>>  		.expected_active = BIT(0) | BIT(1),
>>  		.expected_count_sr_entries = 1,
>>  		/* Different bits on the same register: create a single entry */
>> -		.entries = (const struct xe_rtp_entry_sr[]) {
>> +		.table = XE_RTP_TABLE_SR(
>>  			{ XE_RTP_NAME("basic-1"),
>>  			  XE_RTP_RULES(FUNC(match_yes)),
>>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
>> @@ -298,8 +298,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>>  			  XE_RTP_RULES(FUNC(match_yes)),
>>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1)))
>>  			},
>> -			{}
>> -		},
>> +		),
>>  	},
>>  	{
>>  		.name = "no-match-no-add",
>> @@ -309,7 +308,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>>  		.expected_active = BIT(0),
>>  		.expected_count_sr_entries = 1,
>>  		/* Don't coalesce second entry since rules don't match */
>> -		.entries = (const struct xe_rtp_entry_sr[]) {
>> +		.table = XE_RTP_TABLE_SR(
>>  			{ XE_RTP_NAME("basic-1"),
>>  			  XE_RTP_RULES(FUNC(match_yes)),
>>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
>> @@ -318,8 +317,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>>  			  XE_RTP_RULES(FUNC(match_no)),
>>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1)))
>>  			},
>> -			{}
>> -		},
>> +		),
>>  	},
>>  	{
>>  		.name = "two-regs-two-entries",
>> @@ -329,7 +327,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>>  		.expected_active = BIT(0) | BIT(1),
>>  		.expected_count_sr_entries = 2,
>>  		/* Same bits on different registers are not coalesced */
>> -		.entries = (const struct xe_rtp_entry_sr[]) {
>> +		.table = XE_RTP_TABLE_SR(
>>  			{ XE_RTP_NAME("basic-1"),
>>  			  XE_RTP_RULES(FUNC(match_yes)),
>>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
>> @@ -338,8 +336,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>>  			  XE_RTP_RULES(FUNC(match_yes)),
>>  			  XE_RTP_ACTIONS(SET(REGULAR_REG2, REG_BIT(0)))
>>  			},
>> -			{}
>> -		},
>> +		),
>>  	},
>>  	{
>>  		.name = "clr-one-set-other",
>> @@ -349,7 +346,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>>  		.expected_active = BIT(0) | BIT(1),
>>  		.expected_count_sr_entries = 1,
>>  		/* Check clr vs set actions on different bits */
>> -		.entries = (const struct xe_rtp_entry_sr[]) {
>> +		.table = XE_RTP_TABLE_SR(
>>  			{ XE_RTP_NAME("basic-1"),
>>  			  XE_RTP_RULES(FUNC(match_yes)),
>>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
>> @@ -358,8 +355,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>>  			  XE_RTP_RULES(FUNC(match_yes)),
>>  			  XE_RTP_ACTIONS(CLR(REGULAR_REG1, REG_BIT(1)))
>>  			},
>> -			{}
>> -		},
>> +		),
>>  	},
>>  	{
>>  #define TEMP_MASK	REG_GENMASK(10, 8)
>> @@ -371,14 +367,13 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>>  		.expected_active = BIT(0),
>>  		.expected_count_sr_entries = 1,
>>  		/* Check FIELD_SET works */
>> -		.entries = (const struct xe_rtp_entry_sr[]) {
>> +		.table = XE_RTP_TABLE_SR(
>>  			{ XE_RTP_NAME("basic-1"),
>>  			  XE_RTP_RULES(FUNC(match_yes)),
>>  			  XE_RTP_ACTIONS(FIELD_SET(REGULAR_REG1,
>>  						   TEMP_MASK, TEMP_FIELD))
>>  			},
>> -			{}
>> -		},
>> +		),
>>  #undef TEMP_MASK
>>  #undef TEMP_FIELD
>>  	},
>> @@ -390,7 +385,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>>  		.expected_active = BIT(0) | BIT(1),
>>  		.expected_count_sr_entries = 1,
>>  		.expected_sr_errors = 1,
>> -		.entries = (const struct xe_rtp_entry_sr[]) {
>> +		.table = XE_RTP_TABLE_SR(
>>  			{ XE_RTP_NAME("basic-1"),
>>  			  XE_RTP_RULES(FUNC(match_yes)),
>>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
>> @@ -400,8 +395,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>>  			  XE_RTP_RULES(FUNC(match_yes)),
>>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
>>  			},
>> -			{}
>> -		},
>> +		),
>>  	},
>>  	{
>>  		.name = "conflict-not-disjoint",
>> @@ -411,7 +405,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>>  		.expected_active = BIT(0) | BIT(1),
>>  		.expected_count_sr_entries = 1,
>>  		.expected_sr_errors = 1,
>> -		.entries = (const struct xe_rtp_entry_sr[]) {
>> +		.table = XE_RTP_TABLE_SR(
>>  			{ XE_RTP_NAME("basic-1"),
>>  			  XE_RTP_RULES(FUNC(match_yes)),
>>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
>> @@ -421,8 +415,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>>  			  XE_RTP_RULES(FUNC(match_yes)),
>>  			  XE_RTP_ACTIONS(CLR(REGULAR_REG1, REG_GENMASK(1, 0)))
>>  			},
>> -			{}
>> -		},
>> +		),
>>  	},
>>  	{
>>  		.name = "conflict-reg-type",
>> @@ -432,7 +425,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>>  		.expected_active = BIT(0) | BIT(1) | BIT(2),
>>  		.expected_count_sr_entries = 1,
>>  		.expected_sr_errors = 2,
>> -		.entries = (const struct xe_rtp_entry_sr[]) {
>> +		.table = XE_RTP_TABLE_SR(
>>  			{ XE_RTP_NAME("basic-1"),
>>  			  XE_RTP_RULES(FUNC(match_yes)),
>>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
>> @@ -447,8 +440,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>>  			  XE_RTP_RULES(FUNC(match_yes)),
>>  			  XE_RTP_ACTIONS(SET(MASKED_REG1, REG_BIT(0)))
>>  			},
>> -			{}
>> -		},
>> +		),
>>  	},
>>  	{
>>  		.name = "bad-mcr-reg-forced-to-regular",
>> @@ -458,13 +450,13 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>>  		.expected_active = BIT(0),
>>  		.expected_count_sr_entries = 1,
>>  		.expected_sr_errors = 1,
>> -		.entries = (const struct xe_rtp_entry_sr[]) {
>> +		.table = XE_RTP_TABLE_SR(
>>  			{ XE_RTP_NAME("bad-mcr-regular-reg"),
>>  			  XE_RTP_RULES(FUNC(match_yes)),
>>  			  XE_RTP_ACTIONS(SET(BAD_MCR_REG4, REG_BIT(0)))
>>  			},
>>  			{}
>> -		},
>> +		),
>>  	},
>>  	{
>>  		.name = "bad-regular-reg-forced-to-mcr",
>> @@ -474,13 +466,13 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>>  		.expected_active = BIT(0),
>>  		.expected_count_sr_entries = 1,
>>  		.expected_sr_errors = 1,
>> -		.entries = (const struct xe_rtp_entry_sr[]) {
>> +		.table = XE_RTP_TABLE_SR(
>>  			{ XE_RTP_NAME("bad-regular-reg"),
>>  			  XE_RTP_RULES(FUNC(match_yes)),
>>  			  XE_RTP_ACTIONS(SET(BAD_REGULAR_REG5, REG_BIT(0)))
>>  			},
>>  			{}
>> -		},
>> +		),
>>  	},
>>  };
>>  
>> @@ -492,16 +484,12 @@ static void xe_rtp_process_to_sr_tests(struct kunit *test)
>>  	struct xe_reg_sr *reg_sr = &gt->reg_sr;
>>  	const struct xe_reg_sr_entry *sre, *sr_entry = NULL;
>>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
>> -	unsigned long idx, count_sr_entries = 0, count_rtp_entries = 0, active = 0;
>> +	unsigned long idx, count_sr_entries = 0, active = 0;
>>  
>>  	xe_reg_sr_init(reg_sr, "xe_rtp_to_sr_tests", xe);
>>  
>> -	while (param->entries[count_rtp_entries].rules)
>> -		count_rtp_entries++;
>> -
>> -	xe_rtp_process_ctx_enable_active_tracking(&ctx, &active, count_rtp_entries);
>> -	xe_rtp_process_to_sr(&ctx, param->entries, count_rtp_entries,
>> -			     reg_sr, false);
>> +	xe_rtp_process_ctx_enable_active_tracking(&ctx, &active, param->table.n_entries);
>> +	xe_rtp_process_to_sr(&ctx, &param->table, reg_sr, false);
>>  
>>  	xa_for_each(&reg_sr->xa, idx, sre) {
>>  		if (idx == param->expected_reg.addr)
>> @@ -534,56 +522,52 @@ static const struct rtp_test_case rtp_cases[] = {
>>  	{
>>  		.name = "active1",
>>  		.expected_active = BIT(0),
>> -		.entries = (const struct xe_rtp_entry[]) {
>> +		.table = XE_RTP_TABLE(
>>  			{ XE_RTP_NAME("r1"),
>>  			  XE_RTP_RULES(FUNC(match_yes)),
>>  			},
>> -			{}
>> -		},
>> +		),
>>  	},
>>  	{
>>  		.name = "active2",
>>  		.expected_active = BIT(0) | BIT(1),
>> -		.entries = (const struct xe_rtp_entry[]) {
>> +		.table = XE_RTP_TABLE(
>>  			{ XE_RTP_NAME("r1"),
>>  			  XE_RTP_RULES(FUNC(match_yes)),
>>  			},
>>  			{ XE_RTP_NAME("r2"),
>>  			  XE_RTP_RULES(FUNC(match_yes)),
>>  			},
>> -			{}
>> -		},
>> +		),
>>  	},
>>  	{
>>  		.name = "active-inactive",
>>  		.expected_active = BIT(0),
>> -		.entries = (const struct xe_rtp_entry[]) {
>> +		.table = XE_RTP_TABLE(
>>  			{ XE_RTP_NAME("r1"),
>>  			  XE_RTP_RULES(FUNC(match_yes)),
>>  			},
>>  			{ XE_RTP_NAME("r2"),
>>  			  XE_RTP_RULES(FUNC(match_no)),
>>  			},
>> -			{}
>> -		},
>> +		),
>>  	},
>>  	{
>>  		.name = "inactive-active",
>>  		.expected_active = BIT(1),
>> -		.entries = (const struct xe_rtp_entry[]) {
>> +		.table = XE_RTP_TABLE(
>>  			{ XE_RTP_NAME("r1"),
>>  			  XE_RTP_RULES(FUNC(match_no)),
>>  			},
>>  			{ XE_RTP_NAME("r2"),
>>  			  XE_RTP_RULES(FUNC(match_yes)),
>>  			},
>> -			{}
>> -		},
>> +		),
>>  	},
>>  	{
>>  		.name = "inactive-active-inactive",
>>  		.expected_active = BIT(1),
>> -		.entries = (const struct xe_rtp_entry[]) {
>> +		.table = XE_RTP_TABLE(
>>  			{ XE_RTP_NAME("r1"),
>>  			  XE_RTP_RULES(FUNC(match_no)),
>>  			},
>> @@ -593,13 +577,12 @@ static const struct rtp_test_case rtp_cases[] = {
>>  			{ XE_RTP_NAME("r3"),
>>  			  XE_RTP_RULES(FUNC(match_no)),
>>  			},
>> -			{}
>> -		},
>> +		),
>>  	},
>>  	{
>>  		.name = "inactive-inactive-inactive",
>>  		.expected_active = 0,
>> -		.entries = (const struct xe_rtp_entry[]) {
>> +		.table = XE_RTP_TABLE(
>>  			{ XE_RTP_NAME("r1"),
>>  			  XE_RTP_RULES(FUNC(match_no)),
>>  			},
>> @@ -609,8 +592,7 @@ static const struct rtp_test_case rtp_cases[] = {
>>  			{ XE_RTP_NAME("r3"),
>>  			  XE_RTP_RULES(FUNC(match_no)),
>>  			},
>> -			{}
>> -		},
>> +		),
>>  	},
>>  };
>>  
>> @@ -620,13 +602,10 @@ static void xe_rtp_process_tests(struct kunit *test)
>>  	struct xe_device *xe = test->priv;
>>  	struct xe_gt *gt = xe_device_get_root_tile(xe)->primary_gt;
>>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
>> -	unsigned long count_rtp_entries = 0, active = 0;
>> -
>> -	while (param->entries[count_rtp_entries].rules)
>> -		count_rtp_entries++;
>> +	unsigned long active = 0;
>>  
>> -	xe_rtp_process_ctx_enable_active_tracking(&ctx, &active, count_rtp_entries);
>> -	xe_rtp_process(&ctx, param->entries);
>> +	xe_rtp_process_ctx_enable_active_tracking(&ctx, &active, param->table.n_entries);
>> +	xe_rtp_process(&ctx, &param->table);
>>  
>>  	KUNIT_EXPECT_EQ(test, active, param->expected_active);
>>  }
>> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
>> index 8c66ff6f3d3c..98265293f2dc 100644
>> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
>> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
>> @@ -346,7 +346,7 @@ hw_engine_setup_default_lrc_state(struct xe_hw_engine *hwe)
>>  	u32 blit_cctl_val = REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, mocs_write_idx) |
>>  			    REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, mocs_read_idx);
>>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
>> -	const struct xe_rtp_entry_sr lrc_setup[] = {
>> +	const struct xe_rtp_table_sr lrc_setup = XE_RTP_TABLE_SR(
>>  		/*
>>  		 * Some blitter commands do not have a field for MOCS, those
>>  		 * commands will use MOCS index pointed by BLIT_CCTL.
>> @@ -369,10 +369,9 @@ hw_engine_setup_default_lrc_state(struct xe_hw_engine *hwe)
>>  					   PREEMPT_GPGPU_THREAD_GROUP_LEVEL)),
>>  		  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE)
>>  		},
>> -	};
>> +	);
>>  
>> -	xe_rtp_process_to_sr(&ctx, lrc_setup, ARRAY_SIZE(lrc_setup),
>> -			     &hwe->reg_lrc, true);
>> +	xe_rtp_process_to_sr(&ctx, &lrc_setup, &hwe->reg_lrc, true);
>>  }
>>  
>>  void xe_hw_engine_setup_reg_lrc(struct xe_hw_engine *hwe)
>> @@ -408,7 +407,7 @@ hw_engine_setup_default_state(struct xe_hw_engine *hwe)
>>  	u32 ring_cmd_cctl_val = REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, mocs_write_idx) |
>>  				REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, mocs_read_idx);
>>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
>> -	const struct xe_rtp_entry_sr engine_entries[] = {
>> +	const struct xe_rtp_table_sr engine_sr = XE_RTP_TABLE_SR(
>>  		{ XE_RTP_NAME("RING_CMD_CCTL_default_MOCS"),
>>  		  XE_RTP_RULES(FUNC(xe_rtp_match_always)),
>>  		  XE_RTP_ACTIONS(FIELD_SET(RING_CMD_CCTL(0),
>> @@ -465,10 +464,9 @@ hw_engine_setup_default_state(struct xe_hw_engine *hwe)
>>  		  XE_RTP_ACTIONS(SET(GFX_MODE(0), GFX_MSIX_INTERRUPT_ENABLE,
>>  				     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
>>  		},
>> -	};
>> +	);
>>  
>> -	xe_rtp_process_to_sr(&ctx, engine_entries, ARRAY_SIZE(engine_entries),
>> -			     &hwe->reg_sr, false);
>> +	xe_rtp_process_to_sr(&ctx, &engine_sr, &hwe->reg_sr, false);
>>  }
>>  
>>  static const struct engine_info *find_engine_info(enum xe_engine_class class, int instance)
>> diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
>> index fb65940848d7..2e84b1c49f37 100644
>> --- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
>> +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
>> @@ -41,7 +41,7 @@ static bool match_multi_queue_class(const struct xe_device *xe,
>>  	return xe_gt_supports_multi_queue(gt, hwe->class);
>>  }
>>  
>> -static const struct xe_rtp_entry_sr register_whitelist[] = {
>> +static const struct xe_rtp_table_sr register_whitelist = XE_RTP_TABLE_SR(
>>  	{ XE_RTP_NAME("WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865"),
>>  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
>>  	  XE_RTP_ACTIONS(WHITELIST(PS_INVOCATION_COUNT,
>> @@ -154,7 +154,7 @@ static const struct xe_rtp_entry_sr register_whitelist[] = {
>>  	  XE_RTP_RULES(FUNC(match_has_mert), ENGINE_CLASS(COPY)),
>>  	  XE_RTP_ACTIONS(WHITELIST_OA_MERT_MMIO_TRG)
>>  	},
>> -};
>> +);
>>  
>>  static void whitelist_apply_to_hwe(struct xe_hw_engine *hwe)
>>  {
>> @@ -202,8 +202,7 @@ void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe)
>>  {
>>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
>>  
>> -	xe_rtp_process_to_sr(&ctx, register_whitelist, ARRAY_SIZE(register_whitelist),
>> -			     &hwe->reg_whitelist, false);
>> +	xe_rtp_process_to_sr(&ctx, &register_whitelist, &hwe->reg_whitelist, false);
>>  	whitelist_apply_to_hwe(hwe);
>>  }
>>  
>> diff --git a/drivers/gpu/drm/xe/xe_rtp.c b/drivers/gpu/drm/xe/xe_rtp.c
>> index dec9d94e6fb0..83a40e1f9528 100644
>> --- a/drivers/gpu/drm/xe/xe_rtp.c
>> +++ b/drivers/gpu/drm/xe/xe_rtp.c
>> @@ -326,8 +326,7 @@ static void rtp_mark_active(struct xe_device *xe,
>>   * xe_rtp_process_to_sr - Process all rtp @entries, adding the matching ones to
>>   *                        the save-restore argument.
>>   * @ctx: The context for processing the table, with one of device, gt or hwe
>> - * @entries: Table with RTP definitions
>> - * @n_entries: Number of entries to process, usually ARRAY_SIZE(entries)
>> + * @table: Table with RTP definitions
>>   * @sr: Save-restore struct where matching rules execute the action. This can be
>>   *      viewed as the "coalesced view" of multiple the tables. The bits for each
>>   *      register set are expected not to collide with previously added entries
>> @@ -339,12 +338,10 @@ static void rtp_mark_active(struct xe_device *xe,
>>   * used to calculate the right register offset
>>   */
>>  void xe_rtp_process_to_sr(struct xe_rtp_process_ctx *ctx,
>> -			  const struct xe_rtp_entry_sr *entries,
>> -			  size_t n_entries,
>> +			  const struct xe_rtp_table_sr *table,
>>  			  struct xe_reg_sr *sr,
>>  			  bool process_in_vf)
>>  {
>> -	const struct xe_rtp_entry_sr *entry;
>>  	struct xe_hw_engine *hwe = NULL;
>>  	struct xe_gt *gt = NULL;
>>  	struct xe_device *xe = NULL;
>> @@ -354,9 +351,10 @@ void xe_rtp_process_to_sr(struct xe_rtp_process_ctx *ctx,
>>  	if (!process_in_vf && IS_SRIOV_VF(xe))
>>  		return;
>>  
>> -	xe_assert(xe, entries);
>> +	xe_assert(xe, table->entries);
>>  
>> -	for (entry = entries; entry - entries < n_entries; entry++) {
>> +	for (size_t i = 0; i < table->n_entries; i++) {
>> +		const struct xe_rtp_entry_sr *entry = &table->entries[i];
>>  		bool match = false;
>>  
>>  		if (entry->flags & XE_RTP_ENTRY_FLAG_FOREACH_ENGINE) {
>> @@ -371,37 +369,40 @@ void xe_rtp_process_to_sr(struct xe_rtp_process_ctx *ctx,
>>  		}
>>  
>>  		if (match)
>> -			rtp_mark_active(xe, ctx, entry - entries);
>> +			rtp_mark_active(xe, ctx, i);
>>  	}
>>  }
>>  EXPORT_SYMBOL_IF_KUNIT(xe_rtp_process_to_sr);
>>  
>>  /**
>> - * xe_rtp_process - Process all rtp @entries, without running any action
>> + * xe_rtp_process - Process all entries in rtp @table, without running any action
>>   * @ctx: The context for processing the table, with one of device, gt or hwe
>> - * @entries: Table with RTP definitions
>> + * @table: Table with RTP definitions
>>   *
>> - * Walk the table pointed by @entries (with an empty sentinel), executing the
>> + * Walk the table pointed by @table, executing the
>>   * rules. One difference from xe_rtp_process_to_sr(): there is no action
>>   * associated with each entry since this uses struct xe_rtp_entry. Its main use
>>   * is for marking active workarounds via
>>   * xe_rtp_process_ctx_enable_active_tracking().
>>   */
>>  void xe_rtp_process(struct xe_rtp_process_ctx *ctx,
>> -		    const struct xe_rtp_entry *entries)
>> +		    const struct xe_rtp_table *table)
>>  {
>> -	const struct xe_rtp_entry *entry;
>>  	struct xe_hw_engine *hwe;
>>  	struct xe_gt *gt;
>>  	struct xe_device *xe;
>>  
>>  	rtp_get_context(ctx, &hwe, &gt, &xe);
>>  
>> -	for (entry = entries; entry && entry->rules; entry++) {
>> +	xe_assert(xe, table->entries);
>> +
>> +	for (size_t i = 0; i < table->n_entries; i++) {
>> +		const struct xe_rtp_entry *entry = &table->entries[i];
>> +
>>  		if (!rule_matches(xe, gt, hwe, entry->rules, entry->n_rules))
>>  			continue;
>>  
>> -		rtp_mark_active(xe, ctx, entry - entries);
>> +		rtp_mark_active(xe, ctx, i);
>>  	}
>>  }
>>  EXPORT_SYMBOL_IF_KUNIT(xe_rtp_process);
>> diff --git a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h
>> index e4f1930ca1c3..4e3cfd69f922 100644
>> --- a/drivers/gpu/drm/xe/xe_rtp.h
>> +++ b/drivers/gpu/drm/xe/xe_rtp.h
>> @@ -461,6 +461,16 @@ struct xe_reg_sr;
>>  		XE_RTP_PASTE_FOREACH(ACTION_, COMMA, (__VA_ARGS__))	\
>>  	}
>>  
>> +#define XE_RTP_TABLE_SR(...) { \
>> +	.entries = (const struct xe_rtp_entry_sr[]){__VA_ARGS__}, \
>> +	.n_entries = ARRAY_SIZE(((const struct xe_rtp_entry_sr[]){__VA_ARGS__})), \
>> +}
>> +
>> +#define XE_RTP_TABLE(...) { \
>> +	.entries = (const struct xe_rtp_entry[]){__VA_ARGS__}, \
>> +	.n_entries = ARRAY_SIZE(((const struct xe_rtp_entry[]){__VA_ARGS__})), \
>> +}
>> +
>>  #define XE_RTP_PROCESS_CTX_INITIALIZER(arg__) _Generic((arg__),							\
>>  	struct xe_hw_engine * :	(struct xe_rtp_process_ctx){ { (void *)(arg__) }, XE_RTP_PROCESS_TYPE_ENGINE },	\
>>  	struct xe_gt * :	(struct xe_rtp_process_ctx){ { (void *)(arg__) }, XE_RTP_PROCESS_TYPE_GT },	\
>> @@ -471,12 +481,12 @@ void xe_rtp_process_ctx_enable_active_tracking(struct xe_rtp_process_ctx *ctx,
>>  					       size_t n_entries);
>>  
>>  void xe_rtp_process_to_sr(struct xe_rtp_process_ctx *ctx,
>> -			  const struct xe_rtp_entry_sr *entries,
>> -			  size_t n_entries, struct xe_reg_sr *sr,
>> +			  const struct xe_rtp_table_sr *table,
>> +			  struct xe_reg_sr *sr,
>>  			  bool process_in_vf);
>>  
>>  void xe_rtp_process(struct xe_rtp_process_ctx *ctx,
>> -		    const struct xe_rtp_entry *entries);
>> +		    const struct xe_rtp_table *table);
>>  
>>  /* Match functions to be used with XE_RTP_MATCH_FUNC */
>>  
>> diff --git a/drivers/gpu/drm/xe/xe_rtp_types.h b/drivers/gpu/drm/xe/xe_rtp_types.h
>> index 0265c16d2762..58018ae4f8cc 100644
>> --- a/drivers/gpu/drm/xe/xe_rtp_types.h
>> +++ b/drivers/gpu/drm/xe/xe_rtp_types.h
>> @@ -112,6 +112,16 @@ struct xe_rtp_entry {
>>  	u8 n_rules;
>>  };
>>  
>> +struct xe_rtp_table_sr {
>> +	const struct xe_rtp_entry_sr *entries;
>> +	size_t n_entries;
>> +};
>> +
>> +struct xe_rtp_table {
>> +	const struct xe_rtp_entry *entries;
>> +	size_t n_entries;
>> +};
>> +
>>  enum xe_rtp_process_type {
>>  	XE_RTP_PROCESS_TYPE_DEVICE,
>>  	XE_RTP_PROCESS_TYPE_GT,
>> diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
>> index 9a1b3862e192..bf3fad9cdbef 100644
>> --- a/drivers/gpu/drm/xe/xe_tuning.c
>> +++ b/drivers/gpu/drm/xe/xe_tuning.c
>> @@ -20,7 +20,7 @@
>>  #undef XE_REG_MCR
>>  #define XE_REG_MCR(...)     XE_REG(__VA_ARGS__, .mcr = 1)
>>  
>> -static const struct xe_rtp_entry_sr gt_tunings[] = {
>> +static const struct xe_rtp_table_sr gt_tunings = XE_RTP_TABLE_SR(
>>  	{ XE_RTP_NAME("Tuning: Blend Fill Caching Optimization Disable"),
>>  	  XE_RTP_RULES(PLATFORM(DG2)),
>>  	  XE_RTP_ACTIONS(SET(XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS))
>> @@ -100,9 +100,9 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
>>  	  XE_RTP_ACTIONS(FIELD_SET(GAMSTLB_CTRL, BANK_HASH_MODE,
>>  				   BANK_HASH_4KB_MODE))
>>  	},
>> -};
>> +);
>>  
>> -static const struct xe_rtp_entry_sr engine_tunings[] = {
>> +static const struct xe_rtp_table_sr engine_tunings = XE_RTP_TABLE_SR(
>>  	{ XE_RTP_NAME("Tuning: L3 Hashing Mask"),
>>  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210),
>>  		       FUNC(xe_rtp_match_first_render_or_compute)),
>> @@ -129,9 +129,9 @@ static const struct xe_rtp_entry_sr engine_tunings[] = {
>>  		       FUNC(xe_rtp_match_first_render_or_compute)),
>>  	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN2, TILEY_LOCALID))
>>  	},
>> -};
>> +);
>>  
>> -static const struct xe_rtp_entry_sr lrc_tunings[] = {
>> +static const struct xe_rtp_table_sr lrc_tunings = XE_RTP_TABLE_SR(
>>  	{ XE_RTP_NAME("Tuning: Windower HW Filtering"),
>>  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3599), ENGINE_CLASS(RENDER)),
>>  	  XE_RTP_ACTIONS(SET(XEHP_COMMON_SLICE_CHICKEN4, HW_FILTERING))
>> @@ -171,7 +171,7 @@ static const struct xe_rtp_entry_sr lrc_tunings[] = {
>>  	  XE_RTP_ACTIONS(FIELD_SET(FF_MODE, VS_HIT_MAX_VALUE_MASK,
>>  				   REG_FIELD_PREP(VS_HIT_MAX_VALUE_MASK, 0x3f)))
>>  	},
>> -};
>> +);
>>  
>>  /**
>>   * xe_tuning_init - initialize gt with tunings bookkeeping
>> @@ -185,9 +185,9 @@ int xe_tuning_init(struct xe_gt *gt)
>>  	size_t n_lrc, n_engine, n_gt, total;
>>  	unsigned long *p;
>>  
>> -	n_gt = BITS_TO_LONGS(ARRAY_SIZE(gt_tunings));
>> -	n_engine = BITS_TO_LONGS(ARRAY_SIZE(engine_tunings));
>> -	n_lrc = BITS_TO_LONGS(ARRAY_SIZE(lrc_tunings));
>> +	n_gt = BITS_TO_LONGS(gt_tunings.n_entries);
>> +	n_engine = BITS_TO_LONGS(engine_tunings.n_entries);
>> +	n_lrc = BITS_TO_LONGS(lrc_tunings.n_entries);
>>  	total = n_gt + n_engine + n_lrc;
>>  
>>  	p = drmm_kzalloc(&xe->drm, sizeof(*p) * total, GFP_KERNEL);
>> @@ -210,9 +210,8 @@ void xe_tuning_process_gt(struct xe_gt *gt)
>>  
>>  	xe_rtp_process_ctx_enable_active_tracking(&ctx,
>>  						  gt->tuning_active.gt,
>> -						  ARRAY_SIZE(gt_tunings));
>> -	xe_rtp_process_to_sr(&ctx, gt_tunings, ARRAY_SIZE(gt_tunings),
>> -			     &gt->reg_sr, false);
>> +						  gt_tunings.n_entries);
>> +	xe_rtp_process_to_sr(&ctx, &gt_tunings, &gt->reg_sr, false);
>>  }
>>  EXPORT_SYMBOL_IF_KUNIT(xe_tuning_process_gt);
>>  
>> @@ -222,9 +221,8 @@ void xe_tuning_process_engine(struct xe_hw_engine *hwe)
>>  
>>  	xe_rtp_process_ctx_enable_active_tracking(&ctx,
>>  						  hwe->gt->tuning_active.engine,
>> -						  ARRAY_SIZE(engine_tunings));
>> -	xe_rtp_process_to_sr(&ctx, engine_tunings, ARRAY_SIZE(engine_tunings),
>> -			     &hwe->reg_sr, false);
>> +						  engine_tunings.n_entries);
>> +	xe_rtp_process_to_sr(&ctx, &engine_tunings, &hwe->reg_sr, false);
>>  }
>>  EXPORT_SYMBOL_IF_KUNIT(xe_tuning_process_engine);
>>  
>> @@ -242,9 +240,8 @@ void xe_tuning_process_lrc(struct xe_hw_engine *hwe)
>>  
>>  	xe_rtp_process_ctx_enable_active_tracking(&ctx,
>>  						  hwe->gt->tuning_active.lrc,
>> -						  ARRAY_SIZE(lrc_tunings));
>> -	xe_rtp_process_to_sr(&ctx, lrc_tunings, ARRAY_SIZE(lrc_tunings),
>> -			     &hwe->reg_lrc, true);
>> +						  lrc_tunings.n_entries);
>> +	xe_rtp_process_to_sr(&ctx, &lrc_tunings, &hwe->reg_lrc, true);
>>  }
>>  
>>  /**
>> @@ -259,18 +256,18 @@ int xe_tuning_dump(struct xe_gt *gt, struct drm_printer *p)
>>  	size_t idx;
>>  
>>  	drm_printf(p, "GT Tunings\n");
>> -	for_each_set_bit(idx, gt->tuning_active.gt, ARRAY_SIZE(gt_tunings))
>> -		drm_printf_indent(p, 1, "%s\n", gt_tunings[idx].name);
>> +	for_each_set_bit(idx, gt->tuning_active.gt, gt_tunings.n_entries)
>> +		drm_printf_indent(p, 1, "%s\n", gt_tunings.entries[idx].name);
>>  
>>  	drm_puts(p, "\n");
>>  	drm_printf(p, "Engine Tunings\n");
>> -	for_each_set_bit(idx, gt->tuning_active.engine, ARRAY_SIZE(engine_tunings))
>> -		drm_printf_indent(p, 1, "%s\n", engine_tunings[idx].name);
>> +	for_each_set_bit(idx, gt->tuning_active.engine, engine_tunings.n_entries)
>> +		drm_printf_indent(p, 1, "%s\n", engine_tunings.entries[idx].name);
>>  
>>  	drm_puts(p, "\n");
>>  	drm_printf(p, "LRC Tunings\n");
>> -	for_each_set_bit(idx, gt->tuning_active.lrc, ARRAY_SIZE(lrc_tunings))
>> -		drm_printf_indent(p, 1, "%s\n", lrc_tunings[idx].name);
>> +	for_each_set_bit(idx, gt->tuning_active.lrc, lrc_tunings.n_entries)
>> +		drm_printf_indent(p, 1, "%s\n", lrc_tunings.entries[idx].name);
>>  
>>  	return 0;
>>  }
>> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
>> index cb811f8a7781..b9d9fe0801aa 100644
>> --- a/drivers/gpu/drm/xe/xe_wa.c
>> +++ b/drivers/gpu/drm/xe/xe_wa.c
>> @@ -130,7 +130,7 @@
>>  __diag_push();
>>  __diag_ignore_all("-Woverride-init", "Allow field overrides in table");
>>  
>> -static const struct xe_rtp_entry_sr gt_was[] = {
>> +static const struct xe_rtp_table_sr gt_was = XE_RTP_TABLE_SR(
>>  	/* Workarounds applying over a range of IPs */
>>  
>>  	{ XE_RTP_NAME("14011060649"),
>> @@ -306,9 +306,9 @@ static const struct xe_rtp_entry_sr gt_was[] = {
>>  	  XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
>>  	  XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
>>  	},
>> -};
>> +);
>>  
>> -static const struct xe_rtp_entry_sr engine_was[] = {
>> +static const struct xe_rtp_table_sr engine_was = XE_RTP_TABLE_SR(
>>  	/* Workarounds applying over a range of IPs */
>>  
>>  	{ XE_RTP_NAME("22010931296, 18011464164, 14010919138"),
>> @@ -614,9 +614,9 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>>  		       FUNC(xe_rtp_match_first_render_or_compute)),
>>  	  XE_RTP_ACTIONS(SET(TDL_CHICKEN, BIT_APQ_OPT_DIS))
>>  	},
>> -};
>> +);
>>  
>> -static const struct xe_rtp_entry_sr lrc_was[] = {
>> +static const struct xe_rtp_table_sr lrc_was = XE_RTP_TABLE_SR(
>>  	{ XE_RTP_NAME("16011163337"),
>>  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
>>  	  /* read verification is ignored due to 1608008084. */
>> @@ -794,21 +794,29 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
>>  		       ENGINE_CLASS(RENDER)),
>>  	  XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX))
>>  	},
>> -};
>> +);
>>  
>> -static __maybe_unused const struct xe_rtp_entry oob_was[] = {
>> +static const struct xe_rtp_entry oob_was_entries[] = {
>>  #include <generated/xe_wa_oob.c>
>> -	{}
>>  };
>>  
>> -static_assert(ARRAY_SIZE(oob_was) - 1 == _XE_WA_OOB_COUNT);
>> +static_assert(ARRAY_SIZE(oob_was_entries)  == _XE_WA_OOB_COUNT);
>>  
>> -static __maybe_unused const struct xe_rtp_entry device_oob_was[] = {
>> +static __maybe_unused const struct xe_rtp_table oob_was = {
>> +	.entries = oob_was_entries,
>> +	.n_entries = ARRAY_SIZE(oob_was_entries),
>> +};
>> +
>> +static const struct xe_rtp_entry device_oob_was_entries[] = {
>>  #include <generated/xe_device_wa_oob.c>
>> -	{}
>>  };
>>  
>> -static_assert(ARRAY_SIZE(device_oob_was) - 1 == _XE_DEVICE_WA_OOB_COUNT);
>> +static_assert(ARRAY_SIZE(device_oob_was_entries) == _XE_DEVICE_WA_OOB_COUNT);
>> +
>> +static __maybe_unused const struct xe_rtp_table device_oob_was = {
>> +	.entries = device_oob_was_entries,
>> +	.n_entries = ARRAY_SIZE(device_oob_was_entries),
>> +};
>>  
>>  __diag_pop();
>>  
>> @@ -824,10 +832,10 @@ void xe_wa_process_device_oob(struct xe_device *xe)
>>  {
>>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(xe);
>>  
>> -	xe_rtp_process_ctx_enable_active_tracking(&ctx, xe->wa_active.oob, ARRAY_SIZE(device_oob_was));
>> +	xe_rtp_process_ctx_enable_active_tracking(&ctx, xe->wa_active.oob, device_oob_was.n_entries);
>>  
>>  	xe->wa_active.oob_initialized = true;
>> -	xe_rtp_process(&ctx, device_oob_was);
>> +	xe_rtp_process(&ctx, &device_oob_was);
>>  }
>>  
>>  /**
>> @@ -842,9 +850,9 @@ void xe_wa_process_gt_oob(struct xe_gt *gt)
>>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
>>  
>>  	xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.oob,
>> -						  ARRAY_SIZE(oob_was));
>> +						  oob_was.n_entries);
>>  	gt->wa_active.oob_initialized = true;
>> -	xe_rtp_process(&ctx, oob_was);
>> +	xe_rtp_process(&ctx, &oob_was);
>>  }
>>  
>>  /**
>> @@ -859,9 +867,8 @@ void xe_wa_process_gt(struct xe_gt *gt)
>>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
>>  
>>  	xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.gt,
>> -						  ARRAY_SIZE(gt_was));
>> -	xe_rtp_process_to_sr(&ctx, gt_was, ARRAY_SIZE(gt_was),
>> -			     &gt->reg_sr, false);
>> +						  gt_was.n_entries);
>> +	xe_rtp_process_to_sr(&ctx, &gt_was, &gt->reg_sr, false);
>>  }
>>  EXPORT_SYMBOL_IF_KUNIT(xe_wa_process_gt);
>>  
>> @@ -878,9 +885,8 @@ void xe_wa_process_engine(struct xe_hw_engine *hwe)
>>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
>>  
>>  	xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.engine,
>> -						  ARRAY_SIZE(engine_was));
>> -	xe_rtp_process_to_sr(&ctx, engine_was, ARRAY_SIZE(engine_was),
>> -			     &hwe->reg_sr, false);
>> +						  engine_was.n_entries);
>> +	xe_rtp_process_to_sr(&ctx, &engine_was, &hwe->reg_sr, false);
>>  }
>>  
>>  /**
>> @@ -896,9 +902,8 @@ void xe_wa_process_lrc(struct xe_hw_engine *hwe)
>>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
>>  
>>  	xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.lrc,
>> -						  ARRAY_SIZE(lrc_was));
>> -	xe_rtp_process_to_sr(&ctx, lrc_was, ARRAY_SIZE(lrc_was),
>> -			     &hwe->reg_lrc, true);
>> +						  lrc_was.n_entries);
>> +	xe_rtp_process_to_sr(&ctx, &lrc_was, &hwe->reg_lrc, true);
>>  }
>>  
>>  /**
>> @@ -912,7 +917,7 @@ int xe_wa_device_init(struct xe_device *xe)
>>  	unsigned long *p;
>>  
>>  	p = drmm_kzalloc(&xe->drm,
>> -			 sizeof(*p) * BITS_TO_LONGS(ARRAY_SIZE(device_oob_was)),
>> +			 sizeof(*p) * BITS_TO_LONGS(device_oob_was.n_entries),
>>  			 GFP_KERNEL);
>>  
>>  	if (!p)
>> @@ -935,10 +940,10 @@ int xe_wa_gt_init(struct xe_gt *gt)
>>  	size_t n_oob, n_lrc, n_engine, n_gt, total;
>>  	unsigned long *p;
>>  
>> -	n_gt = BITS_TO_LONGS(ARRAY_SIZE(gt_was));
>> -	n_engine = BITS_TO_LONGS(ARRAY_SIZE(engine_was));
>> -	n_lrc = BITS_TO_LONGS(ARRAY_SIZE(lrc_was));
>> -	n_oob = BITS_TO_LONGS(ARRAY_SIZE(oob_was));
>> +	n_gt = BITS_TO_LONGS(gt_was.n_entries);
>> +	n_engine = BITS_TO_LONGS(engine_was.n_entries);
>> +	n_lrc = BITS_TO_LONGS(lrc_was.n_entries);
>> +	n_oob = BITS_TO_LONGS(oob_was.n_entries);
>>  	total = n_gt + n_engine + n_lrc + n_oob;
>>  
>>  	p = drmm_kzalloc(&xe->drm, sizeof(*p) * total, GFP_KERNEL);
>> @@ -962,9 +967,9 @@ void xe_wa_device_dump(struct xe_device *xe, struct drm_printer *p)
>>  	size_t idx;
>>  
>>  	drm_printf(p, "Device OOB Workarounds\n");
>> -	for_each_set_bit(idx, xe->wa_active.oob, ARRAY_SIZE(device_oob_was))
>> -		if (device_oob_was[idx].name)
>> -			drm_printf_indent(p, 1, "%s\n", device_oob_was[idx].name);
>> +	for_each_set_bit(idx, xe->wa_active.oob, device_oob_was.n_entries)
>> +		if (device_oob_was.entries[idx].name)
>> +			drm_printf_indent(p, 1, "%s\n", device_oob_was.entries[idx].name);
>>  }
>>  
>>  /**
>> @@ -979,24 +984,24 @@ int xe_wa_gt_dump(struct xe_gt *gt, struct drm_printer *p)
>>  	size_t idx;
>>  
>>  	drm_printf(p, "GT Workarounds\n");
>> -	for_each_set_bit(idx, gt->wa_active.gt, ARRAY_SIZE(gt_was))
>> -		drm_printf_indent(p, 1, "%s\n", gt_was[idx].name);
>> +	for_each_set_bit(idx, gt->wa_active.gt, gt_was.n_entries)
>> +		drm_printf_indent(p, 1, "%s\n", gt_was.entries[idx].name);
>>  
>>  	drm_puts(p, "\n");
>>  	drm_printf(p, "Engine Workarounds\n");
>> -	for_each_set_bit(idx, gt->wa_active.engine, ARRAY_SIZE(engine_was))
>> -		drm_printf_indent(p, 1, "%s\n", engine_was[idx].name);
>> +	for_each_set_bit(idx, gt->wa_active.engine, engine_was.n_entries)
>> +		drm_printf_indent(p, 1, "%s\n", engine_was.entries[idx].name);
>>  
>>  	drm_puts(p, "\n");
>>  	drm_printf(p, "LRC Workarounds\n");
>> -	for_each_set_bit(idx, gt->wa_active.lrc, ARRAY_SIZE(lrc_was))
>> -		drm_printf_indent(p, 1, "%s\n", lrc_was[idx].name);
>> +	for_each_set_bit(idx, gt->wa_active.lrc, lrc_was.n_entries)
>> +		drm_printf_indent(p, 1, "%s\n", lrc_was.entries[idx].name);
>>  
>>  	drm_puts(p, "\n");
>>  	drm_printf(p, "OOB Workarounds\n");
>> -	for_each_set_bit(idx, gt->wa_active.oob, ARRAY_SIZE(oob_was))
>> -		if (oob_was[idx].name)
>> -			drm_printf_indent(p, 1, "%s\n", oob_was[idx].name);
>> +	for_each_set_bit(idx, gt->wa_active.oob, oob_was.n_entries)
>> +		if (oob_was.entries[idx].name)
>> +			drm_printf_indent(p, 1, "%s\n", oob_was.entries[idx].name);
>>  	return 0;
>>  }
>>  
>> -- 
>> 2.43.0

Re: [PATCH v5 2/4] drm/xe/rtp: Ensure gt_was doesn't evaluate rules with engine types

[Gustavo Sousa]

Violet Monti <violet.monti@intel.com> writes:

> It is currently possible for a RTP rule, and subsequently a workaround,
> to expect contexts that may not be present when the workaround is
> applied. For example, the workarounds in the engine_was[] in drm/xe/xe_wa.c
> expect an engine entity to be active. Conversely, the gt_was[] is not
> depending on an engine entity to implement its workarounds. This kunit
> test addition checks the gt_was[] workaround list for any workarounds
> with XEP_RTP_ENGINE_CLASS() rules. If a workaround does have one of
> these rules, the workaround is then checked for the "FOREACH_ENGINE" flag,
> which ensures the workaround is implemented properly.
>
> The result of this test is an expectation failure if a workaround has an
> improper XE_RTP_ENGINE_CLASS() rule setup, and aims to prevent future
> issues of gt_was workarounds being applied without proper contexts.
>
> The gt_tunings[] RTP table has the same functional layout and
> requirements as gt_was[], so it shares the same kunit test function,
> minimizing excessive code.
>
> v5:
>     - Remove unnecessary headers from xe_rtp_table_test.c
>
> v4:
>     - No change
>
> v3:
>     - Removed "VISIBLE_IF_KUNIT" keyword from xe_wa.h
>     - Added gt_tunings[] for testing
>     - Reworked KUNIT_EXPECT_TRUE() for easier parsing of errors
>
> v2:
>     - Moved contents of xe_rtp_tables_test.h to .c and removed file
>     - Renamed macro RTP_KUNIT_ARRAY_PARAM to RTP_TABLE_PARAM
>     - Removed unnecessary functions and iterative components from
>       generated _gen_params functions and implemented usage of table
>       name and WA number as entry name
>     - Condensed xe_rtp_table_gt_test() to use KUNIT_EXPECT_TRUE with no
>       message statement
>     - Removed xe_rtp_table_test_init() and xe_rtp_table_test_exit() as
>       fake device initialization is not necessary
>
> Signed-off-by: Violet Monti <violet.monti@intel.com>

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>

> ---
>  drivers/gpu/drm/xe/tests/Makefile             |  1 +
>  drivers/gpu/drm/xe/tests/xe_rtp_tables_test.c | 53 +++++++++++++++++++
>  drivers/gpu/drm/xe/xe_tuning.c                |  3 +-
>  drivers/gpu/drm/xe/xe_tuning.h                |  6 +++
>  drivers/gpu/drm/xe/xe_wa.c                    |  3 +-
>  drivers/gpu/drm/xe/xe_wa.h                    |  5 ++
>  6 files changed, 69 insertions(+), 2 deletions(-)
>  create mode 100644 drivers/gpu/drm/xe/tests/xe_rtp_tables_test.c
>
> diff --git a/drivers/gpu/drm/xe/tests/Makefile b/drivers/gpu/drm/xe/tests/Makefile
> index 0e3408f4952c..f7aa47f11a36 100644
> --- a/drivers/gpu/drm/xe/tests/Makefile
> +++ b/drivers/gpu/drm/xe/tests/Makefile
> @@ -9,5 +9,6 @@ obj-$(CONFIG_DRM_XE_KUNIT_TEST) += xe_test.o
>  xe_test-y = xe_test_mod.o \
>  	xe_args_test.o \
>  	xe_pci_test.o \
> +	xe_rtp_tables_test.o \
>  	xe_rtp_test.o \
>  	xe_wa_test.o
> diff --git a/drivers/gpu/drm/xe/tests/xe_rtp_tables_test.c b/drivers/gpu/drm/xe/tests/xe_rtp_tables_test.c
> new file mode 100644
> index 000000000000..7dd77133bc42
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/tests/xe_rtp_tables_test.c
> @@ -0,0 +1,53 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#include <kunit/test.h>
> +
> +#include "xe_rtp_types.h"
> +#include "xe_tuning.h"
> +#include "xe_wa.h"
> +
> +#define RTP_TABLE_PARAM(table)									\
> +	static const void *table##_gen_params(struct kunit *test,				\
> +					     const void *prev, char *desc)			\
> +	{											\
> +		typeof((table.entries)[0]) *__next = prev ?					\
> +			((typeof(__next))prev) + 1 : (table.entries);				\
> +		if (__next - table.entries < table.n_entries) {					\
> +			scnprintf(desc, KUNIT_PARAM_DESC_SIZE, #table "/%s", __next->name);	\
> +			return __next;								\
> +		}										\
> +		return NULL;									\
> +	}
> +
> +static void xe_rtp_table_gt_test(struct kunit *test)
> +{
> +	const struct xe_rtp_entry_sr *entry = test->param_value;
> +
> +	for (int i = 0; i < entry->n_rules; i++) {
> +		KUNIT_EXPECT_TRUE(test,
> +				  entry->rules[i].match_type != XE_RTP_MATCH_ENGINE_CLASS ||
> +				  entry->flags & XE_RTP_ENTRY_FLAG_FOREACH_ENGINE);
> +		KUNIT_EXPECT_TRUE(test,
> +				  entry->rules[i].match_type != XE_RTP_MATCH_NOT_ENGINE_CLASS ||
> +				  entry->flags & XE_RTP_ENTRY_FLAG_FOREACH_ENGINE);
> +	}
> +}
> +
> +RTP_TABLE_PARAM(gt_was);
> +RTP_TABLE_PARAM(gt_tunings);
> +
> +static struct kunit_case xe_rtp_table_tests[] = {
> +	KUNIT_CASE_PARAM(xe_rtp_table_gt_test, gt_was_gen_params),
> +	KUNIT_CASE_PARAM(xe_rtp_table_gt_test, gt_tunings_gen_params),
> +	{}
> +};
> +
> +static struct kunit_suite xe_rtp_tables_test_suite = {
> +	.name = "xe_rtp_tables_test",
> +	.test_cases = xe_rtp_table_tests,
> +};
> +
> +kunit_test_suite(xe_rtp_tables_test_suite);
> diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
> index bf3fad9cdbef..bcec40ca2d35 100644
> --- a/drivers/gpu/drm/xe/xe_tuning.c
> +++ b/drivers/gpu/drm/xe/xe_tuning.c
> @@ -20,7 +20,7 @@
>  #undef XE_REG_MCR
>  #define XE_REG_MCR(...)     XE_REG(__VA_ARGS__, .mcr = 1)
>  
> -static const struct xe_rtp_table_sr gt_tunings = XE_RTP_TABLE_SR(
> +VISIBLE_IF_KUNIT const struct xe_rtp_table_sr gt_tunings = XE_RTP_TABLE_SR(
>  	{ XE_RTP_NAME("Tuning: Blend Fill Caching Optimization Disable"),
>  	  XE_RTP_RULES(PLATFORM(DG2)),
>  	  XE_RTP_ACTIONS(SET(XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS))
> @@ -101,6 +101,7 @@ static const struct xe_rtp_table_sr gt_tunings = XE_RTP_TABLE_SR(
>  				   BANK_HASH_4KB_MODE))
>  	},
>  );
> +EXPORT_SYMBOL_IF_KUNIT(gt_tunings);
>  
>  static const struct xe_rtp_table_sr engine_tunings = XE_RTP_TABLE_SR(
>  	{ XE_RTP_NAME("Tuning: L3 Hashing Mask"),
> diff --git a/drivers/gpu/drm/xe/xe_tuning.h b/drivers/gpu/drm/xe/xe_tuning.h
> index d18e187debf6..869564e3e992 100644
> --- a/drivers/gpu/drm/xe/xe_tuning.h
> +++ b/drivers/gpu/drm/xe/xe_tuning.h
> @@ -6,6 +6,8 @@
>  #ifndef _XE_TUNING_H_
>  #define _XE_TUNING_H_
>  
> +#include <kunit/visibility.h>
> +
>  struct drm_printer;
>  struct xe_gt;
>  struct xe_hw_engine;
> @@ -16,4 +18,8 @@ void xe_tuning_process_engine(struct xe_hw_engine *hwe);
>  void xe_tuning_process_lrc(struct xe_hw_engine *hwe);
>  int xe_tuning_dump(struct xe_gt *gt, struct drm_printer *p);
>  
> +#if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
> +extern const struct xe_rtp_table_sr gt_tunings;
> +#endif
> +
>  #endif
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index b9d9fe0801aa..1a1e04215f21 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -130,7 +130,7 @@
>  __diag_push();
>  __diag_ignore_all("-Woverride-init", "Allow field overrides in table");
>  
> -static const struct xe_rtp_table_sr gt_was = XE_RTP_TABLE_SR(
> +VISIBLE_IF_KUNIT const struct xe_rtp_table_sr gt_was = XE_RTP_TABLE_SR(
>  	/* Workarounds applying over a range of IPs */
>  
>  	{ XE_RTP_NAME("14011060649"),
> @@ -307,6 +307,7 @@ static const struct xe_rtp_table_sr gt_was = XE_RTP_TABLE_SR(
>  	  XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
>  	},
>  );
> +EXPORT_SYMBOL_IF_KUNIT(gt_was);
>  
>  static const struct xe_rtp_table_sr engine_was = XE_RTP_TABLE_SR(
>  	/* Workarounds applying over a range of IPs */
> diff --git a/drivers/gpu/drm/xe/xe_wa.h b/drivers/gpu/drm/xe/xe_wa.h
> index a5f7d33c1b32..8784b491dde7 100644
> --- a/drivers/gpu/drm/xe/xe_wa.h
> +++ b/drivers/gpu/drm/xe/xe_wa.h
> @@ -6,6 +6,7 @@
>  #ifndef _XE_WA_H_
>  #define _XE_WA_H_
>  
> +#include <kunit/visibility.h>
>  #include "xe_assert.h"
>  
>  struct drm_printer;
> @@ -24,6 +25,10 @@ void xe_wa_apply_tile_workarounds(struct xe_tile *tile);
>  void xe_wa_device_dump(struct xe_device *xe, struct drm_printer *p);
>  int xe_wa_gt_dump(struct xe_gt *gt, struct drm_printer *p);
>  
> +#if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
> +extern const struct xe_rtp_table_sr gt_was;
> +#endif
> +
>  /**
>   * XE_GT_WA - Out-of-band GT workarounds, to be queried and called as needed.
>   * @gt__: gt instance
> -- 
> 2.43.0

✓ Xe.CI.FULL: success for drm/xe/rtp: WA table context testing

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 54640 bytes --]

== Series Details ==

Series: drm/xe/rtp: WA table context testing
URL   : https://patchwork.freedesktop.org/series/167474/
State : success

== Summary ==

CI Bug Log - changes from xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b_FULL -> xe-pw-167474v1_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-167474v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@fbdev@unaligned-write:
    - shard-bmg:          [PASS][1] -> [FAIL][2] ([Intel XE#7950])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-bmg-3/igt@fbdev@unaligned-write.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-2/igt@fbdev@unaligned-write.html

  * igt@intel_hwmon@hwmon-write:
    - shard-lnl:          NOTRUN -> [SKIP][3] ([Intel XE#1125] / [Intel XE#7312])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-8/igt@intel_hwmon@hwmon-write.html

  * igt@kms_atomic_transition@plane-all-transition@pipe-a-hdmi-a-3:
    - shard-bmg:          [PASS][4] -> [DMESG-FAIL][5] ([Intel XE#7774]) +1 other test dmesg-fail
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-bmg-5/igt@kms_atomic_transition@plane-all-transition@pipe-a-hdmi-a-3.html
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-2/igt@kms_atomic_transition@plane-all-transition@pipe-a-hdmi-a-3.html

  * igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-bmg:          NOTRUN -> [SKIP][6] ([Intel XE#7059] / [Intel XE#7085])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-10/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@x-tiled-16bpp-rotate-270:
    - shard-lnl:          NOTRUN -> [SKIP][7] ([Intel XE#1407]) +1 other test skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-5/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#2327]) +1 other test skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-8/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-64bpp-rotate-270:
    - shard-lnl:          NOTRUN -> [SKIP][9] ([Intel XE#1124]) +2 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-1/igt@kms_big_fb@y-tiled-64bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-64bpp-rotate-180:
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#1124])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-10/igt@kms_big_fb@yf-tiled-64bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-addfb:
    - shard-lnl:          NOTRUN -> [SKIP][11] ([Intel XE#1467] / [Intel XE#7367])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-5/igt@kms_big_fb@yf-tiled-addfb.html

  * igt@kms_bw@linear-tiling-1-displays-target-2560x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][12] ([Intel XE#367])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-5/igt@kms_bw@linear-tiling-1-displays-target-2560x1440p.html

  * igt@kms_bw@linear-tiling-3-displays-target-2560x1440p:
    - shard-lnl:          NOTRUN -> [SKIP][13] ([Intel XE#367])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-3/igt@kms_bw@linear-tiling-3-displays-target-2560x1440p.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs@pipe-b-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#2652]) +8 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-7/igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs@pipe-b-dp-2.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc:
    - shard-lnl:          NOTRUN -> [SKIP][15] ([Intel XE#2887]) +3 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-5/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][16] ([Intel XE#2887]) +3 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-4/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_chamelium_audio@dp-audio:
    - shard-lnl:          NOTRUN -> [SKIP][17] ([Intel XE#373]) +2 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-7/igt@kms_chamelium_audio@dp-audio.html

  * igt@kms_chamelium_color@ctm-max:
    - shard-bmg:          NOTRUN -> [SKIP][18] ([Intel XE#2325] / [Intel XE#7358])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-4/igt@kms_chamelium_color@ctm-max.html

  * igt@kms_chamelium_edid@dp-edid-change-during-hibernate:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#2252]) +1 other test skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-2/igt@kms_chamelium_edid@dp-edid-change-during-hibernate.html

  * igt@kms_chamelium_sharpness_filter@filter-basic:
    - shard-bmg:          NOTRUN -> [SKIP][20] ([Intel XE#6507])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-2/igt@kms_chamelium_sharpness_filter@filter-basic.html

  * igt@kms_content_protection@dp-mst-lic-type-1:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#2390] / [Intel XE#6974])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-8/igt@kms_content_protection@dp-mst-lic-type-1.html

  * igt@kms_cursor_crc@cursor-offscreen-128x42:
    - shard-bmg:          NOTRUN -> [SKIP][22] ([Intel XE#2320]) +1 other test skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-4/igt@kms_cursor_crc@cursor-offscreen-128x42.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-toggle:
    - shard-lnl:          NOTRUN -> [SKIP][23] ([Intel XE#309] / [Intel XE#7343])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-3/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#2286] / [Intel XE#6035])
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-7/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats:
    - shard-lnl:          NOTRUN -> [SKIP][25] ([Intel XE#4422] / [Intel XE#7442])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-2/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats.html

  * igt@kms_feature_discovery@display-4x:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#1138] / [Intel XE#7344])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-1/igt@kms_feature_discovery@display-4x.html

  * igt@kms_flip@2x-flip-vs-suspend-interruptible:
    - shard-lnl:          NOTRUN -> [SKIP][27] ([Intel XE#1421]) +1 other test skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-5/igt@kms_flip@2x-flip-vs-suspend-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-lnl:          NOTRUN -> [FAIL][28] ([Intel XE#301]) +1 other test fail
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling:
    - shard-lnl:          NOTRUN -> [SKIP][29] ([Intel XE#7178] / [Intel XE#7351])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
    - shard-bmg:          NOTRUN -> [SKIP][30] ([Intel XE#7178] / [Intel XE#7349])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-1/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html

  * igt@kms_force_connector_basic@force-edid:
    - shard-lnl:          NOTRUN -> [SKIP][31] ([Intel XE#352])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-5/igt@kms_force_connector_basic@force-edid.html

  * igt@kms_frontbuffer_tracking@drrshdr-1p-primscrn-indfb-msflip-blt:
    - shard-lnl:          NOTRUN -> [SKIP][32] ([Intel XE#6312]) +5 other tests skip
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-8/igt@kms_frontbuffer_tracking@drrshdr-1p-primscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt:
    - shard-lnl:          NOTRUN -> [SKIP][33] ([Intel XE#656] / [Intel XE#7905]) +10 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-modesetfrombusy:
    - shard-bmg:          NOTRUN -> [SKIP][34] ([Intel XE#4141]) +4 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-modesetfrombusy.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-tiling-linear:
    - shard-lnl:          NOTRUN -> [SKIP][35] ([Intel XE#6312] / [Intel XE#651]) +2 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-2/igt@kms_frontbuffer_tracking@fbcdrrs-tiling-linear.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-primscrn-shrfb-msflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][36] ([Intel XE#2311]) +21 other tests skip
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-primscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbchdr-argb161616f-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][37] ([Intel XE#6703]) +6 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbchdr-argb161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][38] ([Intel XE#7061] / [Intel XE#7356]) +2 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-4/igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-abgr161616f-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][39] ([Intel XE#7061]) +1 other test skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-8/igt@kms_frontbuffer_tracking@fbcpsrhdr-abgr161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@hdr-1p-primscrn-pri-indfb-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][40] ([Intel XE#7865]) +6 other tests skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-8/igt@kms_frontbuffer_tracking@hdr-1p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-onoff:
    - shard-bmg:          NOTRUN -> [SKIP][41] ([Intel XE#2313]) +17 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-8/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-pri-shrfb-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][42] ([Intel XE#7905]) +9 other tests skip
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-4/igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-pri-shrfb-draw-blt.html

  * igt@kms_hdr@static-toggle-suspend@pipe-a-hdmi-a-3-xrgb16161616f:
    - shard-bmg:          [PASS][43] -> [SKIP][44] ([Intel XE#7915]) +1 other test skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-bmg-6/igt@kms_hdr@static-toggle-suspend@pipe-a-hdmi-a-3-xrgb16161616f.html
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-8/igt@kms_hdr@static-toggle-suspend@pipe-a-hdmi-a-3-xrgb16161616f.html

  * igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#7283])
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-4/igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier.html

  * igt@kms_plane@pixel-format-yf-tiled-modifier:
    - shard-lnl:          NOTRUN -> [SKIP][46] ([Intel XE#7283])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-3/igt@kms_plane@pixel-format-yf-tiled-modifier.html

  * igt@kms_plane_scaling@intel-max-src-size:
    - shard-bmg:          [PASS][47] -> [SKIP][48] ([Intel XE#2685] / [Intel XE#3307])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-bmg-10/igt@kms_plane_scaling@intel-max-src-size.html
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-3/igt@kms_plane_scaling@intel-max-src-size.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-a:
    - shard-bmg:          NOTRUN -> [SKIP][49] ([Intel XE#2763] / [Intel XE#6886]) +4 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-10/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-a.html

  * igt@kms_pm_dc@dc5-psr:
    - shard-lnl:          [PASS][50] -> [FAIL][51] ([Intel XE#7340])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-lnl-2/igt@kms_pm_dc@dc5-psr.html
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-7/igt@kms_pm_dc@dc5-psr.html

  * igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf:
    - shard-bmg:          NOTRUN -> [SKIP][52] ([Intel XE#1489])
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-3/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@pr-plane-move-sf-dmg-area:
    - shard-lnl:          NOTRUN -> [SKIP][53] ([Intel XE#2893] / [Intel XE#7304]) +1 other test skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-7/igt@kms_psr2_sf@pr-plane-move-sf-dmg-area.html

  * igt@kms_psr@fbc-psr2-no-drrs:
    - shard-lnl:          NOTRUN -> [SKIP][54] ([Intel XE#1406] / [Intel XE#7345])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-4/igt@kms_psr@fbc-psr2-no-drrs.html

  * igt@kms_psr@fbc-psr2-no-drrs@edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][55] ([Intel XE#1406] / [Intel XE#4609])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-4/igt@kms_psr@fbc-psr2-no-drrs@edp-1.html

  * igt@kms_psr@pr-no-drrs:
    - shard-lnl:          NOTRUN -> [SKIP][56] ([Intel XE#1406])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-3/igt@kms_psr@pr-no-drrs.html

  * igt@kms_psr@psr-cursor-plane-move:
    - shard-bmg:          NOTRUN -> [SKIP][57] ([Intel XE#2234] / [Intel XE#2850]) +3 other tests skip
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-8/igt@kms_psr@psr-cursor-plane-move.html

  * igt@kms_psr@psr2-primary-render:
    - shard-bmg:          NOTRUN -> [SKIP][58] ([Intel XE#2234])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-9/igt@kms_psr@psr2-primary-render.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-270:
    - shard-bmg:          NOTRUN -> [SKIP][59] ([Intel XE#3904] / [Intel XE#7342])
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-1/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
    - shard-lnl:          NOTRUN -> [SKIP][60] ([Intel XE#1127] / [Intel XE#5813]) +1 other test skip
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-5/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@sprite-rotation-270:
    - shard-lnl:          NOTRUN -> [SKIP][61] ([Intel XE#3414] / [Intel XE#3904] / [Intel XE#7342])
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-4/igt@kms_rotation_crc@sprite-rotation-270.html

  * igt@xe_compute@eu-busy-10s:
    - shard-bmg:          NOTRUN -> [SKIP][62] ([Intel XE#6599])
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-7/igt@xe_compute@eu-busy-10s.html

  * igt@xe_create@invalid-pad:
    - shard-bmg:          [PASS][63] -> [SKIP][64] ([Intel XE#6557] / [Intel XE#6703])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-bmg-5/igt@xe_create@invalid-pad.html
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-2/igt@xe_create@invalid-pad.html

  * igt@xe_eudebug@basic-vm-bind-metadata-discovery:
    - shard-bmg:          NOTRUN -> [SKIP][65] ([Intel XE#7636]) +2 other tests skip
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-2/igt@xe_eudebug@basic-vm-bind-metadata-discovery.html

  * igt@xe_eudebug_online@interrupt-all-set-breakpoint:
    - shard-lnl:          NOTRUN -> [SKIP][66] ([Intel XE#7636]) +2 other tests skip
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-2/igt@xe_eudebug_online@interrupt-all-set-breakpoint.html

  * igt@xe_evict@evict-large-external:
    - shard-lnl:          NOTRUN -> [SKIP][67] ([Intel XE#6540] / [Intel XE#688]) +2 other tests skip
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-3/igt@xe_evict@evict-large-external.html

  * igt@xe_exec_balancer@twice-parallel-basic:
    - shard-lnl:          NOTRUN -> [SKIP][68] ([Intel XE#7482]) +4 other tests skip
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-7/igt@xe_exec_balancer@twice-parallel-basic.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-rebind:
    - shard-lnl:          NOTRUN -> [SKIP][69] ([Intel XE#1392]) +1 other test skip
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-2/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-rebind.html

  * igt@xe_exec_basic@multigpu-once-userptr:
    - shard-bmg:          NOTRUN -> [SKIP][70] ([Intel XE#2322] / [Intel XE#7372]) +1 other test skip
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-6/igt@xe_exec_basic@multigpu-once-userptr.html

  * igt@xe_exec_fault_mode@once-multi-queue-userptr-imm:
    - shard-bmg:          NOTRUN -> [SKIP][71] ([Intel XE#7136]) +3 other tests skip
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-4/igt@xe_exec_fault_mode@once-multi-queue-userptr-imm.html

  * igt@xe_exec_fault_mode@twice-multi-queue-userptr-invalidate-prefetch:
    - shard-lnl:          NOTRUN -> [SKIP][72] ([Intel XE#7136]) +4 other tests skip
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-8/igt@xe_exec_fault_mode@twice-multi-queue-userptr-invalidate-prefetch.html

  * igt@xe_exec_multi_queue@many-queues-userptr-invalidate:
    - shard-bmg:          NOTRUN -> [SKIP][73] ([Intel XE#6874]) +8 other tests skip
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-8/igt@xe_exec_multi_queue@many-queues-userptr-invalidate.html

  * igt@xe_exec_multi_queue@one-queue-preempt-mode-userptr:
    - shard-lnl:          NOTRUN -> [SKIP][74] ([Intel XE#6874]) +5 other tests skip
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-1/igt@xe_exec_multi_queue@one-queue-preempt-mode-userptr.html

  * igt@xe_exec_reset@multi-queue-close-fd:
    - shard-bmg:          NOTRUN -> [SKIP][75] ([Intel XE#7866])
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-2/igt@xe_exec_reset@multi-queue-close-fd.html

  * igt@xe_exec_reset@multi-queue-gt-reset:
    - shard-lnl:          NOTRUN -> [SKIP][76] ([Intel XE#7866])
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-1/igt@xe_exec_reset@multi-queue-gt-reset.html

  * igt@xe_exec_system_allocator@many-large-execqueues-new-race-nomemset:
    - shard-bmg:          [PASS][77] -> [SKIP][78] ([Intel XE#6703]) +51 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-bmg-8/igt@xe_exec_system_allocator@many-large-execqueues-new-race-nomemset.html
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-2/igt@xe_exec_system_allocator@many-large-execqueues-new-race-nomemset.html

  * igt@xe_exec_threads@threads-multi-queue-fd-userptr:
    - shard-lnl:          NOTRUN -> [SKIP][79] ([Intel XE#7138]) +2 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-3/igt@xe_exec_threads@threads-multi-queue-fd-userptr.html

  * igt@xe_exec_threads@threads-multi-queue-hang-fd-userptr-invalidate-race:
    - shard-bmg:          NOTRUN -> [SKIP][80] ([Intel XE#7138]) +2 other tests skip
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-5/igt@xe_exec_threads@threads-multi-queue-hang-fd-userptr-invalidate-race.html

  * igt@xe_module_load@load:
    - shard-lnl:          ([PASS][81], [PASS][82], [PASS][83], [PASS][84], [PASS][85], [PASS][86], [PASS][87], [PASS][88], [PASS][89], [PASS][90], [PASS][91], [PASS][92], [PASS][93], [PASS][94], [PASS][95], [PASS][96], [PASS][97], [PASS][98], [PASS][99], [PASS][100], [PASS][101], [PASS][102], [PASS][103], [PASS][104]) -> ([PASS][105], [PASS][106], [PASS][107], [PASS][108], [PASS][109], [PASS][110], [PASS][111], [PASS][112], [PASS][113], [PASS][114], [PASS][115], [SKIP][116], [PASS][117], [PASS][118], [PASS][119], [PASS][120], [PASS][121], [PASS][122], [PASS][123], [PASS][124], [PASS][125], [PASS][126], [PASS][127], [PASS][128], [PASS][129]) ([Intel XE#378] / [Intel XE#7405])
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-lnl-8/igt@xe_module_load@load.html
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-lnl-7/igt@xe_module_load@load.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-lnl-7/igt@xe_module_load@load.html
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-lnl-1/igt@xe_module_load@load.html
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-lnl-2/igt@xe_module_load@load.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-lnl-7/igt@xe_module_load@load.html
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-lnl-5/igt@xe_module_load@load.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-lnl-5/igt@xe_module_load@load.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-lnl-3/igt@xe_module_load@load.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-lnl-3/igt@xe_module_load@load.html
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-lnl-5/igt@xe_module_load@load.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-lnl-8/igt@xe_module_load@load.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-lnl-1/igt@xe_module_load@load.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-lnl-1/igt@xe_module_load@load.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-lnl-8/igt@xe_module_load@load.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-lnl-4/igt@xe_module_load@load.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-lnl-4/igt@xe_module_load@load.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-lnl-4/igt@xe_module_load@load.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-lnl-3/igt@xe_module_load@load.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-lnl-2/igt@xe_module_load@load.html
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-lnl-7/igt@xe_module_load@load.html
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-lnl-4/igt@xe_module_load@load.html
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-lnl-2/igt@xe_module_load@load.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-lnl-2/igt@xe_module_load@load.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-5/igt@xe_module_load@load.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-3/igt@xe_module_load@load.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-7/igt@xe_module_load@load.html
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-8/igt@xe_module_load@load.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-3/igt@xe_module_load@load.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-3/igt@xe_module_load@load.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-5/igt@xe_module_load@load.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-8/igt@xe_module_load@load.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-7/igt@xe_module_load@load.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-7/igt@xe_module_load@load.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-1/igt@xe_module_load@load.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-5/igt@xe_module_load@load.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-1/igt@xe_module_load@load.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-3/igt@xe_module_load@load.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-2/igt@xe_module_load@load.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-4/igt@xe_module_load@load.html
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-4/igt@xe_module_load@load.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-8/igt@xe_module_load@load.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-5/igt@xe_module_load@load.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-4/igt@xe_module_load@load.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-2/igt@xe_module_load@load.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-2/igt@xe_module_load@load.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-1/igt@xe_module_load@load.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-5/igt@xe_module_load@load.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-7/igt@xe_module_load@load.html

  * igt@xe_page_reclaim@boundary-split:
    - shard-bmg:          NOTRUN -> [SKIP][130] ([Intel XE#7793])
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-7/igt@xe_page_reclaim@boundary-split.html

  * igt@xe_pat@pat-index-xehpc:
    - shard-lnl:          NOTRUN -> [SKIP][131] ([Intel XE#1420] / [Intel XE#2838] / [Intel XE#7590])
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-2/igt@xe_pat@pat-index-xehpc.html

  * igt@xe_pm@d3hot-i2c:
    - shard-lnl:          NOTRUN -> [SKIP][132] ([Intel XE#5742] / [Intel XE#7328] / [Intel XE#7400])
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-7/igt@xe_pm@d3hot-i2c.html

  * igt@xe_pm@s2idle-d3cold-basic-exec:
    - shard-lnl:          NOTRUN -> [SKIP][133] ([Intel XE#2284] / [Intel XE#366] / [Intel XE#7370])
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-2/igt@xe_pm@s2idle-d3cold-basic-exec.html

  * igt@xe_pmu@all-fn-engine-activity-load:
    - shard-lnl:          NOTRUN -> [SKIP][134] ([Intel XE#4650] / [Intel XE#7347])
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-1/igt@xe_pmu@all-fn-engine-activity-load.html

  * igt@xe_pxp@pxp-optout:
    - shard-bmg:          NOTRUN -> [SKIP][135] ([Intel XE#4733] / [Intel XE#7417])
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-3/igt@xe_pxp@pxp-optout.html

  * igt@xe_sriov_flr@flr-basic:
    - shard-lnl:          NOTRUN -> [SKIP][136] ([Intel XE#7569])
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-2/igt@xe_sriov_flr@flr-basic.html

  * igt@xe_sriov_flr@flr-vf1-clear:
    - shard-bmg:          [PASS][137] -> [FAIL][138] ([Intel XE#6569]) +1 other test fail
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-bmg-9/igt@xe_sriov_flr@flr-vf1-clear.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-2/igt@xe_sriov_flr@flr-vf1-clear.html

  * igt@xe_sriov_vram@vf-access-after-resize-down:
    - shard-bmg:          [PASS][139] -> [FAIL][140] ([Intel XE#7992])
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-bmg-8/igt@xe_sriov_vram@vf-access-after-resize-down.html
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-7/igt@xe_sriov_vram@vf-access-after-resize-down.html

  * igt@xe_sriov_vram@vf-access-beyond:
    - shard-lnl:          NOTRUN -> [SKIP][141] ([Intel XE#6376] / [Intel XE#7330] / [Intel XE#7422])
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-7/igt@xe_sriov_vram@vf-access-beyond.html

  * igt@xe_vm@large-userptr-split-misaligned-binds-16777216:
    - shard-lnl:          [PASS][142] -> [ABORT][143] ([Intel XE#8007])
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-lnl-5/igt@xe_vm@large-userptr-split-misaligned-binds-16777216.html
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-4/igt@xe_vm@large-userptr-split-misaligned-binds-16777216.html

  * igt@xe_wedged@wedged-mode-toggle:
    - shard-bmg:          [PASS][144] -> [ABORT][145] ([Intel XE#8007])
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-bmg-8/igt@xe_wedged@wedged-mode-toggle.html
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-2/igt@xe_wedged@wedged-mode-toggle.html

  
#### Possible fixes ####

  * igt@kms_cursor_legacy@cursora-vs-flipb-varying-size:
    - shard-bmg:          [INCOMPLETE][146] ([Intel XE#8151]) -> [PASS][147]
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-bmg-2/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-6/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-bmg:          [FAIL][148] ([Intel XE#7571]) -> [PASS][149]
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-bmg-2/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-7/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_flip@blocking-wf_vblank:
    - shard-lnl:          [FAIL][150] ([Intel XE#6266]) -> [PASS][151] +1 other test pass
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-lnl-8/igt@kms_flip@blocking-wf_vblank.html
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-3/igt@kms_flip@blocking-wf_vblank.html

  * igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-upscaling:
    - shard-lnl:          [ABORT][152] ([Intel XE#8007]) -> [PASS][153] +1 other test pass
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-lnl-5/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-upscaling.html
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-2/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-upscaling.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [SKIP][154] ([Intel XE#1503]) -> [PASS][155]
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-bmg-4/igt@kms_hdr@invalid-hdr.html
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-7/igt@kms_hdr@invalid-hdr.html

  * igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-3-xrgb2101010:
    - shard-bmg:          [SKIP][156] ([Intel XE#7922]) -> [PASS][157] +1 other test pass
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-bmg-4/igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-3-xrgb2101010.html
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-7/igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-3-xrgb2101010.html

  * igt@kms_hdr@static-toggle@pipe-a-hdmi-a-3-xrgb16161616f:
    - shard-bmg:          [SKIP][158] ([Intel XE#7915]) -> [PASS][159] +1 other test pass
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-bmg-1/igt@kms_hdr@static-toggle@pipe-a-hdmi-a-3-xrgb16161616f.html
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-2/igt@kms_hdr@static-toggle@pipe-a-hdmi-a-3-xrgb16161616f.html

  * igt@kms_pm_dc@dc6-psr:
    - shard-lnl:          [FAIL][160] ([Intel XE#7340]) -> [PASS][161]
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-lnl-4/igt@kms_pm_dc@dc6-psr.html
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-7/igt@kms_pm_dc@dc6-psr.html

  * igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1:
    - shard-lnl:          [FAIL][162] ([Intel XE#2142]) -> [PASS][163] +1 other test pass
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-lnl-1/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-3/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html

  
#### Warnings ####

  * igt@kms_big_fb@yf-tiled-addfb:
    - shard-bmg:          [SKIP][164] ([Intel XE#2328] / [Intel XE#7367]) -> [SKIP][165] ([Intel XE#6703])
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-bmg-10/igt@kms_big_fb@yf-tiled-addfb.html
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-2/igt@kms_big_fb@yf-tiled-addfb.html

  * igt@kms_bw@linear-tiling-3-displays-target-3840x2160p:
    - shard-bmg:          [SKIP][166] ([Intel XE#367]) -> [SKIP][167] ([Intel XE#6703])
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-bmg-6/igt@kms_bw@linear-tiling-3-displays-target-3840x2160p.html
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-2/igt@kms_bw@linear-tiling-3-displays-target-3840x2160p.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-mc-ccs:
    - shard-bmg:          [SKIP][168] ([Intel XE#2887]) -> [SKIP][169] ([Intel XE#6703])
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-bmg-3/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-mc-ccs.html
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-2/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-mc-ccs.html

  * igt@kms_chamelium_frames@dp-crc-single:
    - shard-bmg:          [SKIP][170] ([Intel XE#2252]) -> [SKIP][171] ([Intel XE#6703]) +1 other test skip
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-bmg-8/igt@kms_chamelium_frames@dp-crc-single.html
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-2/igt@kms_chamelium_frames@dp-crc-single.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions:
    - shard-lnl:          [SKIP][172] ([Intel XE#309] / [Intel XE#7343]) -> [SKIP][173] ([Intel XE#309] / [Intel XE#7343] / [Intel XE#7935])
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-lnl-5/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-lnl-8/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
    - shard-bmg:          [SKIP][174] ([Intel XE#7178] / [Intel XE#7351]) -> [SKIP][175] ([Intel XE#6703])
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-bmg-1/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-2/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html

  * igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-render:
    - shard-bmg:          [SKIP][176] ([Intel XE#7061] / [Intel XE#7356]) -> [SKIP][177] ([Intel XE#6703])
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-render.html
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][178] ([Intel XE#2311]) -> [SKIP][179] ([Intel XE#6703]) +4 other tests skip
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-primscrn-cur-indfb-draw-mmap-wc.html
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-scndscrn-spr-indfb-onoff:
    - shard-bmg:          [SKIP][180] ([Intel XE#2313]) -> [SKIP][181] ([Intel XE#6703]) +2 other tests skip
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-scndscrn-spr-indfb-onoff.html
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-scndscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@psrhdr-abgr161616f-draw-mmap-wc:
    - shard-bmg:          [SKIP][182] ([Intel XE#7061]) -> [SKIP][183] ([Intel XE#6703])
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-bmg-3/igt@kms_frontbuffer_tracking@psrhdr-abgr161616f-draw-mmap-wc.html
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-2/igt@kms_frontbuffer_tracking@psrhdr-abgr161616f-draw-mmap-wc.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5:
    - shard-bmg:          [SKIP][184] ([Intel XE#2763] / [Intel XE#6886]) -> [SKIP][185] ([Intel XE#6703])
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-bmg-6/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5.html
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5.html

  * igt@kms_psr@fbc-psr-cursor-plane-onoff:
    - shard-bmg:          [SKIP][186] ([Intel XE#2234] / [Intel XE#2850]) -> [SKIP][187] ([Intel XE#6703])
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-bmg-9/igt@kms_psr@fbc-psr-cursor-plane-onoff.html
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-2/igt@kms_psr@fbc-psr-cursor-plane-onoff.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
    - shard-bmg:          [SKIP][188] ([Intel XE#2330] / [Intel XE#5813]) -> [SKIP][189] ([Intel XE#6703])
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-bmg-10/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-2/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [SKIP][190] ([Intel XE#2426] / [Intel XE#5848]) -> [FAIL][191] ([Intel XE#1729] / [Intel XE#7424])
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern.html
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-10/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_vrr@flip-suspend:
    - shard-bmg:          [SKIP][192] ([Intel XE#1499]) -> [SKIP][193] ([Intel XE#6703])
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-bmg-2/igt@kms_vrr@flip-suspend.html
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-2/igt@kms_vrr@flip-suspend.html

  * igt@xe_eudebug_online@stopped-thread:
    - shard-bmg:          [SKIP][194] ([Intel XE#7636]) -> [SKIP][195] ([Intel XE#6703])
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-bmg-9/igt@xe_eudebug_online@stopped-thread.html
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-2/igt@xe_eudebug_online@stopped-thread.html

  * igt@xe_evict@evict-mixed-threads-small-multi-queue:
    - shard-bmg:          [SKIP][196] ([Intel XE#7140]) -> [SKIP][197] ([Intel XE#6703])
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-bmg-6/igt@xe_evict@evict-mixed-threads-small-multi-queue.html
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-2/igt@xe_evict@evict-mixed-threads-small-multi-queue.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic-defer-mmap:
    - shard-bmg:          [SKIP][198] ([Intel XE#2322] / [Intel XE#7372]) -> [SKIP][199] ([Intel XE#6703])
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-bmg-7/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic-defer-mmap.html
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-2/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic-defer-mmap.html

  * igt@xe_exec_multi_queue@two-queues-preempt-mode-fault-priority:
    - shard-bmg:          [SKIP][200] ([Intel XE#6874]) -> [SKIP][201] ([Intel XE#6703]) +1 other test skip
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-bmg-5/igt@xe_exec_multi_queue@two-queues-preempt-mode-fault-priority.html
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-2/igt@xe_exec_multi_queue@two-queues-preempt-mode-fault-priority.html

  * igt@xe_exec_threads@threads-multi-queue-shared-vm-rebind:
    - shard-bmg:          [SKIP][202] ([Intel XE#7138]) -> [SKIP][203] ([Intel XE#6703])
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b/shard-bmg-9/igt@xe_exec_threads@threads-multi-queue-shared-vm-rebind.html
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/shard-bmg-2/igt@xe_exec_threads@threads-multi-queue-shared-vm-rebind.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1125]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1125
  [Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
  [Intel XE#1138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1138
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1420]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1420
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1467]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1467
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#2142]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2142
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2286]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2286
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2328]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2328
  [Intel XE#2330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2330
  [Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2685]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2685
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2838]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2838
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3307
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/352
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
  [Intel XE#4609]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4609
  [Intel XE#4650]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4650
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#5742]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5742
  [Intel XE#5813]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5813
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#6035]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6035
  [Intel XE#6266]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6266
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6376
  [Intel XE#6507]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6507
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#6540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6540
  [Intel XE#6557]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6557
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#6569]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6569
  [Intel XE#6599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6599
  [Intel XE#6703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6703
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
  [Intel XE#7059]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7059
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7085]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7085
  [Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
  [Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
  [Intel XE#7140]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7140
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7304
  [Intel XE#7312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7312
  [Intel XE#7328]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7328
  [Intel XE#7330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7330
  [Intel XE#7340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7340
  [Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342
  [Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
  [Intel XE#7344]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7344
  [Intel XE#7345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7345
  [Intel XE#7347]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7347
  [Intel XE#7349]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7349
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
  [Intel XE#7367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7367
  [Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7400]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7400
  [Intel XE#7405]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7405
  [Intel XE#7417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7417
  [Intel XE#7422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7422
  [Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
  [Intel XE#7442]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7442
  [Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
  [Intel XE#7569]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7569
  [Intel XE#7571]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7571
  [Intel XE#7590]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7590
  [Intel XE#7636]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7636
  [Intel XE#7774]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7774
  [Intel XE#7793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7793
  [Intel XE#7865]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7865
  [Intel XE#7866]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7866
  [Intel XE#7905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7905
  [Intel XE#7915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7915
  [Intel XE#7922]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7922
  [Intel XE#7935]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7935
  [Intel XE#7950]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7950
  [Intel XE#7992]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7992
  [Intel XE#8007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8007
  [Intel XE#8151]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8151


Build changes
-------------

  * IGT: IGT_8940 -> IGT_8941
  * Linux: xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b -> xe-pw-167474v1

  IGT_8940: 656294e257ae4a63e41dbd9d4c11c17ad2543210 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  IGT_8941: 0e365bfe5ccc6d1f7607db10bc21c72d30292cea @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-5144-ad585773b42ab96a2706dc82478e2021fec1a53b: ad585773b42ab96a2706dc82478e2021fec1a53b
  xe-pw-167474v1: 167474v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167474v1/index.html

[-- Attachment #2: Type: text/html, Size: 62819 bytes --]

Re: [PATCH v5 1/4] drm/xe/rtp: Add struct types for RTP tables

[Matt Roper]

On Thu, May 28, 2026 at 09:35:32AM -0700, Violet Monti wrote:
> From: Gustavo Sousa <gustavo.sousa@intel.com>
> 
> We currently have a mixture of styles for our RTP tables with respect of
> how we define the number of entries:
> 
>   * xe_rtp_process_to_sr() expects to receive the number of entries as
>     arguments;
>   * xe_rtp_process() expects the array to have a sentinel at the end of
>     the array;
>   * in xe_rtp_test.c, even though xe_rtp_process_to_sr() does not
>     require a sentinel value, we need to rely on that technique to be
>     able to count xe_rtp_entry_sr entries because simply using
>     ARRAY_SIZE() is not possible.
> 
> The style used by xe_rtp_process_to_sr() makes it hard to share the
> tables with other compilation units (e.g. kunit tests), since the number
> of entries is calculated with ARRAY_SIZE(), which is done at compile
> time.
> 
> Since we use the size of the tables to create some bitmasks, using a
> sentinel style doesn't seem great either.
> 
> A way to reconcile things into a single style is to have a struct type
> that would hold the entries array and the number of entries.  Since we
> have xe_rtp_entry and xe_rtp_entry_sr, we would have one type for each.
> 
> The advantage of the proposed approach is that now we have a nice way to
> share the tables directly to kunit tests with information about their
> size.
> 
> v5:
>     - Remove added code from conflict resolution issues
> 
> v4:
>     - Removed conflicts with main branch
> 
> v3:
>     - No changes
> 
> v2:
>     - Add compatibility with new xe_rtp_table_sr format for
>       "bad-mcr-reg-forced-to-regular" and
>       "bad-regular-reg-forced-to-mcr"
> 
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Violet Monti <violet.monti@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/xe/tests/xe_rtp_test.c | 101 ++++++++++---------------
>  drivers/gpu/drm/xe/xe_hw_engine.c      |  14 ++--
>  drivers/gpu/drm/xe/xe_reg_whitelist.c  |   7 +-
>  drivers/gpu/drm/xe/xe_rtp.c            |  31 ++++----
>  drivers/gpu/drm/xe/xe_rtp.h            |  16 +++-
>  drivers/gpu/drm/xe/xe_rtp_types.h      |  10 +++
>  drivers/gpu/drm/xe/xe_tuning.c         |  45 +++++------
>  drivers/gpu/drm/xe/xe_wa.c             |  89 ++++++++++++----------
>  8 files changed, 156 insertions(+), 157 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/tests/xe_rtp_test.c b/drivers/gpu/drm/xe/tests/xe_rtp_test.c
> index 642f6e090ad0..16bf85033c0c 100644
> --- a/drivers/gpu/drm/xe/tests/xe_rtp_test.c
> +++ b/drivers/gpu/drm/xe/tests/xe_rtp_test.c
> @@ -54,13 +54,13 @@ struct rtp_to_sr_test_case {
>  	unsigned long expected_count_sr_entries;
>  	unsigned int expected_sr_errors;
>  	unsigned long expected_active;
> -	const struct xe_rtp_entry_sr *entries;
> +	const struct xe_rtp_table_sr table;
>  };
>  
>  struct rtp_test_case {
>  	const char *name;
>  	unsigned long expected_active;
> -	const struct xe_rtp_entry *entries;
> +	const struct xe_rtp_table table;
>  };
>  
>  static bool fake_xe_gt_mcr_check_reg(struct xe_gt *gt, struct xe_reg reg)
> @@ -289,7 +289,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  		.expected_active = BIT(0) | BIT(1),
>  		.expected_count_sr_entries = 1,
>  		/* Different bits on the same register: create a single entry */
> -		.entries = (const struct xe_rtp_entry_sr[]) {
> +		.table = XE_RTP_TABLE_SR(
>  			{ XE_RTP_NAME("basic-1"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
> @@ -298,8 +298,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1)))
>  			},
> -			{}
> -		},
> +		),
>  	},
>  	{
>  		.name = "no-match-no-add",
> @@ -309,7 +308,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  		.expected_active = BIT(0),
>  		.expected_count_sr_entries = 1,
>  		/* Don't coalesce second entry since rules don't match */
> -		.entries = (const struct xe_rtp_entry_sr[]) {
> +		.table = XE_RTP_TABLE_SR(
>  			{ XE_RTP_NAME("basic-1"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
> @@ -318,8 +317,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  			  XE_RTP_RULES(FUNC(match_no)),
>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1)))
>  			},
> -			{}
> -		},
> +		),
>  	},
>  	{
>  		.name = "two-regs-two-entries",
> @@ -329,7 +327,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  		.expected_active = BIT(0) | BIT(1),
>  		.expected_count_sr_entries = 2,
>  		/* Same bits on different registers are not coalesced */
> -		.entries = (const struct xe_rtp_entry_sr[]) {
> +		.table = XE_RTP_TABLE_SR(
>  			{ XE_RTP_NAME("basic-1"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
> @@ -338,8 +336,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(SET(REGULAR_REG2, REG_BIT(0)))
>  			},
> -			{}
> -		},
> +		),
>  	},
>  	{
>  		.name = "clr-one-set-other",
> @@ -349,7 +346,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  		.expected_active = BIT(0) | BIT(1),
>  		.expected_count_sr_entries = 1,
>  		/* Check clr vs set actions on different bits */
> -		.entries = (const struct xe_rtp_entry_sr[]) {
> +		.table = XE_RTP_TABLE_SR(
>  			{ XE_RTP_NAME("basic-1"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
> @@ -358,8 +355,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(CLR(REGULAR_REG1, REG_BIT(1)))
>  			},
> -			{}
> -		},
> +		),
>  	},
>  	{
>  #define TEMP_MASK	REG_GENMASK(10, 8)
> @@ -371,14 +367,13 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  		.expected_active = BIT(0),
>  		.expected_count_sr_entries = 1,
>  		/* Check FIELD_SET works */
> -		.entries = (const struct xe_rtp_entry_sr[]) {
> +		.table = XE_RTP_TABLE_SR(
>  			{ XE_RTP_NAME("basic-1"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(FIELD_SET(REGULAR_REG1,
>  						   TEMP_MASK, TEMP_FIELD))
>  			},
> -			{}
> -		},
> +		),
>  #undef TEMP_MASK
>  #undef TEMP_FIELD
>  	},
> @@ -390,7 +385,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  		.expected_active = BIT(0) | BIT(1),
>  		.expected_count_sr_entries = 1,
>  		.expected_sr_errors = 1,
> -		.entries = (const struct xe_rtp_entry_sr[]) {
> +		.table = XE_RTP_TABLE_SR(
>  			{ XE_RTP_NAME("basic-1"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
> @@ -400,8 +395,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
>  			},
> -			{}
> -		},
> +		),
>  	},
>  	{
>  		.name = "conflict-not-disjoint",
> @@ -411,7 +405,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  		.expected_active = BIT(0) | BIT(1),
>  		.expected_count_sr_entries = 1,
>  		.expected_sr_errors = 1,
> -		.entries = (const struct xe_rtp_entry_sr[]) {
> +		.table = XE_RTP_TABLE_SR(
>  			{ XE_RTP_NAME("basic-1"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
> @@ -421,8 +415,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(CLR(REGULAR_REG1, REG_GENMASK(1, 0)))
>  			},
> -			{}
> -		},
> +		),
>  	},
>  	{
>  		.name = "conflict-reg-type",
> @@ -432,7 +425,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  		.expected_active = BIT(0) | BIT(1) | BIT(2),
>  		.expected_count_sr_entries = 1,
>  		.expected_sr_errors = 2,
> -		.entries = (const struct xe_rtp_entry_sr[]) {
> +		.table = XE_RTP_TABLE_SR(
>  			{ XE_RTP_NAME("basic-1"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
> @@ -447,8 +440,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(SET(MASKED_REG1, REG_BIT(0)))
>  			},
> -			{}
> -		},
> +		),
>  	},
>  	{
>  		.name = "bad-mcr-reg-forced-to-regular",
> @@ -458,13 +450,13 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  		.expected_active = BIT(0),
>  		.expected_count_sr_entries = 1,
>  		.expected_sr_errors = 1,
> -		.entries = (const struct xe_rtp_entry_sr[]) {
> +		.table = XE_RTP_TABLE_SR(
>  			{ XE_RTP_NAME("bad-mcr-regular-reg"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(SET(BAD_MCR_REG4, REG_BIT(0)))
>  			},
>  			{}
> -		},
> +		),
>  	},
>  	{
>  		.name = "bad-regular-reg-forced-to-mcr",
> @@ -474,13 +466,13 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  		.expected_active = BIT(0),
>  		.expected_count_sr_entries = 1,
>  		.expected_sr_errors = 1,
> -		.entries = (const struct xe_rtp_entry_sr[]) {
> +		.table = XE_RTP_TABLE_SR(
>  			{ XE_RTP_NAME("bad-regular-reg"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(SET(BAD_REGULAR_REG5, REG_BIT(0)))
>  			},
>  			{}
> -		},
> +		),
>  	},
>  };
>  
> @@ -492,16 +484,12 @@ static void xe_rtp_process_to_sr_tests(struct kunit *test)
>  	struct xe_reg_sr *reg_sr = &gt->reg_sr;
>  	const struct xe_reg_sr_entry *sre, *sr_entry = NULL;
>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
> -	unsigned long idx, count_sr_entries = 0, count_rtp_entries = 0, active = 0;
> +	unsigned long idx, count_sr_entries = 0, active = 0;
>  
>  	xe_reg_sr_init(reg_sr, "xe_rtp_to_sr_tests", xe);
>  
> -	while (param->entries[count_rtp_entries].rules)
> -		count_rtp_entries++;
> -
> -	xe_rtp_process_ctx_enable_active_tracking(&ctx, &active, count_rtp_entries);
> -	xe_rtp_process_to_sr(&ctx, param->entries, count_rtp_entries,
> -			     reg_sr, false);
> +	xe_rtp_process_ctx_enable_active_tracking(&ctx, &active, param->table.n_entries);
> +	xe_rtp_process_to_sr(&ctx, &param->table, reg_sr, false);
>  
>  	xa_for_each(&reg_sr->xa, idx, sre) {
>  		if (idx == param->expected_reg.addr)
> @@ -534,56 +522,52 @@ static const struct rtp_test_case rtp_cases[] = {
>  	{
>  		.name = "active1",
>  		.expected_active = BIT(0),
> -		.entries = (const struct xe_rtp_entry[]) {
> +		.table = XE_RTP_TABLE(
>  			{ XE_RTP_NAME("r1"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			},
> -			{}
> -		},
> +		),
>  	},
>  	{
>  		.name = "active2",
>  		.expected_active = BIT(0) | BIT(1),
> -		.entries = (const struct xe_rtp_entry[]) {
> +		.table = XE_RTP_TABLE(
>  			{ XE_RTP_NAME("r1"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			},
>  			{ XE_RTP_NAME("r2"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			},
> -			{}
> -		},
> +		),
>  	},
>  	{
>  		.name = "active-inactive",
>  		.expected_active = BIT(0),
> -		.entries = (const struct xe_rtp_entry[]) {
> +		.table = XE_RTP_TABLE(
>  			{ XE_RTP_NAME("r1"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			},
>  			{ XE_RTP_NAME("r2"),
>  			  XE_RTP_RULES(FUNC(match_no)),
>  			},
> -			{}
> -		},
> +		),
>  	},
>  	{
>  		.name = "inactive-active",
>  		.expected_active = BIT(1),
> -		.entries = (const struct xe_rtp_entry[]) {
> +		.table = XE_RTP_TABLE(
>  			{ XE_RTP_NAME("r1"),
>  			  XE_RTP_RULES(FUNC(match_no)),
>  			},
>  			{ XE_RTP_NAME("r2"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			},
> -			{}
> -		},
> +		),
>  	},
>  	{
>  		.name = "inactive-active-inactive",
>  		.expected_active = BIT(1),
> -		.entries = (const struct xe_rtp_entry[]) {
> +		.table = XE_RTP_TABLE(
>  			{ XE_RTP_NAME("r1"),
>  			  XE_RTP_RULES(FUNC(match_no)),
>  			},
> @@ -593,13 +577,12 @@ static const struct rtp_test_case rtp_cases[] = {
>  			{ XE_RTP_NAME("r3"),
>  			  XE_RTP_RULES(FUNC(match_no)),
>  			},
> -			{}
> -		},
> +		),
>  	},
>  	{
>  		.name = "inactive-inactive-inactive",
>  		.expected_active = 0,
> -		.entries = (const struct xe_rtp_entry[]) {
> +		.table = XE_RTP_TABLE(
>  			{ XE_RTP_NAME("r1"),
>  			  XE_RTP_RULES(FUNC(match_no)),
>  			},
> @@ -609,8 +592,7 @@ static const struct rtp_test_case rtp_cases[] = {
>  			{ XE_RTP_NAME("r3"),
>  			  XE_RTP_RULES(FUNC(match_no)),
>  			},
> -			{}
> -		},
> +		),
>  	},
>  };
>  
> @@ -620,13 +602,10 @@ static void xe_rtp_process_tests(struct kunit *test)
>  	struct xe_device *xe = test->priv;
>  	struct xe_gt *gt = xe_device_get_root_tile(xe)->primary_gt;
>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
> -	unsigned long count_rtp_entries = 0, active = 0;
> -
> -	while (param->entries[count_rtp_entries].rules)
> -		count_rtp_entries++;
> +	unsigned long active = 0;
>  
> -	xe_rtp_process_ctx_enable_active_tracking(&ctx, &active, count_rtp_entries);
> -	xe_rtp_process(&ctx, param->entries);
> +	xe_rtp_process_ctx_enable_active_tracking(&ctx, &active, param->table.n_entries);
> +	xe_rtp_process(&ctx, &param->table);
>  
>  	KUNIT_EXPECT_EQ(test, active, param->expected_active);
>  }
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index 8c66ff6f3d3c..98265293f2dc 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -346,7 +346,7 @@ hw_engine_setup_default_lrc_state(struct xe_hw_engine *hwe)
>  	u32 blit_cctl_val = REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, mocs_write_idx) |
>  			    REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, mocs_read_idx);
>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
> -	const struct xe_rtp_entry_sr lrc_setup[] = {
> +	const struct xe_rtp_table_sr lrc_setup = XE_RTP_TABLE_SR(
>  		/*
>  		 * Some blitter commands do not have a field for MOCS, those
>  		 * commands will use MOCS index pointed by BLIT_CCTL.
> @@ -369,10 +369,9 @@ hw_engine_setup_default_lrc_state(struct xe_hw_engine *hwe)
>  					   PREEMPT_GPGPU_THREAD_GROUP_LEVEL)),
>  		  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE)
>  		},
> -	};
> +	);
>  
> -	xe_rtp_process_to_sr(&ctx, lrc_setup, ARRAY_SIZE(lrc_setup),
> -			     &hwe->reg_lrc, true);
> +	xe_rtp_process_to_sr(&ctx, &lrc_setup, &hwe->reg_lrc, true);
>  }
>  
>  void xe_hw_engine_setup_reg_lrc(struct xe_hw_engine *hwe)
> @@ -408,7 +407,7 @@ hw_engine_setup_default_state(struct xe_hw_engine *hwe)
>  	u32 ring_cmd_cctl_val = REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, mocs_write_idx) |
>  				REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, mocs_read_idx);
>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
> -	const struct xe_rtp_entry_sr engine_entries[] = {
> +	const struct xe_rtp_table_sr engine_sr = XE_RTP_TABLE_SR(
>  		{ XE_RTP_NAME("RING_CMD_CCTL_default_MOCS"),
>  		  XE_RTP_RULES(FUNC(xe_rtp_match_always)),
>  		  XE_RTP_ACTIONS(FIELD_SET(RING_CMD_CCTL(0),
> @@ -465,10 +464,9 @@ hw_engine_setup_default_state(struct xe_hw_engine *hwe)
>  		  XE_RTP_ACTIONS(SET(GFX_MODE(0), GFX_MSIX_INTERRUPT_ENABLE,
>  				     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
>  		},
> -	};
> +	);
>  
> -	xe_rtp_process_to_sr(&ctx, engine_entries, ARRAY_SIZE(engine_entries),
> -			     &hwe->reg_sr, false);
> +	xe_rtp_process_to_sr(&ctx, &engine_sr, &hwe->reg_sr, false);
>  }
>  
>  static const struct engine_info *find_engine_info(enum xe_engine_class class, int instance)
> diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> index fb65940848d7..2e84b1c49f37 100644
> --- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
> +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> @@ -41,7 +41,7 @@ static bool match_multi_queue_class(const struct xe_device *xe,
>  	return xe_gt_supports_multi_queue(gt, hwe->class);
>  }
>  
> -static const struct xe_rtp_entry_sr register_whitelist[] = {
> +static const struct xe_rtp_table_sr register_whitelist = XE_RTP_TABLE_SR(
>  	{ XE_RTP_NAME("WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865"),
>  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
>  	  XE_RTP_ACTIONS(WHITELIST(PS_INVOCATION_COUNT,
> @@ -154,7 +154,7 @@ static const struct xe_rtp_entry_sr register_whitelist[] = {
>  	  XE_RTP_RULES(FUNC(match_has_mert), ENGINE_CLASS(COPY)),
>  	  XE_RTP_ACTIONS(WHITELIST_OA_MERT_MMIO_TRG)
>  	},
> -};
> +);
>  
>  static void whitelist_apply_to_hwe(struct xe_hw_engine *hwe)
>  {
> @@ -202,8 +202,7 @@ void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe)
>  {
>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
>  
> -	xe_rtp_process_to_sr(&ctx, register_whitelist, ARRAY_SIZE(register_whitelist),
> -			     &hwe->reg_whitelist, false);
> +	xe_rtp_process_to_sr(&ctx, &register_whitelist, &hwe->reg_whitelist, false);
>  	whitelist_apply_to_hwe(hwe);
>  }
>  
> diff --git a/drivers/gpu/drm/xe/xe_rtp.c b/drivers/gpu/drm/xe/xe_rtp.c
> index dec9d94e6fb0..83a40e1f9528 100644
> --- a/drivers/gpu/drm/xe/xe_rtp.c
> +++ b/drivers/gpu/drm/xe/xe_rtp.c
> @@ -326,8 +326,7 @@ static void rtp_mark_active(struct xe_device *xe,
>   * xe_rtp_process_to_sr - Process all rtp @entries, adding the matching ones to
>   *                        the save-restore argument.
>   * @ctx: The context for processing the table, with one of device, gt or hwe
> - * @entries: Table with RTP definitions
> - * @n_entries: Number of entries to process, usually ARRAY_SIZE(entries)
> + * @table: Table with RTP definitions
>   * @sr: Save-restore struct where matching rules execute the action. This can be
>   *      viewed as the "coalesced view" of multiple the tables. The bits for each
>   *      register set are expected not to collide with previously added entries
> @@ -339,12 +338,10 @@ static void rtp_mark_active(struct xe_device *xe,
>   * used to calculate the right register offset
>   */
>  void xe_rtp_process_to_sr(struct xe_rtp_process_ctx *ctx,
> -			  const struct xe_rtp_entry_sr *entries,
> -			  size_t n_entries,
> +			  const struct xe_rtp_table_sr *table,
>  			  struct xe_reg_sr *sr,
>  			  bool process_in_vf)
>  {
> -	const struct xe_rtp_entry_sr *entry;
>  	struct xe_hw_engine *hwe = NULL;
>  	struct xe_gt *gt = NULL;
>  	struct xe_device *xe = NULL;
> @@ -354,9 +351,10 @@ void xe_rtp_process_to_sr(struct xe_rtp_process_ctx *ctx,
>  	if (!process_in_vf && IS_SRIOV_VF(xe))
>  		return;
>  
> -	xe_assert(xe, entries);
> +	xe_assert(xe, table->entries);
>  
> -	for (entry = entries; entry - entries < n_entries; entry++) {
> +	for (size_t i = 0; i < table->n_entries; i++) {
> +		const struct xe_rtp_entry_sr *entry = &table->entries[i];
>  		bool match = false;
>  
>  		if (entry->flags & XE_RTP_ENTRY_FLAG_FOREACH_ENGINE) {
> @@ -371,37 +369,40 @@ void xe_rtp_process_to_sr(struct xe_rtp_process_ctx *ctx,
>  		}
>  
>  		if (match)
> -			rtp_mark_active(xe, ctx, entry - entries);
> +			rtp_mark_active(xe, ctx, i);
>  	}
>  }
>  EXPORT_SYMBOL_IF_KUNIT(xe_rtp_process_to_sr);
>  
>  /**
> - * xe_rtp_process - Process all rtp @entries, without running any action
> + * xe_rtp_process - Process all entries in rtp @table, without running any action
>   * @ctx: The context for processing the table, with one of device, gt or hwe
> - * @entries: Table with RTP definitions
> + * @table: Table with RTP definitions
>   *
> - * Walk the table pointed by @entries (with an empty sentinel), executing the
> + * Walk the table pointed by @table, executing the
>   * rules. One difference from xe_rtp_process_to_sr(): there is no action
>   * associated with each entry since this uses struct xe_rtp_entry. Its main use
>   * is for marking active workarounds via
>   * xe_rtp_process_ctx_enable_active_tracking().
>   */
>  void xe_rtp_process(struct xe_rtp_process_ctx *ctx,
> -		    const struct xe_rtp_entry *entries)
> +		    const struct xe_rtp_table *table)
>  {
> -	const struct xe_rtp_entry *entry;
>  	struct xe_hw_engine *hwe;
>  	struct xe_gt *gt;
>  	struct xe_device *xe;
>  
>  	rtp_get_context(ctx, &hwe, &gt, &xe);
>  
> -	for (entry = entries; entry && entry->rules; entry++) {
> +	xe_assert(xe, table->entries);
> +
> +	for (size_t i = 0; i < table->n_entries; i++) {
> +		const struct xe_rtp_entry *entry = &table->entries[i];
> +
>  		if (!rule_matches(xe, gt, hwe, entry->rules, entry->n_rules))
>  			continue;
>  
> -		rtp_mark_active(xe, ctx, entry - entries);
> +		rtp_mark_active(xe, ctx, i);
>  	}
>  }
>  EXPORT_SYMBOL_IF_KUNIT(xe_rtp_process);
> diff --git a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h
> index e4f1930ca1c3..4e3cfd69f922 100644
> --- a/drivers/gpu/drm/xe/xe_rtp.h
> +++ b/drivers/gpu/drm/xe/xe_rtp.h
> @@ -461,6 +461,16 @@ struct xe_reg_sr;
>  		XE_RTP_PASTE_FOREACH(ACTION_, COMMA, (__VA_ARGS__))	\
>  	}
>  
> +#define XE_RTP_TABLE_SR(...) { \
> +	.entries = (const struct xe_rtp_entry_sr[]){__VA_ARGS__}, \
> +	.n_entries = ARRAY_SIZE(((const struct xe_rtp_entry_sr[]){__VA_ARGS__})), \
> +}
> +
> +#define XE_RTP_TABLE(...) { \
> +	.entries = (const struct xe_rtp_entry[]){__VA_ARGS__}, \
> +	.n_entries = ARRAY_SIZE(((const struct xe_rtp_entry[]){__VA_ARGS__})), \
> +}
> +
>  #define XE_RTP_PROCESS_CTX_INITIALIZER(arg__) _Generic((arg__),							\
>  	struct xe_hw_engine * :	(struct xe_rtp_process_ctx){ { (void *)(arg__) }, XE_RTP_PROCESS_TYPE_ENGINE },	\
>  	struct xe_gt * :	(struct xe_rtp_process_ctx){ { (void *)(arg__) }, XE_RTP_PROCESS_TYPE_GT },	\
> @@ -471,12 +481,12 @@ void xe_rtp_process_ctx_enable_active_tracking(struct xe_rtp_process_ctx *ctx,
>  					       size_t n_entries);
>  
>  void xe_rtp_process_to_sr(struct xe_rtp_process_ctx *ctx,
> -			  const struct xe_rtp_entry_sr *entries,
> -			  size_t n_entries, struct xe_reg_sr *sr,
> +			  const struct xe_rtp_table_sr *table,
> +			  struct xe_reg_sr *sr,
>  			  bool process_in_vf);
>  
>  void xe_rtp_process(struct xe_rtp_process_ctx *ctx,
> -		    const struct xe_rtp_entry *entries);
> +		    const struct xe_rtp_table *table);
>  
>  /* Match functions to be used with XE_RTP_MATCH_FUNC */
>  
> diff --git a/drivers/gpu/drm/xe/xe_rtp_types.h b/drivers/gpu/drm/xe/xe_rtp_types.h
> index 0265c16d2762..58018ae4f8cc 100644
> --- a/drivers/gpu/drm/xe/xe_rtp_types.h
> +++ b/drivers/gpu/drm/xe/xe_rtp_types.h
> @@ -112,6 +112,16 @@ struct xe_rtp_entry {
>  	u8 n_rules;
>  };
>  
> +struct xe_rtp_table_sr {
> +	const struct xe_rtp_entry_sr *entries;
> +	size_t n_entries;
> +};
> +
> +struct xe_rtp_table {
> +	const struct xe_rtp_entry *entries;
> +	size_t n_entries;
> +};
> +
>  enum xe_rtp_process_type {
>  	XE_RTP_PROCESS_TYPE_DEVICE,
>  	XE_RTP_PROCESS_TYPE_GT,
> diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
> index 9a1b3862e192..bf3fad9cdbef 100644
> --- a/drivers/gpu/drm/xe/xe_tuning.c
> +++ b/drivers/gpu/drm/xe/xe_tuning.c
> @@ -20,7 +20,7 @@
>  #undef XE_REG_MCR
>  #define XE_REG_MCR(...)     XE_REG(__VA_ARGS__, .mcr = 1)
>  
> -static const struct xe_rtp_entry_sr gt_tunings[] = {
> +static const struct xe_rtp_table_sr gt_tunings = XE_RTP_TABLE_SR(
>  	{ XE_RTP_NAME("Tuning: Blend Fill Caching Optimization Disable"),
>  	  XE_RTP_RULES(PLATFORM(DG2)),
>  	  XE_RTP_ACTIONS(SET(XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS))
> @@ -100,9 +100,9 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
>  	  XE_RTP_ACTIONS(FIELD_SET(GAMSTLB_CTRL, BANK_HASH_MODE,
>  				   BANK_HASH_4KB_MODE))
>  	},
> -};
> +);
>  
> -static const struct xe_rtp_entry_sr engine_tunings[] = {
> +static const struct xe_rtp_table_sr engine_tunings = XE_RTP_TABLE_SR(
>  	{ XE_RTP_NAME("Tuning: L3 Hashing Mask"),
>  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210),
>  		       FUNC(xe_rtp_match_first_render_or_compute)),
> @@ -129,9 +129,9 @@ static const struct xe_rtp_entry_sr engine_tunings[] = {
>  		       FUNC(xe_rtp_match_first_render_or_compute)),
>  	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN2, TILEY_LOCALID))
>  	},
> -};
> +);
>  
> -static const struct xe_rtp_entry_sr lrc_tunings[] = {
> +static const struct xe_rtp_table_sr lrc_tunings = XE_RTP_TABLE_SR(
>  	{ XE_RTP_NAME("Tuning: Windower HW Filtering"),
>  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3599), ENGINE_CLASS(RENDER)),
>  	  XE_RTP_ACTIONS(SET(XEHP_COMMON_SLICE_CHICKEN4, HW_FILTERING))
> @@ -171,7 +171,7 @@ static const struct xe_rtp_entry_sr lrc_tunings[] = {
>  	  XE_RTP_ACTIONS(FIELD_SET(FF_MODE, VS_HIT_MAX_VALUE_MASK,
>  				   REG_FIELD_PREP(VS_HIT_MAX_VALUE_MASK, 0x3f)))
>  	},
> -};
> +);
>  
>  /**
>   * xe_tuning_init - initialize gt with tunings bookkeeping
> @@ -185,9 +185,9 @@ int xe_tuning_init(struct xe_gt *gt)
>  	size_t n_lrc, n_engine, n_gt, total;
>  	unsigned long *p;
>  
> -	n_gt = BITS_TO_LONGS(ARRAY_SIZE(gt_tunings));
> -	n_engine = BITS_TO_LONGS(ARRAY_SIZE(engine_tunings));
> -	n_lrc = BITS_TO_LONGS(ARRAY_SIZE(lrc_tunings));
> +	n_gt = BITS_TO_LONGS(gt_tunings.n_entries);
> +	n_engine = BITS_TO_LONGS(engine_tunings.n_entries);
> +	n_lrc = BITS_TO_LONGS(lrc_tunings.n_entries);
>  	total = n_gt + n_engine + n_lrc;
>  
>  	p = drmm_kzalloc(&xe->drm, sizeof(*p) * total, GFP_KERNEL);
> @@ -210,9 +210,8 @@ void xe_tuning_process_gt(struct xe_gt *gt)
>  
>  	xe_rtp_process_ctx_enable_active_tracking(&ctx,
>  						  gt->tuning_active.gt,
> -						  ARRAY_SIZE(gt_tunings));
> -	xe_rtp_process_to_sr(&ctx, gt_tunings, ARRAY_SIZE(gt_tunings),
> -			     &gt->reg_sr, false);
> +						  gt_tunings.n_entries);
> +	xe_rtp_process_to_sr(&ctx, &gt_tunings, &gt->reg_sr, false);
>  }
>  EXPORT_SYMBOL_IF_KUNIT(xe_tuning_process_gt);
>  
> @@ -222,9 +221,8 @@ void xe_tuning_process_engine(struct xe_hw_engine *hwe)
>  
>  	xe_rtp_process_ctx_enable_active_tracking(&ctx,
>  						  hwe->gt->tuning_active.engine,
> -						  ARRAY_SIZE(engine_tunings));
> -	xe_rtp_process_to_sr(&ctx, engine_tunings, ARRAY_SIZE(engine_tunings),
> -			     &hwe->reg_sr, false);
> +						  engine_tunings.n_entries);
> +	xe_rtp_process_to_sr(&ctx, &engine_tunings, &hwe->reg_sr, false);
>  }
>  EXPORT_SYMBOL_IF_KUNIT(xe_tuning_process_engine);
>  
> @@ -242,9 +240,8 @@ void xe_tuning_process_lrc(struct xe_hw_engine *hwe)
>  
>  	xe_rtp_process_ctx_enable_active_tracking(&ctx,
>  						  hwe->gt->tuning_active.lrc,
> -						  ARRAY_SIZE(lrc_tunings));
> -	xe_rtp_process_to_sr(&ctx, lrc_tunings, ARRAY_SIZE(lrc_tunings),
> -			     &hwe->reg_lrc, true);
> +						  lrc_tunings.n_entries);
> +	xe_rtp_process_to_sr(&ctx, &lrc_tunings, &hwe->reg_lrc, true);
>  }
>  
>  /**
> @@ -259,18 +256,18 @@ int xe_tuning_dump(struct xe_gt *gt, struct drm_printer *p)
>  	size_t idx;
>  
>  	drm_printf(p, "GT Tunings\n");
> -	for_each_set_bit(idx, gt->tuning_active.gt, ARRAY_SIZE(gt_tunings))
> -		drm_printf_indent(p, 1, "%s\n", gt_tunings[idx].name);
> +	for_each_set_bit(idx, gt->tuning_active.gt, gt_tunings.n_entries)
> +		drm_printf_indent(p, 1, "%s\n", gt_tunings.entries[idx].name);
>  
>  	drm_puts(p, "\n");
>  	drm_printf(p, "Engine Tunings\n");
> -	for_each_set_bit(idx, gt->tuning_active.engine, ARRAY_SIZE(engine_tunings))
> -		drm_printf_indent(p, 1, "%s\n", engine_tunings[idx].name);
> +	for_each_set_bit(idx, gt->tuning_active.engine, engine_tunings.n_entries)
> +		drm_printf_indent(p, 1, "%s\n", engine_tunings.entries[idx].name);
>  
>  	drm_puts(p, "\n");
>  	drm_printf(p, "LRC Tunings\n");
> -	for_each_set_bit(idx, gt->tuning_active.lrc, ARRAY_SIZE(lrc_tunings))
> -		drm_printf_indent(p, 1, "%s\n", lrc_tunings[idx].name);
> +	for_each_set_bit(idx, gt->tuning_active.lrc, lrc_tunings.n_entries)
> +		drm_printf_indent(p, 1, "%s\n", lrc_tunings.entries[idx].name);
>  
>  	return 0;
>  }
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index cb811f8a7781..b9d9fe0801aa 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -130,7 +130,7 @@
>  __diag_push();
>  __diag_ignore_all("-Woverride-init", "Allow field overrides in table");
>  
> -static const struct xe_rtp_entry_sr gt_was[] = {
> +static const struct xe_rtp_table_sr gt_was = XE_RTP_TABLE_SR(
>  	/* Workarounds applying over a range of IPs */
>  
>  	{ XE_RTP_NAME("14011060649"),
> @@ -306,9 +306,9 @@ static const struct xe_rtp_entry_sr gt_was[] = {
>  	  XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
>  	  XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
>  	},
> -};
> +);
>  
> -static const struct xe_rtp_entry_sr engine_was[] = {
> +static const struct xe_rtp_table_sr engine_was = XE_RTP_TABLE_SR(
>  	/* Workarounds applying over a range of IPs */
>  
>  	{ XE_RTP_NAME("22010931296, 18011464164, 14010919138"),
> @@ -614,9 +614,9 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  		       FUNC(xe_rtp_match_first_render_or_compute)),
>  	  XE_RTP_ACTIONS(SET(TDL_CHICKEN, BIT_APQ_OPT_DIS))
>  	},
> -};
> +);
>  
> -static const struct xe_rtp_entry_sr lrc_was[] = {
> +static const struct xe_rtp_table_sr lrc_was = XE_RTP_TABLE_SR(
>  	{ XE_RTP_NAME("16011163337"),
>  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
>  	  /* read verification is ignored due to 1608008084. */
> @@ -794,21 +794,29 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
>  		       ENGINE_CLASS(RENDER)),
>  	  XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX))
>  	},
> -};
> +);
>  
> -static __maybe_unused const struct xe_rtp_entry oob_was[] = {
> +static const struct xe_rtp_entry oob_was_entries[] = {
>  #include <generated/xe_wa_oob.c>
> -	{}
>  };
>  
> -static_assert(ARRAY_SIZE(oob_was) - 1 == _XE_WA_OOB_COUNT);
> +static_assert(ARRAY_SIZE(oob_was_entries)  == _XE_WA_OOB_COUNT);
>  
> -static __maybe_unused const struct xe_rtp_entry device_oob_was[] = {
> +static __maybe_unused const struct xe_rtp_table oob_was = {
> +	.entries = oob_was_entries,
> +	.n_entries = ARRAY_SIZE(oob_was_entries),
> +};
> +
> +static const struct xe_rtp_entry device_oob_was_entries[] = {
>  #include <generated/xe_device_wa_oob.c>
> -	{}
>  };
>  
> -static_assert(ARRAY_SIZE(device_oob_was) - 1 == _XE_DEVICE_WA_OOB_COUNT);
> +static_assert(ARRAY_SIZE(device_oob_was_entries) == _XE_DEVICE_WA_OOB_COUNT);
> +
> +static __maybe_unused const struct xe_rtp_table device_oob_was = {
> +	.entries = device_oob_was_entries,
> +	.n_entries = ARRAY_SIZE(device_oob_was_entries),
> +};
>  
>  __diag_pop();
>  
> @@ -824,10 +832,10 @@ void xe_wa_process_device_oob(struct xe_device *xe)
>  {
>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(xe);
>  
> -	xe_rtp_process_ctx_enable_active_tracking(&ctx, xe->wa_active.oob, ARRAY_SIZE(device_oob_was));
> +	xe_rtp_process_ctx_enable_active_tracking(&ctx, xe->wa_active.oob, device_oob_was.n_entries);
>  
>  	xe->wa_active.oob_initialized = true;
> -	xe_rtp_process(&ctx, device_oob_was);
> +	xe_rtp_process(&ctx, &device_oob_was);
>  }
>  
>  /**
> @@ -842,9 +850,9 @@ void xe_wa_process_gt_oob(struct xe_gt *gt)
>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
>  
>  	xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.oob,
> -						  ARRAY_SIZE(oob_was));
> +						  oob_was.n_entries);
>  	gt->wa_active.oob_initialized = true;
> -	xe_rtp_process(&ctx, oob_was);
> +	xe_rtp_process(&ctx, &oob_was);
>  }
>  
>  /**
> @@ -859,9 +867,8 @@ void xe_wa_process_gt(struct xe_gt *gt)
>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
>  
>  	xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.gt,
> -						  ARRAY_SIZE(gt_was));
> -	xe_rtp_process_to_sr(&ctx, gt_was, ARRAY_SIZE(gt_was),
> -			     &gt->reg_sr, false);
> +						  gt_was.n_entries);
> +	xe_rtp_process_to_sr(&ctx, &gt_was, &gt->reg_sr, false);
>  }
>  EXPORT_SYMBOL_IF_KUNIT(xe_wa_process_gt);
>  
> @@ -878,9 +885,8 @@ void xe_wa_process_engine(struct xe_hw_engine *hwe)
>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
>  
>  	xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.engine,
> -						  ARRAY_SIZE(engine_was));
> -	xe_rtp_process_to_sr(&ctx, engine_was, ARRAY_SIZE(engine_was),
> -			     &hwe->reg_sr, false);
> +						  engine_was.n_entries);
> +	xe_rtp_process_to_sr(&ctx, &engine_was, &hwe->reg_sr, false);
>  }
>  
>  /**
> @@ -896,9 +902,8 @@ void xe_wa_process_lrc(struct xe_hw_engine *hwe)
>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
>  
>  	xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.lrc,
> -						  ARRAY_SIZE(lrc_was));
> -	xe_rtp_process_to_sr(&ctx, lrc_was, ARRAY_SIZE(lrc_was),
> -			     &hwe->reg_lrc, true);
> +						  lrc_was.n_entries);
> +	xe_rtp_process_to_sr(&ctx, &lrc_was, &hwe->reg_lrc, true);
>  }
>  
>  /**
> @@ -912,7 +917,7 @@ int xe_wa_device_init(struct xe_device *xe)
>  	unsigned long *p;
>  
>  	p = drmm_kzalloc(&xe->drm,
> -			 sizeof(*p) * BITS_TO_LONGS(ARRAY_SIZE(device_oob_was)),
> +			 sizeof(*p) * BITS_TO_LONGS(device_oob_was.n_entries),
>  			 GFP_KERNEL);
>  
>  	if (!p)
> @@ -935,10 +940,10 @@ int xe_wa_gt_init(struct xe_gt *gt)
>  	size_t n_oob, n_lrc, n_engine, n_gt, total;
>  	unsigned long *p;
>  
> -	n_gt = BITS_TO_LONGS(ARRAY_SIZE(gt_was));
> -	n_engine = BITS_TO_LONGS(ARRAY_SIZE(engine_was));
> -	n_lrc = BITS_TO_LONGS(ARRAY_SIZE(lrc_was));
> -	n_oob = BITS_TO_LONGS(ARRAY_SIZE(oob_was));
> +	n_gt = BITS_TO_LONGS(gt_was.n_entries);
> +	n_engine = BITS_TO_LONGS(engine_was.n_entries);
> +	n_lrc = BITS_TO_LONGS(lrc_was.n_entries);
> +	n_oob = BITS_TO_LONGS(oob_was.n_entries);
>  	total = n_gt + n_engine + n_lrc + n_oob;
>  
>  	p = drmm_kzalloc(&xe->drm, sizeof(*p) * total, GFP_KERNEL);
> @@ -962,9 +967,9 @@ void xe_wa_device_dump(struct xe_device *xe, struct drm_printer *p)
>  	size_t idx;
>  
>  	drm_printf(p, "Device OOB Workarounds\n");
> -	for_each_set_bit(idx, xe->wa_active.oob, ARRAY_SIZE(device_oob_was))
> -		if (device_oob_was[idx].name)
> -			drm_printf_indent(p, 1, "%s\n", device_oob_was[idx].name);
> +	for_each_set_bit(idx, xe->wa_active.oob, device_oob_was.n_entries)
> +		if (device_oob_was.entries[idx].name)
> +			drm_printf_indent(p, 1, "%s\n", device_oob_was.entries[idx].name);
>  }
>  
>  /**
> @@ -979,24 +984,24 @@ int xe_wa_gt_dump(struct xe_gt *gt, struct drm_printer *p)
>  	size_t idx;
>  
>  	drm_printf(p, "GT Workarounds\n");
> -	for_each_set_bit(idx, gt->wa_active.gt, ARRAY_SIZE(gt_was))
> -		drm_printf_indent(p, 1, "%s\n", gt_was[idx].name);
> +	for_each_set_bit(idx, gt->wa_active.gt, gt_was.n_entries)
> +		drm_printf_indent(p, 1, "%s\n", gt_was.entries[idx].name);
>  
>  	drm_puts(p, "\n");
>  	drm_printf(p, "Engine Workarounds\n");
> -	for_each_set_bit(idx, gt->wa_active.engine, ARRAY_SIZE(engine_was))
> -		drm_printf_indent(p, 1, "%s\n", engine_was[idx].name);
> +	for_each_set_bit(idx, gt->wa_active.engine, engine_was.n_entries)
> +		drm_printf_indent(p, 1, "%s\n", engine_was.entries[idx].name);
>  
>  	drm_puts(p, "\n");
>  	drm_printf(p, "LRC Workarounds\n");
> -	for_each_set_bit(idx, gt->wa_active.lrc, ARRAY_SIZE(lrc_was))
> -		drm_printf_indent(p, 1, "%s\n", lrc_was[idx].name);
> +	for_each_set_bit(idx, gt->wa_active.lrc, lrc_was.n_entries)
> +		drm_printf_indent(p, 1, "%s\n", lrc_was.entries[idx].name);
>  
>  	drm_puts(p, "\n");
>  	drm_printf(p, "OOB Workarounds\n");
> -	for_each_set_bit(idx, gt->wa_active.oob, ARRAY_SIZE(oob_was))
> -		if (oob_was[idx].name)
> -			drm_printf_indent(p, 1, "%s\n", oob_was[idx].name);
> +	for_each_set_bit(idx, gt->wa_active.oob, oob_was.n_entries)
> +		if (oob_was.entries[idx].name)
> +			drm_printf_indent(p, 1, "%s\n", oob_was.entries[idx].name);
>  	return 0;
>  }
>  
> -- 
> 2.43.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH v5 1/4] drm/xe/rtp: Add struct types for RTP tables

[Matt Roper]

On Thu, May 28, 2026 at 09:35:32AM -0700, Violet Monti wrote:
> From: Gustavo Sousa <gustavo.sousa@intel.com>
> 
> We currently have a mixture of styles for our RTP tables with respect of
> how we define the number of entries:
> 
>   * xe_rtp_process_to_sr() expects to receive the number of entries as
>     arguments;
>   * xe_rtp_process() expects the array to have a sentinel at the end of
>     the array;
>   * in xe_rtp_test.c, even though xe_rtp_process_to_sr() does not
>     require a sentinel value, we need to rely on that technique to be
>     able to count xe_rtp_entry_sr entries because simply using
>     ARRAY_SIZE() is not possible.
> 
> The style used by xe_rtp_process_to_sr() makes it hard to share the
> tables with other compilation units (e.g. kunit tests), since the number
> of entries is calculated with ARRAY_SIZE(), which is done at compile
> time.
> 
> Since we use the size of the tables to create some bitmasks, using a
> sentinel style doesn't seem great either.
> 
> A way to reconcile things into a single style is to have a struct type
> that would hold the entries array and the number of entries.  Since we
> have xe_rtp_entry and xe_rtp_entry_sr, we would have one type for each.
> 
> The advantage of the proposed approach is that now we have a nice way to
> share the tables directly to kunit tests with information about their
> size.
> 
> v5:
>     - Remove added code from conflict resolution issues
> 
> v4:
>     - Removed conflicts with main branch
> 
> v3:
>     - No changes
> 
> v2:
>     - Add compatibility with new xe_rtp_table_sr format for
>       "bad-mcr-reg-forced-to-regular" and
>       "bad-regular-reg-forced-to-mcr"
> 
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Violet Monti <violet.monti@intel.com>
> ---
>  drivers/gpu/drm/xe/tests/xe_rtp_test.c | 101 ++++++++++---------------
>  drivers/gpu/drm/xe/xe_hw_engine.c      |  14 ++--
>  drivers/gpu/drm/xe/xe_reg_whitelist.c  |   7 +-
>  drivers/gpu/drm/xe/xe_rtp.c            |  31 ++++----
>  drivers/gpu/drm/xe/xe_rtp.h            |  16 +++-
>  drivers/gpu/drm/xe/xe_rtp_types.h      |  10 +++
>  drivers/gpu/drm/xe/xe_tuning.c         |  45 +++++------
>  drivers/gpu/drm/xe/xe_wa.c             |  89 ++++++++++++----------
>  8 files changed, 156 insertions(+), 157 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/tests/xe_rtp_test.c b/drivers/gpu/drm/xe/tests/xe_rtp_test.c
> index 642f6e090ad0..16bf85033c0c 100644
> --- a/drivers/gpu/drm/xe/tests/xe_rtp_test.c
> +++ b/drivers/gpu/drm/xe/tests/xe_rtp_test.c
> @@ -54,13 +54,13 @@ struct rtp_to_sr_test_case {
>  	unsigned long expected_count_sr_entries;
>  	unsigned int expected_sr_errors;
>  	unsigned long expected_active;
> -	const struct xe_rtp_entry_sr *entries;
> +	const struct xe_rtp_table_sr table;
>  };
>  
>  struct rtp_test_case {
>  	const char *name;
>  	unsigned long expected_active;
> -	const struct xe_rtp_entry *entries;
> +	const struct xe_rtp_table table;
>  };
>  
>  static bool fake_xe_gt_mcr_check_reg(struct xe_gt *gt, struct xe_reg reg)
> @@ -289,7 +289,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  		.expected_active = BIT(0) | BIT(1),
>  		.expected_count_sr_entries = 1,
>  		/* Different bits on the same register: create a single entry */
> -		.entries = (const struct xe_rtp_entry_sr[]) {
> +		.table = XE_RTP_TABLE_SR(
>  			{ XE_RTP_NAME("basic-1"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
> @@ -298,8 +298,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1)))
>  			},
> -			{}
> -		},
> +		),
>  	},
>  	{
>  		.name = "no-match-no-add",
> @@ -309,7 +308,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  		.expected_active = BIT(0),
>  		.expected_count_sr_entries = 1,
>  		/* Don't coalesce second entry since rules don't match */
> -		.entries = (const struct xe_rtp_entry_sr[]) {
> +		.table = XE_RTP_TABLE_SR(
>  			{ XE_RTP_NAME("basic-1"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
> @@ -318,8 +317,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  			  XE_RTP_RULES(FUNC(match_no)),
>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1)))
>  			},
> -			{}
> -		},
> +		),
>  	},
>  	{
>  		.name = "two-regs-two-entries",
> @@ -329,7 +327,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  		.expected_active = BIT(0) | BIT(1),
>  		.expected_count_sr_entries = 2,
>  		/* Same bits on different registers are not coalesced */
> -		.entries = (const struct xe_rtp_entry_sr[]) {
> +		.table = XE_RTP_TABLE_SR(
>  			{ XE_RTP_NAME("basic-1"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
> @@ -338,8 +336,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(SET(REGULAR_REG2, REG_BIT(0)))
>  			},
> -			{}
> -		},
> +		),
>  	},
>  	{
>  		.name = "clr-one-set-other",
> @@ -349,7 +346,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  		.expected_active = BIT(0) | BIT(1),
>  		.expected_count_sr_entries = 1,
>  		/* Check clr vs set actions on different bits */
> -		.entries = (const struct xe_rtp_entry_sr[]) {
> +		.table = XE_RTP_TABLE_SR(
>  			{ XE_RTP_NAME("basic-1"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
> @@ -358,8 +355,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(CLR(REGULAR_REG1, REG_BIT(1)))
>  			},
> -			{}
> -		},
> +		),
>  	},
>  	{
>  #define TEMP_MASK	REG_GENMASK(10, 8)
> @@ -371,14 +367,13 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  		.expected_active = BIT(0),
>  		.expected_count_sr_entries = 1,
>  		/* Check FIELD_SET works */
> -		.entries = (const struct xe_rtp_entry_sr[]) {
> +		.table = XE_RTP_TABLE_SR(
>  			{ XE_RTP_NAME("basic-1"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(FIELD_SET(REGULAR_REG1,
>  						   TEMP_MASK, TEMP_FIELD))
>  			},
> -			{}
> -		},
> +		),
>  #undef TEMP_MASK
>  #undef TEMP_FIELD
>  	},
> @@ -390,7 +385,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  		.expected_active = BIT(0) | BIT(1),
>  		.expected_count_sr_entries = 1,
>  		.expected_sr_errors = 1,
> -		.entries = (const struct xe_rtp_entry_sr[]) {
> +		.table = XE_RTP_TABLE_SR(
>  			{ XE_RTP_NAME("basic-1"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
> @@ -400,8 +395,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
>  			},
> -			{}
> -		},
> +		),
>  	},
>  	{
>  		.name = "conflict-not-disjoint",
> @@ -411,7 +405,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  		.expected_active = BIT(0) | BIT(1),
>  		.expected_count_sr_entries = 1,
>  		.expected_sr_errors = 1,
> -		.entries = (const struct xe_rtp_entry_sr[]) {
> +		.table = XE_RTP_TABLE_SR(
>  			{ XE_RTP_NAME("basic-1"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
> @@ -421,8 +415,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(CLR(REGULAR_REG1, REG_GENMASK(1, 0)))
>  			},
> -			{}
> -		},
> +		),
>  	},
>  	{
>  		.name = "conflict-reg-type",
> @@ -432,7 +425,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  		.expected_active = BIT(0) | BIT(1) | BIT(2),
>  		.expected_count_sr_entries = 1,
>  		.expected_sr_errors = 2,
> -		.entries = (const struct xe_rtp_entry_sr[]) {
> +		.table = XE_RTP_TABLE_SR(
>  			{ XE_RTP_NAME("basic-1"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
> @@ -447,8 +440,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(SET(MASKED_REG1, REG_BIT(0)))
>  			},
> -			{}
> -		},
> +		),
>  	},
>  	{
>  		.name = "bad-mcr-reg-forced-to-regular",
> @@ -458,13 +450,13 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  		.expected_active = BIT(0),
>  		.expected_count_sr_entries = 1,
>  		.expected_sr_errors = 1,
> -		.entries = (const struct xe_rtp_entry_sr[]) {
> +		.table = XE_RTP_TABLE_SR(
>  			{ XE_RTP_NAME("bad-mcr-regular-reg"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(SET(BAD_MCR_REG4, REG_BIT(0)))
>  			},
>  			{}

Oh sorry, I didn't notice this until right after I sent my r-b, but I
think we meant to drop the sentinel here?  And also on the next patch
hunk as well?


Matt

> -		},
> +		),
>  	},
>  	{
>  		.name = "bad-regular-reg-forced-to-mcr",
> @@ -474,13 +466,13 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
>  		.expected_active = BIT(0),
>  		.expected_count_sr_entries = 1,
>  		.expected_sr_errors = 1,
> -		.entries = (const struct xe_rtp_entry_sr[]) {
> +		.table = XE_RTP_TABLE_SR(
>  			{ XE_RTP_NAME("bad-regular-reg"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			  XE_RTP_ACTIONS(SET(BAD_REGULAR_REG5, REG_BIT(0)))
>  			},
>  			{}
> -		},
> +		),
>  	},
>  };
>  
> @@ -492,16 +484,12 @@ static void xe_rtp_process_to_sr_tests(struct kunit *test)
>  	struct xe_reg_sr *reg_sr = &gt->reg_sr;
>  	const struct xe_reg_sr_entry *sre, *sr_entry = NULL;
>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
> -	unsigned long idx, count_sr_entries = 0, count_rtp_entries = 0, active = 0;
> +	unsigned long idx, count_sr_entries = 0, active = 0;
>  
>  	xe_reg_sr_init(reg_sr, "xe_rtp_to_sr_tests", xe);
>  
> -	while (param->entries[count_rtp_entries].rules)
> -		count_rtp_entries++;
> -
> -	xe_rtp_process_ctx_enable_active_tracking(&ctx, &active, count_rtp_entries);
> -	xe_rtp_process_to_sr(&ctx, param->entries, count_rtp_entries,
> -			     reg_sr, false);
> +	xe_rtp_process_ctx_enable_active_tracking(&ctx, &active, param->table.n_entries);
> +	xe_rtp_process_to_sr(&ctx, &param->table, reg_sr, false);
>  
>  	xa_for_each(&reg_sr->xa, idx, sre) {
>  		if (idx == param->expected_reg.addr)
> @@ -534,56 +522,52 @@ static const struct rtp_test_case rtp_cases[] = {
>  	{
>  		.name = "active1",
>  		.expected_active = BIT(0),
> -		.entries = (const struct xe_rtp_entry[]) {
> +		.table = XE_RTP_TABLE(
>  			{ XE_RTP_NAME("r1"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			},
> -			{}
> -		},
> +		),
>  	},
>  	{
>  		.name = "active2",
>  		.expected_active = BIT(0) | BIT(1),
> -		.entries = (const struct xe_rtp_entry[]) {
> +		.table = XE_RTP_TABLE(
>  			{ XE_RTP_NAME("r1"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			},
>  			{ XE_RTP_NAME("r2"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			},
> -			{}
> -		},
> +		),
>  	},
>  	{
>  		.name = "active-inactive",
>  		.expected_active = BIT(0),
> -		.entries = (const struct xe_rtp_entry[]) {
> +		.table = XE_RTP_TABLE(
>  			{ XE_RTP_NAME("r1"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			},
>  			{ XE_RTP_NAME("r2"),
>  			  XE_RTP_RULES(FUNC(match_no)),
>  			},
> -			{}
> -		},
> +		),
>  	},
>  	{
>  		.name = "inactive-active",
>  		.expected_active = BIT(1),
> -		.entries = (const struct xe_rtp_entry[]) {
> +		.table = XE_RTP_TABLE(
>  			{ XE_RTP_NAME("r1"),
>  			  XE_RTP_RULES(FUNC(match_no)),
>  			},
>  			{ XE_RTP_NAME("r2"),
>  			  XE_RTP_RULES(FUNC(match_yes)),
>  			},
> -			{}
> -		},
> +		),
>  	},
>  	{
>  		.name = "inactive-active-inactive",
>  		.expected_active = BIT(1),
> -		.entries = (const struct xe_rtp_entry[]) {
> +		.table = XE_RTP_TABLE(
>  			{ XE_RTP_NAME("r1"),
>  			  XE_RTP_RULES(FUNC(match_no)),
>  			},
> @@ -593,13 +577,12 @@ static const struct rtp_test_case rtp_cases[] = {
>  			{ XE_RTP_NAME("r3"),
>  			  XE_RTP_RULES(FUNC(match_no)),
>  			},
> -			{}
> -		},
> +		),
>  	},
>  	{
>  		.name = "inactive-inactive-inactive",
>  		.expected_active = 0,
> -		.entries = (const struct xe_rtp_entry[]) {
> +		.table = XE_RTP_TABLE(
>  			{ XE_RTP_NAME("r1"),
>  			  XE_RTP_RULES(FUNC(match_no)),
>  			},
> @@ -609,8 +592,7 @@ static const struct rtp_test_case rtp_cases[] = {
>  			{ XE_RTP_NAME("r3"),
>  			  XE_RTP_RULES(FUNC(match_no)),
>  			},
> -			{}
> -		},
> +		),
>  	},
>  };
>  
> @@ -620,13 +602,10 @@ static void xe_rtp_process_tests(struct kunit *test)
>  	struct xe_device *xe = test->priv;
>  	struct xe_gt *gt = xe_device_get_root_tile(xe)->primary_gt;
>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
> -	unsigned long count_rtp_entries = 0, active = 0;
> -
> -	while (param->entries[count_rtp_entries].rules)
> -		count_rtp_entries++;
> +	unsigned long active = 0;
>  
> -	xe_rtp_process_ctx_enable_active_tracking(&ctx, &active, count_rtp_entries);
> -	xe_rtp_process(&ctx, param->entries);
> +	xe_rtp_process_ctx_enable_active_tracking(&ctx, &active, param->table.n_entries);
> +	xe_rtp_process(&ctx, &param->table);
>  
>  	KUNIT_EXPECT_EQ(test, active, param->expected_active);
>  }
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index 8c66ff6f3d3c..98265293f2dc 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -346,7 +346,7 @@ hw_engine_setup_default_lrc_state(struct xe_hw_engine *hwe)
>  	u32 blit_cctl_val = REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, mocs_write_idx) |
>  			    REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, mocs_read_idx);
>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
> -	const struct xe_rtp_entry_sr lrc_setup[] = {
> +	const struct xe_rtp_table_sr lrc_setup = XE_RTP_TABLE_SR(
>  		/*
>  		 * Some blitter commands do not have a field for MOCS, those
>  		 * commands will use MOCS index pointed by BLIT_CCTL.
> @@ -369,10 +369,9 @@ hw_engine_setup_default_lrc_state(struct xe_hw_engine *hwe)
>  					   PREEMPT_GPGPU_THREAD_GROUP_LEVEL)),
>  		  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE)
>  		},
> -	};
> +	);
>  
> -	xe_rtp_process_to_sr(&ctx, lrc_setup, ARRAY_SIZE(lrc_setup),
> -			     &hwe->reg_lrc, true);
> +	xe_rtp_process_to_sr(&ctx, &lrc_setup, &hwe->reg_lrc, true);
>  }
>  
>  void xe_hw_engine_setup_reg_lrc(struct xe_hw_engine *hwe)
> @@ -408,7 +407,7 @@ hw_engine_setup_default_state(struct xe_hw_engine *hwe)
>  	u32 ring_cmd_cctl_val = REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, mocs_write_idx) |
>  				REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, mocs_read_idx);
>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
> -	const struct xe_rtp_entry_sr engine_entries[] = {
> +	const struct xe_rtp_table_sr engine_sr = XE_RTP_TABLE_SR(
>  		{ XE_RTP_NAME("RING_CMD_CCTL_default_MOCS"),
>  		  XE_RTP_RULES(FUNC(xe_rtp_match_always)),
>  		  XE_RTP_ACTIONS(FIELD_SET(RING_CMD_CCTL(0),
> @@ -465,10 +464,9 @@ hw_engine_setup_default_state(struct xe_hw_engine *hwe)
>  		  XE_RTP_ACTIONS(SET(GFX_MODE(0), GFX_MSIX_INTERRUPT_ENABLE,
>  				     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
>  		},
> -	};
> +	);
>  
> -	xe_rtp_process_to_sr(&ctx, engine_entries, ARRAY_SIZE(engine_entries),
> -			     &hwe->reg_sr, false);
> +	xe_rtp_process_to_sr(&ctx, &engine_sr, &hwe->reg_sr, false);
>  }
>  
>  static const struct engine_info *find_engine_info(enum xe_engine_class class, int instance)
> diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> index fb65940848d7..2e84b1c49f37 100644
> --- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
> +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> @@ -41,7 +41,7 @@ static bool match_multi_queue_class(const struct xe_device *xe,
>  	return xe_gt_supports_multi_queue(gt, hwe->class);
>  }
>  
> -static const struct xe_rtp_entry_sr register_whitelist[] = {
> +static const struct xe_rtp_table_sr register_whitelist = XE_RTP_TABLE_SR(
>  	{ XE_RTP_NAME("WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865"),
>  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
>  	  XE_RTP_ACTIONS(WHITELIST(PS_INVOCATION_COUNT,
> @@ -154,7 +154,7 @@ static const struct xe_rtp_entry_sr register_whitelist[] = {
>  	  XE_RTP_RULES(FUNC(match_has_mert), ENGINE_CLASS(COPY)),
>  	  XE_RTP_ACTIONS(WHITELIST_OA_MERT_MMIO_TRG)
>  	},
> -};
> +);
>  
>  static void whitelist_apply_to_hwe(struct xe_hw_engine *hwe)
>  {
> @@ -202,8 +202,7 @@ void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe)
>  {
>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
>  
> -	xe_rtp_process_to_sr(&ctx, register_whitelist, ARRAY_SIZE(register_whitelist),
> -			     &hwe->reg_whitelist, false);
> +	xe_rtp_process_to_sr(&ctx, &register_whitelist, &hwe->reg_whitelist, false);
>  	whitelist_apply_to_hwe(hwe);
>  }
>  
> diff --git a/drivers/gpu/drm/xe/xe_rtp.c b/drivers/gpu/drm/xe/xe_rtp.c
> index dec9d94e6fb0..83a40e1f9528 100644
> --- a/drivers/gpu/drm/xe/xe_rtp.c
> +++ b/drivers/gpu/drm/xe/xe_rtp.c
> @@ -326,8 +326,7 @@ static void rtp_mark_active(struct xe_device *xe,
>   * xe_rtp_process_to_sr - Process all rtp @entries, adding the matching ones to
>   *                        the save-restore argument.
>   * @ctx: The context for processing the table, with one of device, gt or hwe
> - * @entries: Table with RTP definitions
> - * @n_entries: Number of entries to process, usually ARRAY_SIZE(entries)
> + * @table: Table with RTP definitions
>   * @sr: Save-restore struct where matching rules execute the action. This can be
>   *      viewed as the "coalesced view" of multiple the tables. The bits for each
>   *      register set are expected not to collide with previously added entries
> @@ -339,12 +338,10 @@ static void rtp_mark_active(struct xe_device *xe,
>   * used to calculate the right register offset
>   */
>  void xe_rtp_process_to_sr(struct xe_rtp_process_ctx *ctx,
> -			  const struct xe_rtp_entry_sr *entries,
> -			  size_t n_entries,
> +			  const struct xe_rtp_table_sr *table,
>  			  struct xe_reg_sr *sr,
>  			  bool process_in_vf)
>  {
> -	const struct xe_rtp_entry_sr *entry;
>  	struct xe_hw_engine *hwe = NULL;
>  	struct xe_gt *gt = NULL;
>  	struct xe_device *xe = NULL;
> @@ -354,9 +351,10 @@ void xe_rtp_process_to_sr(struct xe_rtp_process_ctx *ctx,
>  	if (!process_in_vf && IS_SRIOV_VF(xe))
>  		return;
>  
> -	xe_assert(xe, entries);
> +	xe_assert(xe, table->entries);
>  
> -	for (entry = entries; entry - entries < n_entries; entry++) {
> +	for (size_t i = 0; i < table->n_entries; i++) {
> +		const struct xe_rtp_entry_sr *entry = &table->entries[i];
>  		bool match = false;
>  
>  		if (entry->flags & XE_RTP_ENTRY_FLAG_FOREACH_ENGINE) {
> @@ -371,37 +369,40 @@ void xe_rtp_process_to_sr(struct xe_rtp_process_ctx *ctx,
>  		}
>  
>  		if (match)
> -			rtp_mark_active(xe, ctx, entry - entries);
> +			rtp_mark_active(xe, ctx, i);
>  	}
>  }
>  EXPORT_SYMBOL_IF_KUNIT(xe_rtp_process_to_sr);
>  
>  /**
> - * xe_rtp_process - Process all rtp @entries, without running any action
> + * xe_rtp_process - Process all entries in rtp @table, without running any action
>   * @ctx: The context for processing the table, with one of device, gt or hwe
> - * @entries: Table with RTP definitions
> + * @table: Table with RTP definitions
>   *
> - * Walk the table pointed by @entries (with an empty sentinel), executing the
> + * Walk the table pointed by @table, executing the
>   * rules. One difference from xe_rtp_process_to_sr(): there is no action
>   * associated with each entry since this uses struct xe_rtp_entry. Its main use
>   * is for marking active workarounds via
>   * xe_rtp_process_ctx_enable_active_tracking().
>   */
>  void xe_rtp_process(struct xe_rtp_process_ctx *ctx,
> -		    const struct xe_rtp_entry *entries)
> +		    const struct xe_rtp_table *table)
>  {
> -	const struct xe_rtp_entry *entry;
>  	struct xe_hw_engine *hwe;
>  	struct xe_gt *gt;
>  	struct xe_device *xe;
>  
>  	rtp_get_context(ctx, &hwe, &gt, &xe);
>  
> -	for (entry = entries; entry && entry->rules; entry++) {
> +	xe_assert(xe, table->entries);
> +
> +	for (size_t i = 0; i < table->n_entries; i++) {
> +		const struct xe_rtp_entry *entry = &table->entries[i];
> +
>  		if (!rule_matches(xe, gt, hwe, entry->rules, entry->n_rules))
>  			continue;
>  
> -		rtp_mark_active(xe, ctx, entry - entries);
> +		rtp_mark_active(xe, ctx, i);
>  	}
>  }
>  EXPORT_SYMBOL_IF_KUNIT(xe_rtp_process);
> diff --git a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h
> index e4f1930ca1c3..4e3cfd69f922 100644
> --- a/drivers/gpu/drm/xe/xe_rtp.h
> +++ b/drivers/gpu/drm/xe/xe_rtp.h
> @@ -461,6 +461,16 @@ struct xe_reg_sr;
>  		XE_RTP_PASTE_FOREACH(ACTION_, COMMA, (__VA_ARGS__))	\
>  	}
>  
> +#define XE_RTP_TABLE_SR(...) { \
> +	.entries = (const struct xe_rtp_entry_sr[]){__VA_ARGS__}, \
> +	.n_entries = ARRAY_SIZE(((const struct xe_rtp_entry_sr[]){__VA_ARGS__})), \
> +}
> +
> +#define XE_RTP_TABLE(...) { \
> +	.entries = (const struct xe_rtp_entry[]){__VA_ARGS__}, \
> +	.n_entries = ARRAY_SIZE(((const struct xe_rtp_entry[]){__VA_ARGS__})), \
> +}
> +
>  #define XE_RTP_PROCESS_CTX_INITIALIZER(arg__) _Generic((arg__),							\
>  	struct xe_hw_engine * :	(struct xe_rtp_process_ctx){ { (void *)(arg__) }, XE_RTP_PROCESS_TYPE_ENGINE },	\
>  	struct xe_gt * :	(struct xe_rtp_process_ctx){ { (void *)(arg__) }, XE_RTP_PROCESS_TYPE_GT },	\
> @@ -471,12 +481,12 @@ void xe_rtp_process_ctx_enable_active_tracking(struct xe_rtp_process_ctx *ctx,
>  					       size_t n_entries);
>  
>  void xe_rtp_process_to_sr(struct xe_rtp_process_ctx *ctx,
> -			  const struct xe_rtp_entry_sr *entries,
> -			  size_t n_entries, struct xe_reg_sr *sr,
> +			  const struct xe_rtp_table_sr *table,
> +			  struct xe_reg_sr *sr,
>  			  bool process_in_vf);
>  
>  void xe_rtp_process(struct xe_rtp_process_ctx *ctx,
> -		    const struct xe_rtp_entry *entries);
> +		    const struct xe_rtp_table *table);
>  
>  /* Match functions to be used with XE_RTP_MATCH_FUNC */
>  
> diff --git a/drivers/gpu/drm/xe/xe_rtp_types.h b/drivers/gpu/drm/xe/xe_rtp_types.h
> index 0265c16d2762..58018ae4f8cc 100644
> --- a/drivers/gpu/drm/xe/xe_rtp_types.h
> +++ b/drivers/gpu/drm/xe/xe_rtp_types.h
> @@ -112,6 +112,16 @@ struct xe_rtp_entry {
>  	u8 n_rules;
>  };
>  
> +struct xe_rtp_table_sr {
> +	const struct xe_rtp_entry_sr *entries;
> +	size_t n_entries;
> +};
> +
> +struct xe_rtp_table {
> +	const struct xe_rtp_entry *entries;
> +	size_t n_entries;
> +};
> +
>  enum xe_rtp_process_type {
>  	XE_RTP_PROCESS_TYPE_DEVICE,
>  	XE_RTP_PROCESS_TYPE_GT,
> diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
> index 9a1b3862e192..bf3fad9cdbef 100644
> --- a/drivers/gpu/drm/xe/xe_tuning.c
> +++ b/drivers/gpu/drm/xe/xe_tuning.c
> @@ -20,7 +20,7 @@
>  #undef XE_REG_MCR
>  #define XE_REG_MCR(...)     XE_REG(__VA_ARGS__, .mcr = 1)
>  
> -static const struct xe_rtp_entry_sr gt_tunings[] = {
> +static const struct xe_rtp_table_sr gt_tunings = XE_RTP_TABLE_SR(
>  	{ XE_RTP_NAME("Tuning: Blend Fill Caching Optimization Disable"),
>  	  XE_RTP_RULES(PLATFORM(DG2)),
>  	  XE_RTP_ACTIONS(SET(XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS))
> @@ -100,9 +100,9 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
>  	  XE_RTP_ACTIONS(FIELD_SET(GAMSTLB_CTRL, BANK_HASH_MODE,
>  				   BANK_HASH_4KB_MODE))
>  	},
> -};
> +);
>  
> -static const struct xe_rtp_entry_sr engine_tunings[] = {
> +static const struct xe_rtp_table_sr engine_tunings = XE_RTP_TABLE_SR(
>  	{ XE_RTP_NAME("Tuning: L3 Hashing Mask"),
>  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210),
>  		       FUNC(xe_rtp_match_first_render_or_compute)),
> @@ -129,9 +129,9 @@ static const struct xe_rtp_entry_sr engine_tunings[] = {
>  		       FUNC(xe_rtp_match_first_render_or_compute)),
>  	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN2, TILEY_LOCALID))
>  	},
> -};
> +);
>  
> -static const struct xe_rtp_entry_sr lrc_tunings[] = {
> +static const struct xe_rtp_table_sr lrc_tunings = XE_RTP_TABLE_SR(
>  	{ XE_RTP_NAME("Tuning: Windower HW Filtering"),
>  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3599), ENGINE_CLASS(RENDER)),
>  	  XE_RTP_ACTIONS(SET(XEHP_COMMON_SLICE_CHICKEN4, HW_FILTERING))
> @@ -171,7 +171,7 @@ static const struct xe_rtp_entry_sr lrc_tunings[] = {
>  	  XE_RTP_ACTIONS(FIELD_SET(FF_MODE, VS_HIT_MAX_VALUE_MASK,
>  				   REG_FIELD_PREP(VS_HIT_MAX_VALUE_MASK, 0x3f)))
>  	},
> -};
> +);
>  
>  /**
>   * xe_tuning_init - initialize gt with tunings bookkeeping
> @@ -185,9 +185,9 @@ int xe_tuning_init(struct xe_gt *gt)
>  	size_t n_lrc, n_engine, n_gt, total;
>  	unsigned long *p;
>  
> -	n_gt = BITS_TO_LONGS(ARRAY_SIZE(gt_tunings));
> -	n_engine = BITS_TO_LONGS(ARRAY_SIZE(engine_tunings));
> -	n_lrc = BITS_TO_LONGS(ARRAY_SIZE(lrc_tunings));
> +	n_gt = BITS_TO_LONGS(gt_tunings.n_entries);
> +	n_engine = BITS_TO_LONGS(engine_tunings.n_entries);
> +	n_lrc = BITS_TO_LONGS(lrc_tunings.n_entries);
>  	total = n_gt + n_engine + n_lrc;
>  
>  	p = drmm_kzalloc(&xe->drm, sizeof(*p) * total, GFP_KERNEL);
> @@ -210,9 +210,8 @@ void xe_tuning_process_gt(struct xe_gt *gt)
>  
>  	xe_rtp_process_ctx_enable_active_tracking(&ctx,
>  						  gt->tuning_active.gt,
> -						  ARRAY_SIZE(gt_tunings));
> -	xe_rtp_process_to_sr(&ctx, gt_tunings, ARRAY_SIZE(gt_tunings),
> -			     &gt->reg_sr, false);
> +						  gt_tunings.n_entries);
> +	xe_rtp_process_to_sr(&ctx, &gt_tunings, &gt->reg_sr, false);
>  }
>  EXPORT_SYMBOL_IF_KUNIT(xe_tuning_process_gt);
>  
> @@ -222,9 +221,8 @@ void xe_tuning_process_engine(struct xe_hw_engine *hwe)
>  
>  	xe_rtp_process_ctx_enable_active_tracking(&ctx,
>  						  hwe->gt->tuning_active.engine,
> -						  ARRAY_SIZE(engine_tunings));
> -	xe_rtp_process_to_sr(&ctx, engine_tunings, ARRAY_SIZE(engine_tunings),
> -			     &hwe->reg_sr, false);
> +						  engine_tunings.n_entries);
> +	xe_rtp_process_to_sr(&ctx, &engine_tunings, &hwe->reg_sr, false);
>  }
>  EXPORT_SYMBOL_IF_KUNIT(xe_tuning_process_engine);
>  
> @@ -242,9 +240,8 @@ void xe_tuning_process_lrc(struct xe_hw_engine *hwe)
>  
>  	xe_rtp_process_ctx_enable_active_tracking(&ctx,
>  						  hwe->gt->tuning_active.lrc,
> -						  ARRAY_SIZE(lrc_tunings));
> -	xe_rtp_process_to_sr(&ctx, lrc_tunings, ARRAY_SIZE(lrc_tunings),
> -			     &hwe->reg_lrc, true);
> +						  lrc_tunings.n_entries);
> +	xe_rtp_process_to_sr(&ctx, &lrc_tunings, &hwe->reg_lrc, true);
>  }
>  
>  /**
> @@ -259,18 +256,18 @@ int xe_tuning_dump(struct xe_gt *gt, struct drm_printer *p)
>  	size_t idx;
>  
>  	drm_printf(p, "GT Tunings\n");
> -	for_each_set_bit(idx, gt->tuning_active.gt, ARRAY_SIZE(gt_tunings))
> -		drm_printf_indent(p, 1, "%s\n", gt_tunings[idx].name);
> +	for_each_set_bit(idx, gt->tuning_active.gt, gt_tunings.n_entries)
> +		drm_printf_indent(p, 1, "%s\n", gt_tunings.entries[idx].name);
>  
>  	drm_puts(p, "\n");
>  	drm_printf(p, "Engine Tunings\n");
> -	for_each_set_bit(idx, gt->tuning_active.engine, ARRAY_SIZE(engine_tunings))
> -		drm_printf_indent(p, 1, "%s\n", engine_tunings[idx].name);
> +	for_each_set_bit(idx, gt->tuning_active.engine, engine_tunings.n_entries)
> +		drm_printf_indent(p, 1, "%s\n", engine_tunings.entries[idx].name);
>  
>  	drm_puts(p, "\n");
>  	drm_printf(p, "LRC Tunings\n");
> -	for_each_set_bit(idx, gt->tuning_active.lrc, ARRAY_SIZE(lrc_tunings))
> -		drm_printf_indent(p, 1, "%s\n", lrc_tunings[idx].name);
> +	for_each_set_bit(idx, gt->tuning_active.lrc, lrc_tunings.n_entries)
> +		drm_printf_indent(p, 1, "%s\n", lrc_tunings.entries[idx].name);
>  
>  	return 0;
>  }
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index cb811f8a7781..b9d9fe0801aa 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -130,7 +130,7 @@
>  __diag_push();
>  __diag_ignore_all("-Woverride-init", "Allow field overrides in table");
>  
> -static const struct xe_rtp_entry_sr gt_was[] = {
> +static const struct xe_rtp_table_sr gt_was = XE_RTP_TABLE_SR(
>  	/* Workarounds applying over a range of IPs */
>  
>  	{ XE_RTP_NAME("14011060649"),
> @@ -306,9 +306,9 @@ static const struct xe_rtp_entry_sr gt_was[] = {
>  	  XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
>  	  XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
>  	},
> -};
> +);
>  
> -static const struct xe_rtp_entry_sr engine_was[] = {
> +static const struct xe_rtp_table_sr engine_was = XE_RTP_TABLE_SR(
>  	/* Workarounds applying over a range of IPs */
>  
>  	{ XE_RTP_NAME("22010931296, 18011464164, 14010919138"),
> @@ -614,9 +614,9 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  		       FUNC(xe_rtp_match_first_render_or_compute)),
>  	  XE_RTP_ACTIONS(SET(TDL_CHICKEN, BIT_APQ_OPT_DIS))
>  	},
> -};
> +);
>  
> -static const struct xe_rtp_entry_sr lrc_was[] = {
> +static const struct xe_rtp_table_sr lrc_was = XE_RTP_TABLE_SR(
>  	{ XE_RTP_NAME("16011163337"),
>  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
>  	  /* read verification is ignored due to 1608008084. */
> @@ -794,21 +794,29 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
>  		       ENGINE_CLASS(RENDER)),
>  	  XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX))
>  	},
> -};
> +);
>  
> -static __maybe_unused const struct xe_rtp_entry oob_was[] = {
> +static const struct xe_rtp_entry oob_was_entries[] = {
>  #include <generated/xe_wa_oob.c>
> -	{}
>  };
>  
> -static_assert(ARRAY_SIZE(oob_was) - 1 == _XE_WA_OOB_COUNT);
> +static_assert(ARRAY_SIZE(oob_was_entries)  == _XE_WA_OOB_COUNT);
>  
> -static __maybe_unused const struct xe_rtp_entry device_oob_was[] = {
> +static __maybe_unused const struct xe_rtp_table oob_was = {
> +	.entries = oob_was_entries,
> +	.n_entries = ARRAY_SIZE(oob_was_entries),
> +};
> +
> +static const struct xe_rtp_entry device_oob_was_entries[] = {
>  #include <generated/xe_device_wa_oob.c>
> -	{}
>  };
>  
> -static_assert(ARRAY_SIZE(device_oob_was) - 1 == _XE_DEVICE_WA_OOB_COUNT);
> +static_assert(ARRAY_SIZE(device_oob_was_entries) == _XE_DEVICE_WA_OOB_COUNT);
> +
> +static __maybe_unused const struct xe_rtp_table device_oob_was = {
> +	.entries = device_oob_was_entries,
> +	.n_entries = ARRAY_SIZE(device_oob_was_entries),
> +};
>  
>  __diag_pop();
>  
> @@ -824,10 +832,10 @@ void xe_wa_process_device_oob(struct xe_device *xe)
>  {
>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(xe);
>  
> -	xe_rtp_process_ctx_enable_active_tracking(&ctx, xe->wa_active.oob, ARRAY_SIZE(device_oob_was));
> +	xe_rtp_process_ctx_enable_active_tracking(&ctx, xe->wa_active.oob, device_oob_was.n_entries);
>  
>  	xe->wa_active.oob_initialized = true;
> -	xe_rtp_process(&ctx, device_oob_was);
> +	xe_rtp_process(&ctx, &device_oob_was);
>  }
>  
>  /**
> @@ -842,9 +850,9 @@ void xe_wa_process_gt_oob(struct xe_gt *gt)
>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
>  
>  	xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.oob,
> -						  ARRAY_SIZE(oob_was));
> +						  oob_was.n_entries);
>  	gt->wa_active.oob_initialized = true;
> -	xe_rtp_process(&ctx, oob_was);
> +	xe_rtp_process(&ctx, &oob_was);
>  }
>  
>  /**
> @@ -859,9 +867,8 @@ void xe_wa_process_gt(struct xe_gt *gt)
>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
>  
>  	xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.gt,
> -						  ARRAY_SIZE(gt_was));
> -	xe_rtp_process_to_sr(&ctx, gt_was, ARRAY_SIZE(gt_was),
> -			     &gt->reg_sr, false);
> +						  gt_was.n_entries);
> +	xe_rtp_process_to_sr(&ctx, &gt_was, &gt->reg_sr, false);
>  }
>  EXPORT_SYMBOL_IF_KUNIT(xe_wa_process_gt);
>  
> @@ -878,9 +885,8 @@ void xe_wa_process_engine(struct xe_hw_engine *hwe)
>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
>  
>  	xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.engine,
> -						  ARRAY_SIZE(engine_was));
> -	xe_rtp_process_to_sr(&ctx, engine_was, ARRAY_SIZE(engine_was),
> -			     &hwe->reg_sr, false);
> +						  engine_was.n_entries);
> +	xe_rtp_process_to_sr(&ctx, &engine_was, &hwe->reg_sr, false);
>  }
>  
>  /**
> @@ -896,9 +902,8 @@ void xe_wa_process_lrc(struct xe_hw_engine *hwe)
>  	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
>  
>  	xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.lrc,
> -						  ARRAY_SIZE(lrc_was));
> -	xe_rtp_process_to_sr(&ctx, lrc_was, ARRAY_SIZE(lrc_was),
> -			     &hwe->reg_lrc, true);
> +						  lrc_was.n_entries);
> +	xe_rtp_process_to_sr(&ctx, &lrc_was, &hwe->reg_lrc, true);
>  }
>  
>  /**
> @@ -912,7 +917,7 @@ int xe_wa_device_init(struct xe_device *xe)
>  	unsigned long *p;
>  
>  	p = drmm_kzalloc(&xe->drm,
> -			 sizeof(*p) * BITS_TO_LONGS(ARRAY_SIZE(device_oob_was)),
> +			 sizeof(*p) * BITS_TO_LONGS(device_oob_was.n_entries),
>  			 GFP_KERNEL);
>  
>  	if (!p)
> @@ -935,10 +940,10 @@ int xe_wa_gt_init(struct xe_gt *gt)
>  	size_t n_oob, n_lrc, n_engine, n_gt, total;
>  	unsigned long *p;
>  
> -	n_gt = BITS_TO_LONGS(ARRAY_SIZE(gt_was));
> -	n_engine = BITS_TO_LONGS(ARRAY_SIZE(engine_was));
> -	n_lrc = BITS_TO_LONGS(ARRAY_SIZE(lrc_was));
> -	n_oob = BITS_TO_LONGS(ARRAY_SIZE(oob_was));
> +	n_gt = BITS_TO_LONGS(gt_was.n_entries);
> +	n_engine = BITS_TO_LONGS(engine_was.n_entries);
> +	n_lrc = BITS_TO_LONGS(lrc_was.n_entries);
> +	n_oob = BITS_TO_LONGS(oob_was.n_entries);
>  	total = n_gt + n_engine + n_lrc + n_oob;
>  
>  	p = drmm_kzalloc(&xe->drm, sizeof(*p) * total, GFP_KERNEL);
> @@ -962,9 +967,9 @@ void xe_wa_device_dump(struct xe_device *xe, struct drm_printer *p)
>  	size_t idx;
>  
>  	drm_printf(p, "Device OOB Workarounds\n");
> -	for_each_set_bit(idx, xe->wa_active.oob, ARRAY_SIZE(device_oob_was))
> -		if (device_oob_was[idx].name)
> -			drm_printf_indent(p, 1, "%s\n", device_oob_was[idx].name);
> +	for_each_set_bit(idx, xe->wa_active.oob, device_oob_was.n_entries)
> +		if (device_oob_was.entries[idx].name)
> +			drm_printf_indent(p, 1, "%s\n", device_oob_was.entries[idx].name);
>  }
>  
>  /**
> @@ -979,24 +984,24 @@ int xe_wa_gt_dump(struct xe_gt *gt, struct drm_printer *p)
>  	size_t idx;
>  
>  	drm_printf(p, "GT Workarounds\n");
> -	for_each_set_bit(idx, gt->wa_active.gt, ARRAY_SIZE(gt_was))
> -		drm_printf_indent(p, 1, "%s\n", gt_was[idx].name);
> +	for_each_set_bit(idx, gt->wa_active.gt, gt_was.n_entries)
> +		drm_printf_indent(p, 1, "%s\n", gt_was.entries[idx].name);
>  
>  	drm_puts(p, "\n");
>  	drm_printf(p, "Engine Workarounds\n");
> -	for_each_set_bit(idx, gt->wa_active.engine, ARRAY_SIZE(engine_was))
> -		drm_printf_indent(p, 1, "%s\n", engine_was[idx].name);
> +	for_each_set_bit(idx, gt->wa_active.engine, engine_was.n_entries)
> +		drm_printf_indent(p, 1, "%s\n", engine_was.entries[idx].name);
>  
>  	drm_puts(p, "\n");
>  	drm_printf(p, "LRC Workarounds\n");
> -	for_each_set_bit(idx, gt->wa_active.lrc, ARRAY_SIZE(lrc_was))
> -		drm_printf_indent(p, 1, "%s\n", lrc_was[idx].name);
> +	for_each_set_bit(idx, gt->wa_active.lrc, lrc_was.n_entries)
> +		drm_printf_indent(p, 1, "%s\n", lrc_was.entries[idx].name);
>  
>  	drm_puts(p, "\n");
>  	drm_printf(p, "OOB Workarounds\n");
> -	for_each_set_bit(idx, gt->wa_active.oob, ARRAY_SIZE(oob_was))
> -		if (oob_was[idx].name)
> -			drm_printf_indent(p, 1, "%s\n", oob_was[idx].name);
> +	for_each_set_bit(idx, gt->wa_active.oob, oob_was.n_entries)
> +		if (oob_was.entries[idx].name)
> +			drm_printf_indent(p, 1, "%s\n", oob_was.entries[idx].name);
>  	return 0;
>  }
>  
> -- 
> 2.43.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation