* [Intel-gfx] [PATCH 2/6] drm/i915/gt: Move ivb GT workarounds from init_clock_gating to workarounds
2020-06-11 8:01 [Intel-gfx] [PATCH 1/6] drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds Chris Wilson
@ 2020-06-11 8:01 ` Chris Wilson
2020-06-11 9:59 ` Mika Kuoppala
2020-06-11 10:41 ` Chris Wilson
2020-06-11 8:01 ` [Intel-gfx] [PATCH 3/6] drm/i915/gt: Move vlv " Chris Wilson
` (12 subsequent siblings)
13 siblings, 2 replies; 23+ messages in thread
From: Chris Wilson @ 2020-06-11 8:01 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
Rescue the GT workarounds from being buried inside init_clock_gating so
that we remember to apply them after a GT reset, and that they are
included in our verification that the workarounds are applied.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 62 +++++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 48 ----------------
3 files changed, 63 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 39f070bff09d..a5ba3ea8d45a 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -714,6 +714,66 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq)
return 0;
}
+static void
+ivb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
+{
+ /* WaDisableEarlyCull:ivb */
+ wa_masked_en(wal,_3D_CHICKEN3, _3D_CHICKEN_SF_DISABLE_OBJEND_CULL);
+
+ /* WaDisablePSDDualDispatchEnable:ivb */
+ if (IS_IVB_GT1(i915))
+ wa_masked_en(wal,
+ GEN7_HALF_SLICE_CHICKEN1,
+ GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
+
+ /* WaDisable_RenderCache_OperationalFlush:ivb */
+ wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE);
+
+ /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
+ wa_masked_dis(wal,
+ GEN7_COMMON_SLICE_CHICKEN1,
+ GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
+
+ /* WaApplyL3ControlAndL3ChickenMode:ivb */
+ wa_write(wal, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL);
+ wa_write(wal, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
+
+ /* WaForceL3Serialization:ivb */
+ wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE);
+
+ /*
+ * WaVSThreadDispatchOverride:ivb,vlv
+ *
+ * This actually overrides the dispatch
+ * mode for all thread types.
+ */
+ wa_write_masked_or(wal, GEN7_FF_THREAD_MODE,
+ GEN7_FF_SCHED_MASK,
+ GEN7_FF_TS_SCHED_HW |
+ GEN7_FF_VS_SCHED_HW |
+ GEN7_FF_DS_SCHED_HW);
+
+ if (0) { /* causes HiZ corruption on ivb:gt1 */
+ /* enable HiZ Raw Stall Optimization */
+ wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
+ }
+
+ /* WaDisable4x2SubspanOptimization:ivb */
+ wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
+
+ /*
+ * BSpec recommends 8x4 when MSAA is used,
+ * however in practice 16x4 seems fastest.
+ *
+ * Note that PS/WM thread counts depend on the WIZ hashing
+ * disable bit, which we don't touch here, but it's good
+ * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
+ */
+ wa_add(wal, GEN7_GT_MODE, 0,
+ _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4),
+ GEN6_WIZ_HASHING_16x4);
+}
+
static void
hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
@@ -1033,6 +1093,8 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
skl_gt_workarounds_init(i915, wal);
else if (IS_HASWELL(i915))
hsw_gt_workarounds_init(i915, wal);
+ else if (IS_IVYBRIDGE(i915))
+ ivb_gt_workarounds_init(i915, wal);
else if (INTEL_GEN(i915) <= 8)
return;
else
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9aca6d778220..19e1fed198c3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7924,7 +7924,7 @@ enum {
/* GEN7 chicken */
#define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
- #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1 << 10) | (1 << 26))
+ #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC (1 << 10)
#define GEN9_RHWO_OPTIMIZATION_DISABLE (1 << 14)
#define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 249ee720874c..b835e5e97515 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7338,32 +7338,11 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
- /* WaDisableEarlyCull:ivb */
- I915_WRITE(_3D_CHICKEN3,
- _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
-
/* WaDisableBackToBackFlipFix:ivb */
I915_WRITE(IVB_CHICKEN3,
CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
CHICKEN3_DGMG_DONE_FIX_DISABLE);
- /* WaDisablePSDDualDispatchEnable:ivb */
- if (IS_IVB_GT1(dev_priv))
- I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
- _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
-
- /* WaDisable_RenderCache_OperationalFlush:ivb */
- I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
-
- /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
- I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
- GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
-
- /* WaApplyL3ControlAndL3ChickenMode:ivb */
- I915_WRITE(GEN7_L3CNTLREG1,
- GEN7_WA_FOR_GEN7_L3_CONTROL);
- I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
- GEN7_WA_L3_CHICKEN_MODE);
if (IS_IVB_GT1(dev_priv))
I915_WRITE(GEN7_ROW_CHICKEN2,
_MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
@@ -7375,10 +7354,6 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
_MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
}
- /* WaForceL3Serialization:ivb */
- I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
- ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
-
/*
* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
* This implements the WaDisableRCZUnitClockGating:ivb workaround.
@@ -7393,29 +7368,6 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
g4x_disable_trickle_feed(dev_priv);
- gen7_setup_fixed_func_scheduler(dev_priv);
-
- if (0) { /* causes HiZ corruption on ivb:gt1 */
- /* enable HiZ Raw Stall Optimization */
- I915_WRITE(CACHE_MODE_0_GEN7,
- _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
- }
-
- /* WaDisable4x2SubspanOptimization:ivb */
- I915_WRITE(CACHE_MODE_1,
- _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
-
- /*
- * BSpec recommends 8x4 when MSAA is used,
- * however in practice 16x4 seems fastest.
- *
- * Note that PS/WM thread counts depend on the WIZ hashing
- * disable bit, which we don't touch here, but it's good
- * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
- */
- I915_WRITE(GEN7_GT_MODE,
- _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
-
snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
snpcr &= ~GEN6_MBC_SNPCR_MASK;
snpcr |= GEN6_MBC_SNPCR_MED;
--
2.20.1
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^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [Intel-gfx] [PATCH 2/6] drm/i915/gt: Move ivb GT workarounds from init_clock_gating to workarounds
2020-06-11 8:01 ` [Intel-gfx] [PATCH 2/6] drm/i915/gt: Move ivb " Chris Wilson
@ 2020-06-11 9:59 ` Mika Kuoppala
2020-06-11 10:00 ` Mika Kuoppala
2020-06-11 10:41 ` Chris Wilson
1 sibling, 1 reply; 23+ messages in thread
From: Mika Kuoppala @ 2020-06-11 9:59 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: Chris Wilson
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Rescue the GT workarounds from being buried inside init_clock_gating so
> that we remember to apply them after a GT reset, and that they are
> included in our verification that the workarounds are applied.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 62 +++++++++++++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> drivers/gpu/drm/i915/intel_pm.c | 48 ----------------
> 3 files changed, 63 insertions(+), 49 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 39f070bff09d..a5ba3ea8d45a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -714,6 +714,66 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq)
> return 0;
> }
>
> +static void
> +ivb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> +{
> + /* WaDisableEarlyCull:ivb */
> + wa_masked_en(wal,_3D_CHICKEN3, _3D_CHICKEN_SF_DISABLE_OBJEND_CULL);
> +
> + /* WaDisablePSDDualDispatchEnable:ivb */
> + if (IS_IVB_GT1(i915))
> + wa_masked_en(wal,
> + GEN7_HALF_SLICE_CHICKEN1,
> + GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
> +
> + /* WaDisable_RenderCache_OperationalFlush:ivb */
> + wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE);
> +
> + /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
> + wa_masked_dis(wal,
> + GEN7_COMMON_SLICE_CHICKEN1,
> + GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
> +
> + /* WaApplyL3ControlAndL3ChickenMode:ivb */
> + wa_write(wal, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL);
> + wa_write(wal, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
> +
> + /* WaForceL3Serialization:ivb */
> + wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE);
> +
> + /*
> + * WaVSThreadDispatchOverride:ivb,vlv
> + *
> + * This actually overrides the dispatch
> + * mode for all thread types.
> + */
> + wa_write_masked_or(wal, GEN7_FF_THREAD_MODE,
> + GEN7_FF_SCHED_MASK,
> + GEN7_FF_TS_SCHED_HW |
> + GEN7_FF_VS_SCHED_HW |
> + GEN7_FF_DS_SCHED_HW);
> +
> + if (0) { /* causes HiZ corruption on ivb:gt1 */
> + /* enable HiZ Raw Stall Optimization */
> + wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
> + }
> +
> + /* WaDisable4x2SubspanOptimization:ivb */
> + wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
> +
> + /*
> + * BSpec recommends 8x4 when MSAA is used,
> + * however in practice 16x4 seems fastest.
> + *
> + * Note that PS/WM thread counts depend on the WIZ hashing
> + * disable bit, which we don't touch here, but it's good
> + * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
> + */
> + wa_add(wal, GEN7_GT_MODE, 0,
> + _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4),
> + GEN6_WIZ_HASHING_16x4);
> +}
> +
> static void
> hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> {
> @@ -1033,6 +1093,8 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
> skl_gt_workarounds_init(i915, wal);
> else if (IS_HASWELL(i915))
> hsw_gt_workarounds_init(i915, wal);
> + else if (IS_IVYBRIDGE(i915))
> + ivb_gt_workarounds_init(i915, wal);
> else if (INTEL_GEN(i915) <= 8)
> return;
> else
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9aca6d778220..19e1fed198c3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7924,7 +7924,7 @@ enum {
>
> /* GEN7 chicken */
> #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
> - #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1 << 10) | (1 << 26))
> + #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC (1 << 10)
I dont have bspec but evidence is overwhelming that this is masked reg.
> #define GEN9_RHWO_OPTIMIZATION_DISABLE (1 << 14)
>
> #define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 249ee720874c..b835e5e97515 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7338,32 +7338,11 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
>
> I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
>
> - /* WaDisableEarlyCull:ivb */
> - I915_WRITE(_3D_CHICKEN3,
> - _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
> -
> /* WaDisableBackToBackFlipFix:ivb */
> I915_WRITE(IVB_CHICKEN3,
> CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
> CHICKEN3_DGMG_DONE_FIX_DISABLE);
>
> - /* WaDisablePSDDualDispatchEnable:ivb */
> - if (IS_IVB_GT1(dev_priv))
> - I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
> - _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> -
> - /* WaDisable_RenderCache_OperationalFlush:ivb */
> - I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
> -
> - /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
> - I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
> - GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
> -
> - /* WaApplyL3ControlAndL3ChickenMode:ivb */
> - I915_WRITE(GEN7_L3CNTLREG1,
> - GEN7_WA_FOR_GEN7_L3_CONTROL);
> - I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
> - GEN7_WA_L3_CHICKEN_MODE);
> if (IS_IVB_GT1(dev_priv))
> I915_WRITE(GEN7_ROW_CHICKEN2,
> _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> @@ -7375,10 +7354,6 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
> _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> }
>
> - /* WaForceL3Serialization:ivb */
> - I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
> - ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
> -
> /*
> * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
> * This implements the WaDisableRCZUnitClockGating:ivb workaround.
> @@ -7393,29 +7368,6 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
>
> g4x_disable_trickle_feed(dev_priv);
>
> - gen7_setup_fixed_func_scheduler(dev_priv);
This just disappears without explanation.
-Mika
> -
> - if (0) { /* causes HiZ corruption on ivb:gt1 */
> - /* enable HiZ Raw Stall Optimization */
> - I915_WRITE(CACHE_MODE_0_GEN7,
> - _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
> - }
> -
> - /* WaDisable4x2SubspanOptimization:ivb */
> - I915_WRITE(CACHE_MODE_1,
> - _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
> -
> - /*
> - * BSpec recommends 8x4 when MSAA is used,
> - * however in practice 16x4 seems fastest.
> - *
> - * Note that PS/WM thread counts depend on the WIZ hashing
> - * disable bit, which we don't touch here, but it's good
> - * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
> - */
> - I915_WRITE(GEN7_GT_MODE,
> - _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
> -
> snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
> snpcr &= ~GEN6_MBC_SNPCR_MASK;
> snpcr |= GEN6_MBC_SNPCR_MED;
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [Intel-gfx] [PATCH 2/6] drm/i915/gt: Move ivb GT workarounds from init_clock_gating to workarounds
2020-06-11 9:59 ` Mika Kuoppala
@ 2020-06-11 10:00 ` Mika Kuoppala
0 siblings, 0 replies; 23+ messages in thread
From: Mika Kuoppala @ 2020-06-11 10:00 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: Chris Wilson
Mika Kuoppala <mika.kuoppala@linux.intel.com> writes:
> Chris Wilson <chris@chris-wilson.co.uk> writes:
>
>> Rescue the GT workarounds from being buried inside init_clock_gating so
>> that we remember to apply them after a GT reset, and that they are
>> included in our verification that the workarounds are applied.
>>
>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>> ---
>> drivers/gpu/drm/i915/gt/intel_workarounds.c | 62 +++++++++++++++++++++
>> drivers/gpu/drm/i915/i915_reg.h | 2 +-
>> drivers/gpu/drm/i915/intel_pm.c | 48 ----------------
>> 3 files changed, 63 insertions(+), 49 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> index 39f070bff09d..a5ba3ea8d45a 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> @@ -714,6 +714,66 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq)
>> return 0;
>> }
>>
>> +static void
>> +ivb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>> +{
>> + /* WaDisableEarlyCull:ivb */
>> + wa_masked_en(wal,_3D_CHICKEN3, _3D_CHICKEN_SF_DISABLE_OBJEND_CULL);
>> +
>> + /* WaDisablePSDDualDispatchEnable:ivb */
>> + if (IS_IVB_GT1(i915))
>> + wa_masked_en(wal,
>> + GEN7_HALF_SLICE_CHICKEN1,
>> + GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
>> +
>> + /* WaDisable_RenderCache_OperationalFlush:ivb */
>> + wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE);
>> +
>> + /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
>> + wa_masked_dis(wal,
>> + GEN7_COMMON_SLICE_CHICKEN1,
>> + GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
>> +
>> + /* WaApplyL3ControlAndL3ChickenMode:ivb */
>> + wa_write(wal, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL);
>> + wa_write(wal, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
>> +
>> + /* WaForceL3Serialization:ivb */
>> + wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE);
>> +
>> + /*
>> + * WaVSThreadDispatchOverride:ivb,vlv
>> + *
>> + * This actually overrides the dispatch
>> + * mode for all thread types.
>> + */
>> + wa_write_masked_or(wal, GEN7_FF_THREAD_MODE,
>> + GEN7_FF_SCHED_MASK,
>> + GEN7_FF_TS_SCHED_HW |
>> + GEN7_FF_VS_SCHED_HW |
>> + GEN7_FF_DS_SCHED_HW);
>> +
>> + if (0) { /* causes HiZ corruption on ivb:gt1 */
>> + /* enable HiZ Raw Stall Optimization */
>> + wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
>> + }
>> +
>> + /* WaDisable4x2SubspanOptimization:ivb */
>> + wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
>> +
>> + /*
>> + * BSpec recommends 8x4 when MSAA is used,
>> + * however in practice 16x4 seems fastest.
>> + *
>> + * Note that PS/WM thread counts depend on the WIZ hashing
>> + * disable bit, which we don't touch here, but it's good
>> + * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
>> + */
>> + wa_add(wal, GEN7_GT_MODE, 0,
>> + _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4),
>> + GEN6_WIZ_HASHING_16x4);
>> +}
>> +
>> static void
>> hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>> {
>> @@ -1033,6 +1093,8 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
>> skl_gt_workarounds_init(i915, wal);
>> else if (IS_HASWELL(i915))
>> hsw_gt_workarounds_init(i915, wal);
>> + else if (IS_IVYBRIDGE(i915))
>> + ivb_gt_workarounds_init(i915, wal);
>> else if (INTEL_GEN(i915) <= 8)
>> return;
>> else
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 9aca6d778220..19e1fed198c3 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -7924,7 +7924,7 @@ enum {
>>
>> /* GEN7 chicken */
>> #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
>> - #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1 << 10) | (1 << 26))
>> + #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC (1 << 10)
>
> I dont have bspec but evidence is overwhelming that this is masked reg.
>
>> #define GEN9_RHWO_OPTIMIZATION_DISABLE (1 << 14)
>>
>> #define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index 249ee720874c..b835e5e97515 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -7338,32 +7338,11 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
>>
>> I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
>>
>> - /* WaDisableEarlyCull:ivb */
>> - I915_WRITE(_3D_CHICKEN3,
>> - _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
>> -
>> /* WaDisableBackToBackFlipFix:ivb */
>> I915_WRITE(IVB_CHICKEN3,
>> CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
>> CHICKEN3_DGMG_DONE_FIX_DISABLE);
>>
>> - /* WaDisablePSDDualDispatchEnable:ivb */
>> - if (IS_IVB_GT1(dev_priv))
>> - I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
>> - _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
>> -
>> - /* WaDisable_RenderCache_OperationalFlush:ivb */
>> - I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
>> -
>> - /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
>> - I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
>> - GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
>> -
>> - /* WaApplyL3ControlAndL3ChickenMode:ivb */
>> - I915_WRITE(GEN7_L3CNTLREG1,
>> - GEN7_WA_FOR_GEN7_L3_CONTROL);
>> - I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
>> - GEN7_WA_L3_CHICKEN_MODE);
>> if (IS_IVB_GT1(dev_priv))
>> I915_WRITE(GEN7_ROW_CHICKEN2,
>> _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
>> @@ -7375,10 +7354,6 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
>> _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
>> }
>>
>> - /* WaForceL3Serialization:ivb */
>> - I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
>> - ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
>> -
>> /*
>> * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
>> * This implements the WaDisableRCZUnitClockGating:ivb workaround.
>> @@ -7393,29 +7368,6 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
>>
>> g4x_disable_trickle_feed(dev_priv);
>>
>> - gen7_setup_fixed_func_scheduler(dev_priv);
>
> This just disappears without explanation.
Oh there is explanation.
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> -Mika
>
>> -
>> - if (0) { /* causes HiZ corruption on ivb:gt1 */
>> - /* enable HiZ Raw Stall Optimization */
>> - I915_WRITE(CACHE_MODE_0_GEN7,
>> - _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
>> - }
>> -
>> - /* WaDisable4x2SubspanOptimization:ivb */
>> - I915_WRITE(CACHE_MODE_1,
>> - _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
>> -
>> - /*
>> - * BSpec recommends 8x4 when MSAA is used,
>> - * however in practice 16x4 seems fastest.
>> - *
>> - * Note that PS/WM thread counts depend on the WIZ hashing
>> - * disable bit, which we don't touch here, but it's good
>> - * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
>> - */
>> - I915_WRITE(GEN7_GT_MODE,
>> - _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
>> -
>> snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
>> snpcr &= ~GEN6_MBC_SNPCR_MASK;
>> snpcr |= GEN6_MBC_SNPCR_MED;
>> --
>> 2.20.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Intel-gfx] [PATCH 2/6] drm/i915/gt: Move ivb GT workarounds from init_clock_gating to workarounds
2020-06-11 8:01 ` [Intel-gfx] [PATCH 2/6] drm/i915/gt: Move ivb " Chris Wilson
2020-06-11 9:59 ` Mika Kuoppala
@ 2020-06-11 10:41 ` Chris Wilson
1 sibling, 0 replies; 23+ messages in thread
From: Chris Wilson @ 2020-06-11 10:41 UTC (permalink / raw)
To: intel-gfx
Quoting Chris Wilson (2020-06-11 09:01:36)
> +static void
> +ivb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> + /*
> + * BSpec recommends 8x4 when MSAA is used,
> + * however in practice 16x4 seems fastest.
> + *
> + * Note that PS/WM thread counts depend on the WIZ hashing
> + * disable bit, which we don't touch here, but it's good
> + * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
> + */
> + wa_add(wal, GEN7_GT_MODE, 0,
> + _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4),
> + GEN6_WIZ_HASHING_16x4);
Fwiw, from gen8+, we have this in the ctx workarounds. Not sure if
that's a better spot or not. An inquiry for later, as it is passing the
tests for now :)
-Chris
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^ permalink raw reply [flat|nested] 23+ messages in thread
* [Intel-gfx] [PATCH 3/6] drm/i915/gt: Move vlv GT workarounds from init_clock_gating to workarounds
2020-06-11 8:01 [Intel-gfx] [PATCH 1/6] drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds Chris Wilson
2020-06-11 8:01 ` [Intel-gfx] [PATCH 2/6] drm/i915/gt: Move ivb " Chris Wilson
@ 2020-06-11 8:01 ` Chris Wilson
2020-06-11 10:02 ` Mika Kuoppala
2020-06-11 8:01 ` [Intel-gfx] [PATCH 4/6] drm/i915/gt: Move snb " Chris Wilson
` (11 subsequent siblings)
13 siblings, 1 reply; 23+ messages in thread
From: Chris Wilson @ 2020-06-11 8:01 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
Rescue the GT workarounds from being buried inside init_clock_gating so
that we remember to apply them after a GT reset, and that they are
included in our verification that the workarounds are applied.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 59 ++++++++++++++++++++
drivers/gpu/drm/i915/intel_pm.c | 61 ---------------------
2 files changed, 59 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index a5ba3ea8d45a..688ca25d79d0 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -774,6 +774,63 @@ ivb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
GEN6_WIZ_HASHING_16x4);
}
+static void
+vlv_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
+{
+ /* WaDisableEarlyCull:vlv */
+ wa_masked_en(wal,_3D_CHICKEN3, _3D_CHICKEN_SF_DISABLE_OBJEND_CULL);
+
+ /* WaPsdDispatchEnable:vlv */
+ /* WaDisablePSDDualDispatchEnable:vlv */
+ wa_masked_en(wal,
+ GEN7_HALF_SLICE_CHICKEN1,
+ GEN7_MAX_PS_THREAD_DEP |
+ GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
+
+ /* WaDisable_RenderCache_OperationalFlush:vlv */
+ wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE);
+
+ /* WaForceL3Serialization:vlv */
+ wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE);
+
+ /*
+ * WaVSThreadDispatchOverride:ivb,vlv
+ *
+ * This actually overrides the dispatch
+ * mode for all thread types.
+ */
+ wa_write_masked_or(wal,
+ GEN7_FF_THREAD_MODE,
+ GEN7_FF_SCHED_MASK,
+ GEN7_FF_TS_SCHED_HW |
+ GEN7_FF_VS_SCHED_HW |
+ GEN7_FF_DS_SCHED_HW);
+
+ /*
+ * BSpec says this must be set, even though
+ * WaDisable4x2SubspanOptimization isn't listed for VLV.
+ */
+ wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
+
+ /*
+ * BSpec recommends 8x4 when MSAA is used,
+ * however in practice 16x4 seems fastest.
+ *
+ * Note that PS/WM thread counts depend on the WIZ hashing
+ * disable bit, which we don't touch here, but it's good
+ * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
+ */
+ wa_add(wal, GEN7_GT_MODE, 0,
+ _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4),
+ GEN6_WIZ_HASHING_16x4);
+
+ /*
+ * WaIncreaseL3CreditsForVLVB0:vlv
+ * This is the hardware default actually.
+ */
+ wa_write(wal, GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
+}
+
static void
hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
@@ -1093,6 +1150,8 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
skl_gt_workarounds_init(i915, wal);
else if (IS_HASWELL(i915))
hsw_gt_workarounds_init(i915, wal);
+ else if (IS_VALLEYVIEW(i915))
+ vlv_gt_workarounds_init(i915, wal);
else if (IS_IVYBRIDGE(i915))
ivb_gt_workarounds_init(i915, wal);
else if (INTEL_GEN(i915) <= 8)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b835e5e97515..29abde47e987 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7077,24 +7077,6 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
gen6_check_mch_setup(dev_priv);
}
-static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
-{
- u32 reg = I915_READ(GEN7_FF_THREAD_MODE);
-
- /*
- * WaVSThreadDispatchOverride:ivb,vlv
- *
- * This actually overrides the dispatch
- * mode for all thread types.
- */
- reg &= ~GEN7_FF_SCHED_MASK;
- reg |= GEN7_FF_TS_SCHED_HW;
- reg |= GEN7_FF_VS_SCHED_HW;
- reg |= GEN7_FF_DS_SCHED_HW;
-
- I915_WRITE(GEN7_FF_THREAD_MODE, reg);
-}
-
static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
{
/*
@@ -7381,28 +7363,11 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
static void vlv_init_clock_gating(struct drm_i915_private *dev_priv)
{
- /* WaDisableEarlyCull:vlv */
- I915_WRITE(_3D_CHICKEN3,
- _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
-
/* WaDisableBackToBackFlipFix:vlv */
I915_WRITE(IVB_CHICKEN3,
CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
CHICKEN3_DGMG_DONE_FIX_DISABLE);
- /* WaPsdDispatchEnable:vlv */
- /* WaDisablePSDDualDispatchEnable:vlv */
- I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
- _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
- GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
-
- /* WaDisable_RenderCache_OperationalFlush:vlv */
- I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
-
- /* WaForceL3Serialization:vlv */
- I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
- ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
-
/* WaDisableDopClockGating:vlv */
I915_WRITE(GEN7_ROW_CHICKEN2,
_MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
@@ -7412,8 +7377,6 @@ static void vlv_init_clock_gating(struct drm_i915_private *dev_priv)
I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
- gen7_setup_fixed_func_scheduler(dev_priv);
-
/*
* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
* This implements the WaDisableRCZUnitClockGating:vlv workaround.
@@ -7427,30 +7390,6 @@ static void vlv_init_clock_gating(struct drm_i915_private *dev_priv)
I915_WRITE(GEN7_UCGCTL4,
I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
- /*
- * BSpec says this must be set, even though
- * WaDisable4x2SubspanOptimization isn't listed for VLV.
- */
- I915_WRITE(CACHE_MODE_1,
- _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
-
- /*
- * BSpec recommends 8x4 when MSAA is used,
- * however in practice 16x4 seems fastest.
- *
- * Note that PS/WM thread counts depend on the WIZ hashing
- * disable bit, which we don't touch here, but it's good
- * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
- */
- I915_WRITE(GEN7_GT_MODE,
- _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
-
- /*
- * WaIncreaseL3CreditsForVLVB0:vlv
- * This is the hardware default actually.
- */
- I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
-
/*
* WaDisableVLVClockGating_VBIIssue:vlv
* Disable clock gating on th GCFG unit to prevent a delay
--
2.20.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [Intel-gfx] [PATCH 3/6] drm/i915/gt: Move vlv GT workarounds from init_clock_gating to workarounds
2020-06-11 8:01 ` [Intel-gfx] [PATCH 3/6] drm/i915/gt: Move vlv " Chris Wilson
@ 2020-06-11 10:02 ` Mika Kuoppala
0 siblings, 0 replies; 23+ messages in thread
From: Mika Kuoppala @ 2020-06-11 10:02 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: Chris Wilson
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Rescue the GT workarounds from being buried inside init_clock_gating so
> that we remember to apply them after a GT reset, and that they are
> included in our verification that the workarounds are applied.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 59 ++++++++++++++++++++
> drivers/gpu/drm/i915/intel_pm.c | 61 ---------------------
> 2 files changed, 59 insertions(+), 61 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index a5ba3ea8d45a..688ca25d79d0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -774,6 +774,63 @@ ivb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> GEN6_WIZ_HASHING_16x4);
> }
>
> +static void
> +vlv_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> +{
> + /* WaDisableEarlyCull:vlv */
> + wa_masked_en(wal,_3D_CHICKEN3, _3D_CHICKEN_SF_DISABLE_OBJEND_CULL);
> +
> + /* WaPsdDispatchEnable:vlv */
> + /* WaDisablePSDDualDispatchEnable:vlv */
> + wa_masked_en(wal,
> + GEN7_HALF_SLICE_CHICKEN1,
> + GEN7_MAX_PS_THREAD_DEP |
> + GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
> +
> + /* WaDisable_RenderCache_OperationalFlush:vlv */
> + wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE);
> +
> + /* WaForceL3Serialization:vlv */
> + wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE);
> +
> + /*
> + * WaVSThreadDispatchOverride:ivb,vlv
> + *
> + * This actually overrides the dispatch
> + * mode for all thread types.
> + */
> + wa_write_masked_or(wal,
> + GEN7_FF_THREAD_MODE,
> + GEN7_FF_SCHED_MASK,
> + GEN7_FF_TS_SCHED_HW |
> + GEN7_FF_VS_SCHED_HW |
> + GEN7_FF_DS_SCHED_HW);
> +
> + /*
> + * BSpec says this must be set, even though
> + * WaDisable4x2SubspanOptimization isn't listed for VLV.
> + */
> + wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
> +
> + /*
> + * BSpec recommends 8x4 when MSAA is used,
> + * however in practice 16x4 seems fastest.
> + *
> + * Note that PS/WM thread counts depend on the WIZ hashing
> + * disable bit, which we don't touch here, but it's good
> + * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
> + */
> + wa_add(wal, GEN7_GT_MODE, 0,
> + _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4),
> + GEN6_WIZ_HASHING_16x4);
> +
> + /*
> + * WaIncreaseL3CreditsForVLVB0:vlv
> + * This is the hardware default actually.
> + */
> + wa_write(wal, GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
> +}
> +
> static void
> hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> {
> @@ -1093,6 +1150,8 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
> skl_gt_workarounds_init(i915, wal);
> else if (IS_HASWELL(i915))
> hsw_gt_workarounds_init(i915, wal);
> + else if (IS_VALLEYVIEW(i915))
> + vlv_gt_workarounds_init(i915, wal);
> else if (IS_IVYBRIDGE(i915))
> ivb_gt_workarounds_init(i915, wal);
> else if (INTEL_GEN(i915) <= 8)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index b835e5e97515..29abde47e987 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7077,24 +7077,6 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
> gen6_check_mch_setup(dev_priv);
> }
>
> -static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
> -{
> - u32 reg = I915_READ(GEN7_FF_THREAD_MODE);
> -
> - /*
> - * WaVSThreadDispatchOverride:ivb,vlv
> - *
> - * This actually overrides the dispatch
> - * mode for all thread types.
> - */
> - reg &= ~GEN7_FF_SCHED_MASK;
> - reg |= GEN7_FF_TS_SCHED_HW;
> - reg |= GEN7_FF_VS_SCHED_HW;
> - reg |= GEN7_FF_DS_SCHED_HW;
> -
> - I915_WRITE(GEN7_FF_THREAD_MODE, reg);
> -}
> -
> static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
> {
> /*
> @@ -7381,28 +7363,11 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
>
> static void vlv_init_clock_gating(struct drm_i915_private *dev_priv)
> {
> - /* WaDisableEarlyCull:vlv */
> - I915_WRITE(_3D_CHICKEN3,
> - _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
> -
> /* WaDisableBackToBackFlipFix:vlv */
> I915_WRITE(IVB_CHICKEN3,
> CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
> CHICKEN3_DGMG_DONE_FIX_DISABLE);
>
> - /* WaPsdDispatchEnable:vlv */
> - /* WaDisablePSDDualDispatchEnable:vlv */
> - I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
> - _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
> - GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> -
> - /* WaDisable_RenderCache_OperationalFlush:vlv */
> - I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
> -
> - /* WaForceL3Serialization:vlv */
> - I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
> - ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
> -
> /* WaDisableDopClockGating:vlv */
> I915_WRITE(GEN7_ROW_CHICKEN2,
> _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> @@ -7412,8 +7377,6 @@ static void vlv_init_clock_gating(struct drm_i915_private *dev_priv)
> I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
> GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
>
> - gen7_setup_fixed_func_scheduler(dev_priv);
> -
> /*
> * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
> * This implements the WaDisableRCZUnitClockGating:vlv workaround.
> @@ -7427,30 +7390,6 @@ static void vlv_init_clock_gating(struct drm_i915_private *dev_priv)
> I915_WRITE(GEN7_UCGCTL4,
> I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
>
> - /*
> - * BSpec says this must be set, even though
> - * WaDisable4x2SubspanOptimization isn't listed for VLV.
> - */
> - I915_WRITE(CACHE_MODE_1,
> - _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
> -
> - /*
> - * BSpec recommends 8x4 when MSAA is used,
> - * however in practice 16x4 seems fastest.
> - *
> - * Note that PS/WM thread counts depend on the WIZ hashing
> - * disable bit, which we don't touch here, but it's good
> - * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
> - */
> - I915_WRITE(GEN7_GT_MODE,
> - _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
> -
> - /*
> - * WaIncreaseL3CreditsForVLVB0:vlv
> - * This is the hardware default actually.
> - */
> - I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
> -
> /*
> * WaDisableVLVClockGating_VBIIssue:vlv
> * Disable clock gating on th GCFG unit to prevent a delay
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread
* [Intel-gfx] [PATCH 4/6] drm/i915/gt: Move snb GT workarounds from init_clock_gating to workarounds
2020-06-11 8:01 [Intel-gfx] [PATCH 1/6] drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds Chris Wilson
2020-06-11 8:01 ` [Intel-gfx] [PATCH 2/6] drm/i915/gt: Move ivb " Chris Wilson
2020-06-11 8:01 ` [Intel-gfx] [PATCH 3/6] drm/i915/gt: Move vlv " Chris Wilson
@ 2020-06-11 8:01 ` Chris Wilson
2020-06-11 10:04 ` Mika Kuoppala
2020-06-11 8:01 ` [Intel-gfx] [PATCH 5/6] drm/i915/gt: Move ilk " Chris Wilson
` (10 subsequent siblings)
13 siblings, 1 reply; 23+ messages in thread
From: Chris Wilson @ 2020-06-11 8:01 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
Rescue the GT workarounds from being buried inside init_clock_gating so
that we remember to apply them after a GT reset, and that they are
included in our verification that the workarounds are applied.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 41 +++++++++++++++++++++
drivers/gpu/drm/i915/intel_pm.c | 33 -----------------
2 files changed, 41 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 688ca25d79d0..7b4f3434eb6b 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -714,6 +714,45 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq)
return 0;
}
+static void
+snb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
+{
+ /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
+ wa_masked_en(wal,
+ _3D_CHICKEN,
+ _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB);
+
+ /* WaDisable_RenderCache_OperationalFlush:snb */
+ wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE);
+
+ /*
+ * BSpec recoomends 8x4 when MSAA is used,
+ * however in practice 16x4 seems fastest.
+ *
+ * Note that PS/WM thread counts depend on the WIZ hashing
+ * disable bit, which we don't touch here, but it's good
+ * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
+ */
+ wa_add(wal,
+ GEN6_GT_MODE, 0,
+ _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4),
+ GEN6_WIZ_HASHING_16x4);
+
+ wa_masked_dis(wal, CACHE_MODE_0, CM0_STC_EVICT_DISABLE_LRA_SNB);
+
+ wa_masked_en(wal,
+ _3D_CHICKEN3,
+ /* WaStripsFansDisableFastClipPerformanceFix:snb */
+ _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL |
+ /*
+ * Bspec says:
+ * "This bit must be set if 3DSTATE_CLIP clip mode is set
+ * to normal and 3DSTATE_SF number of SF output attributes
+ * is more than 16."
+ */
+ _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH);
+}
+
static void
ivb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
@@ -1154,6 +1193,8 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
vlv_gt_workarounds_init(i915, wal);
else if (IS_IVYBRIDGE(i915))
ivb_gt_workarounds_init(i915, wal);
+ else if (IS_GEN(i915, 6))
+ snb_gt_workarounds_init(i915, wal);
else if (INTEL_GEN(i915) <= 8)
return;
else
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 29abde47e987..b4bea6451418 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6993,27 +6993,6 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
I915_READ(ILK_DISPLAY_CHICKEN2) |
ILK_ELPIN_409_SELECT);
- /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
- I915_WRITE(_3D_CHICKEN,
- _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
-
- /* WaDisable_RenderCache_OperationalFlush:snb */
- I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
-
- /*
- * BSpec recoomends 8x4 when MSAA is used,
- * however in practice 16x4 seems fastest.
- *
- * Note that PS/WM thread counts depend on the WIZ hashing
- * disable bit, which we don't touch here, but it's good
- * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
- */
- I915_WRITE(GEN6_GT_MODE,
- _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
-
- I915_WRITE(CACHE_MODE_0,
- _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
-
I915_WRITE(GEN6_UCGCTL1,
I915_READ(GEN6_UCGCTL1) |
GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
@@ -7036,18 +7015,6 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
- /* WaStripsFansDisableFastClipPerformanceFix:snb */
- I915_WRITE(_3D_CHICKEN3,
- _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
-
- /*
- * Bspec says:
- * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
- * 3DSTATE_SF number of SF output attributes is more than 16."
- */
- I915_WRITE(_3D_CHICKEN3,
- _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
-
/*
* According to the spec the following bits should be
* set in order to enable memory self-refresh and fbc:
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [Intel-gfx] [PATCH 4/6] drm/i915/gt: Move snb GT workarounds from init_clock_gating to workarounds
2020-06-11 8:01 ` [Intel-gfx] [PATCH 4/6] drm/i915/gt: Move snb " Chris Wilson
@ 2020-06-11 10:04 ` Mika Kuoppala
0 siblings, 0 replies; 23+ messages in thread
From: Mika Kuoppala @ 2020-06-11 10:04 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: Chris Wilson
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Rescue the GT workarounds from being buried inside init_clock_gating so
> that we remember to apply them after a GT reset, and that they are
> included in our verification that the workarounds are applied.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 41 +++++++++++++++++++++
> drivers/gpu/drm/i915/intel_pm.c | 33 -----------------
> 2 files changed, 41 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 688ca25d79d0..7b4f3434eb6b 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -714,6 +714,45 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq)
> return 0;
> }
>
> +static void
> +snb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> +{
> + /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
> + wa_masked_en(wal,
> + _3D_CHICKEN,
> + _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB);
> +
> + /* WaDisable_RenderCache_OperationalFlush:snb */
> + wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE);
> +
> + /*
> + * BSpec recoomends 8x4 when MSAA is used,
recommends.
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> + * however in practice 16x4 seems fastest.
> + *
> + * Note that PS/WM thread counts depend on the WIZ hashing
> + * disable bit, which we don't touch here, but it's good
> + * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
> + */
> + wa_add(wal,
> + GEN6_GT_MODE, 0,
> + _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4),
> + GEN6_WIZ_HASHING_16x4);
> +
> + wa_masked_dis(wal, CACHE_MODE_0, CM0_STC_EVICT_DISABLE_LRA_SNB);
> +
> + wa_masked_en(wal,
> + _3D_CHICKEN3,
> + /* WaStripsFansDisableFastClipPerformanceFix:snb */
> + _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL |
> + /*
> + * Bspec says:
> + * "This bit must be set if 3DSTATE_CLIP clip mode is set
> + * to normal and 3DSTATE_SF number of SF output attributes
> + * is more than 16."
> + */
> + _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH);
> +}
> +
> static void
> ivb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> {
> @@ -1154,6 +1193,8 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
> vlv_gt_workarounds_init(i915, wal);
> else if (IS_IVYBRIDGE(i915))
> ivb_gt_workarounds_init(i915, wal);
> + else if (IS_GEN(i915, 6))
> + snb_gt_workarounds_init(i915, wal);
> else if (INTEL_GEN(i915) <= 8)
> return;
> else
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 29abde47e987..b4bea6451418 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6993,27 +6993,6 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
> I915_READ(ILK_DISPLAY_CHICKEN2) |
> ILK_ELPIN_409_SELECT);
>
> - /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
> - I915_WRITE(_3D_CHICKEN,
> - _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
> -
> - /* WaDisable_RenderCache_OperationalFlush:snb */
> - I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
> -
> - /*
> - * BSpec recoomends 8x4 when MSAA is used,
> - * however in practice 16x4 seems fastest.
> - *
> - * Note that PS/WM thread counts depend on the WIZ hashing
> - * disable bit, which we don't touch here, but it's good
> - * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
> - */
> - I915_WRITE(GEN6_GT_MODE,
> - _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
> -
> - I915_WRITE(CACHE_MODE_0,
> - _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
> -
> I915_WRITE(GEN6_UCGCTL1,
> I915_READ(GEN6_UCGCTL1) |
> GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
> @@ -7036,18 +7015,6 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
> GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
> GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
>
> - /* WaStripsFansDisableFastClipPerformanceFix:snb */
> - I915_WRITE(_3D_CHICKEN3,
> - _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
> -
> - /*
> - * Bspec says:
> - * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
> - * 3DSTATE_SF number of SF output attributes is more than 16."
> - */
> - I915_WRITE(_3D_CHICKEN3,
> - _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
> -
> /*
> * According to the spec the following bits should be
> * set in order to enable memory self-refresh and fbc:
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread
* [Intel-gfx] [PATCH 5/6] drm/i915/gt: Move ilk GT workarounds from init_clock_gating to workarounds
2020-06-11 8:01 [Intel-gfx] [PATCH 1/6] drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds Chris Wilson
` (2 preceding siblings ...)
2020-06-11 8:01 ` [Intel-gfx] [PATCH 4/6] drm/i915/gt: Move snb " Chris Wilson
@ 2020-06-11 8:01 ` Chris Wilson
2020-06-11 10:05 ` Mika Kuoppala
2020-06-11 8:01 ` [Intel-gfx] [PATCH 6/6] drm/i915/gt: Move gen4 " Chris Wilson
` (9 subsequent siblings)
13 siblings, 1 reply; 23+ messages in thread
From: Chris Wilson @ 2020-06-11 8:01 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
Rescue the GT workarounds from being buried inside init_clock_gating so
that we remember to apply them after a GT reset, and that they are
included in our verification that the workarounds are applied.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 14 ++++++++++++++
drivers/gpu/drm/i915/intel_pm.c | 10 ----------
2 files changed, 14 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 7b4f3434eb6b..f8b9e104378e 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -714,6 +714,18 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq)
return 0;
}
+static void
+ilk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
+{
+ wa_masked_en(wal,_3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED);
+
+ /* WaDisableRenderCachePipelinedFlush:ilk */
+ wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE);
+
+ /* WaDisable_RenderCache_OperationalFlush:ilk */
+ wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE);
+}
+
static void
snb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
@@ -1195,6 +1207,8 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
ivb_gt_workarounds_init(i915, wal);
else if (IS_GEN(i915, 6))
snb_gt_workarounds_init(i915, wal);
+ else if (IS_GEN(i915, 5))
+ ilk_gt_workarounds_init(i915, wal);
else if (INTEL_GEN(i915) <= 8)
return;
else
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b4bea6451418..7d82a7144a13 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6921,16 +6921,6 @@ static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
I915_WRITE(ILK_DISPLAY_CHICKEN2,
I915_READ(ILK_DISPLAY_CHICKEN2) |
ILK_ELPIN_409_SELECT);
- I915_WRITE(_3D_CHICKEN2,
- _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
- _3D_CHICKEN2_WM_READ_PIPELINED);
-
- /* WaDisableRenderCachePipelinedFlush:ilk */
- I915_WRITE(CACHE_MODE_0,
- _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
-
- /* WaDisable_RenderCache_OperationalFlush:ilk */
- I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
g4x_disable_trickle_feed(dev_priv);
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [Intel-gfx] [PATCH 5/6] drm/i915/gt: Move ilk GT workarounds from init_clock_gating to workarounds
2020-06-11 8:01 ` [Intel-gfx] [PATCH 5/6] drm/i915/gt: Move ilk " Chris Wilson
@ 2020-06-11 10:05 ` Mika Kuoppala
0 siblings, 0 replies; 23+ messages in thread
From: Mika Kuoppala @ 2020-06-11 10:05 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: Chris Wilson
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Rescue the GT workarounds from being buried inside init_clock_gating so
> that we remember to apply them after a GT reset, and that they are
> included in our verification that the workarounds are applied.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 14 ++++++++++++++
> drivers/gpu/drm/i915/intel_pm.c | 10 ----------
> 2 files changed, 14 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 7b4f3434eb6b..f8b9e104378e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -714,6 +714,18 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq)
> return 0;
> }
>
> +static void
> +ilk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> +{
> + wa_masked_en(wal,_3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED);
> +
> + /* WaDisableRenderCachePipelinedFlush:ilk */
> + wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE);
> +
> + /* WaDisable_RenderCache_OperationalFlush:ilk */
> + wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE);
> +}
> +
> static void
> snb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> {
> @@ -1195,6 +1207,8 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
> ivb_gt_workarounds_init(i915, wal);
> else if (IS_GEN(i915, 6))
> snb_gt_workarounds_init(i915, wal);
> + else if (IS_GEN(i915, 5))
> + ilk_gt_workarounds_init(i915, wal);
> else if (INTEL_GEN(i915) <= 8)
> return;
> else
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index b4bea6451418..7d82a7144a13 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6921,16 +6921,6 @@ static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
> I915_WRITE(ILK_DISPLAY_CHICKEN2,
> I915_READ(ILK_DISPLAY_CHICKEN2) |
> ILK_ELPIN_409_SELECT);
> - I915_WRITE(_3D_CHICKEN2,
> - _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
> - _3D_CHICKEN2_WM_READ_PIPELINED);
> -
> - /* WaDisableRenderCachePipelinedFlush:ilk */
> - I915_WRITE(CACHE_MODE_0,
> - _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
> -
> - /* WaDisable_RenderCache_OperationalFlush:ilk */
> - I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
>
> g4x_disable_trickle_feed(dev_priv);
>
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread
* [Intel-gfx] [PATCH 6/6] drm/i915/gt: Move gen4 GT workarounds from init_clock_gating to workarounds
2020-06-11 8:01 [Intel-gfx] [PATCH 1/6] drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds Chris Wilson
` (3 preceding siblings ...)
2020-06-11 8:01 ` [Intel-gfx] [PATCH 5/6] drm/i915/gt: Move ilk " Chris Wilson
@ 2020-06-11 8:01 ` Chris Wilson
2020-06-11 10:07 ` Mika Kuoppala
2020-06-11 9:06 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] drm/i915/gt: Move hsw " Patchwork
` (8 subsequent siblings)
13 siblings, 1 reply; 23+ messages in thread
From: Chris Wilson @ 2020-06-11 8:01 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
Rescue the GT workarounds from being buried inside init_clock_gating so
that we remember to apply them after a GT reset, and that they are
included in our verification that the workarounds are applied.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 27 +++++++++++++++++----
drivers/gpu/drm/i915/intel_pm.c | 15 ------------
2 files changed, 22 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index f8b9e104378e..7b4be64585c3 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -715,15 +715,28 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq)
}
static void
-ilk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
+gen4_gt_workarounds_init(struct drm_i915_private *i915,
+ struct i915_wa_list *wal)
{
- wa_masked_en(wal,_3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED);
+ /* WaDisable_RenderCache_OperationalFlush:gen4,ilk */
+ wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE);
+}
+
+static void
+g4x_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
+{
+ gen4_gt_workarounds_init(i915, wal);
- /* WaDisableRenderCachePipelinedFlush:ilk */
+ /* WaDisableRenderCachePipelinedFlush:g4x,ilk */
wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE);
+}
- /* WaDisable_RenderCache_OperationalFlush:ilk */
- wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE);
+static void
+ilk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
+{
+ g4x_gt_workarounds_init(i915, wal);
+
+ wa_masked_en(wal,_3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED);
}
static void
@@ -1209,6 +1222,10 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
snb_gt_workarounds_init(i915, wal);
else if (IS_GEN(i915, 5))
ilk_gt_workarounds_init(i915, wal);
+ else if (IS_G4X(i915))
+ g4x_gt_workarounds_init(i915, wal);
+ else if (IS_GEN(i915, 4))
+ gen4_gt_workarounds_init(i915, wal);
else if (INTEL_GEN(i915) <= 8)
return;
else
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7d82a7144a13..2a32d6230795 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7399,13 +7399,6 @@ static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
- /* WaDisableRenderCachePipelinedFlush */
- I915_WRITE(CACHE_MODE_0,
- _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
-
- /* WaDisable_RenderCache_OperationalFlush:g4x */
- I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
-
g4x_disable_trickle_feed(dev_priv);
}
@@ -7421,11 +7414,6 @@ static void i965gm_init_clock_gating(struct drm_i915_private *dev_priv)
intel_uncore_write(uncore,
MI_ARB_STATE,
_MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
-
- /* WaDisable_RenderCache_OperationalFlush:gen4 */
- intel_uncore_write(uncore,
- CACHE_MODE_0,
- _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
}
static void i965g_init_clock_gating(struct drm_i915_private *dev_priv)
@@ -7438,9 +7426,6 @@ static void i965g_init_clock_gating(struct drm_i915_private *dev_priv)
I915_WRITE(RENCLK_GATE_D2, 0);
I915_WRITE(MI_ARB_STATE,
_MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
-
- /* WaDisable_RenderCache_OperationalFlush:gen4 */
- I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
}
static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [Intel-gfx] [PATCH 6/6] drm/i915/gt: Move gen4 GT workarounds from init_clock_gating to workarounds
2020-06-11 8:01 ` [Intel-gfx] [PATCH 6/6] drm/i915/gt: Move gen4 " Chris Wilson
@ 2020-06-11 10:07 ` Mika Kuoppala
0 siblings, 0 replies; 23+ messages in thread
From: Mika Kuoppala @ 2020-06-11 10:07 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: Chris Wilson
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Rescue the GT workarounds from being buried inside init_clock_gating so
> that we remember to apply them after a GT reset, and that they are
> included in our verification that the workarounds are applied.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 27 +++++++++++++++++----
> drivers/gpu/drm/i915/intel_pm.c | 15 ------------
> 2 files changed, 22 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index f8b9e104378e..7b4be64585c3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -715,15 +715,28 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq)
> }
>
> static void
> -ilk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> +gen4_gt_workarounds_init(struct drm_i915_private *i915,
> + struct i915_wa_list *wal)
> {
> - wa_masked_en(wal,_3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED);
> + /* WaDisable_RenderCache_OperationalFlush:gen4,ilk */
> + wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE);
> +}
> +
> +static void
> +g4x_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> +{
> + gen4_gt_workarounds_init(i915, wal);
>
> - /* WaDisableRenderCachePipelinedFlush:ilk */
> + /* WaDisableRenderCachePipelinedFlush:g4x,ilk */
> wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE);
> +}
>
> - /* WaDisable_RenderCache_OperationalFlush:ilk */
> - wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE);
> +static void
> +ilk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> +{
> + g4x_gt_workarounds_init(i915, wal);
> +
> + wa_masked_en(wal,_3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED);
> }
>
> static void
> @@ -1209,6 +1222,10 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
> snb_gt_workarounds_init(i915, wal);
> else if (IS_GEN(i915, 5))
> ilk_gt_workarounds_init(i915, wal);
> + else if (IS_G4X(i915))
> + g4x_gt_workarounds_init(i915, wal);
> + else if (IS_GEN(i915, 4))
> + gen4_gt_workarounds_init(i915, wal);
> else if (INTEL_GEN(i915) <= 8)
> return;
> else
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 7d82a7144a13..2a32d6230795 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7399,13 +7399,6 @@ static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
> dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
> I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
>
> - /* WaDisableRenderCachePipelinedFlush */
> - I915_WRITE(CACHE_MODE_0,
> - _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
> -
> - /* WaDisable_RenderCache_OperationalFlush:g4x */
> - I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
> -
> g4x_disable_trickle_feed(dev_priv);
> }
>
> @@ -7421,11 +7414,6 @@ static void i965gm_init_clock_gating(struct drm_i915_private *dev_priv)
> intel_uncore_write(uncore,
> MI_ARB_STATE,
> _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
> -
> - /* WaDisable_RenderCache_OperationalFlush:gen4 */
> - intel_uncore_write(uncore,
> - CACHE_MODE_0,
> - _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
> }
>
> static void i965g_init_clock_gating(struct drm_i915_private *dev_priv)
> @@ -7438,9 +7426,6 @@ static void i965g_init_clock_gating(struct drm_i915_private *dev_priv)
> I915_WRITE(RENCLK_GATE_D2, 0);
> I915_WRITE(MI_ARB_STATE,
> _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
> -
> - /* WaDisable_RenderCache_OperationalFlush:gen4 */
> - I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
> }
>
> static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds
2020-06-11 8:01 [Intel-gfx] [PATCH 1/6] drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds Chris Wilson
` (4 preceding siblings ...)
2020-06-11 8:01 ` [Intel-gfx] [PATCH 6/6] drm/i915/gt: Move gen4 " Chris Wilson
@ 2020-06-11 9:06 ` Patchwork
2020-06-11 9:07 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (7 subsequent siblings)
13 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2020-06-11 9:06 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/6] drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds
URL : https://patchwork.freedesktop.org/series/78214/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d733ff00e147 drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds
e66a89d1b959 drm/i915/gt: Move ivb GT workarounds from init_clock_gating to workarounds
-:25: ERROR:SPACING: space required after that ',' (ctx:VxV)
#25: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:721:
+ wa_masked_en(wal,_3D_CHICKEN3, _3D_CHICKEN_SF_DISABLE_OBJEND_CULL);
^
total: 1 errors, 0 warnings, 0 checks, 153 lines checked
a5568a200839 drm/i915/gt: Move vlv GT workarounds from init_clock_gating to workarounds
-:25: ERROR:SPACING: space required after that ',' (ctx:VxV)
#25: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:781:
+ wa_masked_en(wal,_3D_CHICKEN3, _3D_CHICKEN_SF_DISABLE_OBJEND_CULL);
^
total: 1 errors, 0 warnings, 0 checks, 161 lines checked
2bb63f1a6887 drm/i915/gt: Move snb GT workarounds from init_clock_gating to workarounds
04d5cd5657aa drm/i915/gt: Move ilk GT workarounds from init_clock_gating to workarounds
-:24: ERROR:SPACING: space required after that ',' (ctx:VxV)
#24: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:720:
+ wa_masked_en(wal,_3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED);
^
total: 1 errors, 0 warnings, 0 checks, 42 lines checked
bb704549ca19 drm/i915/gt: Move gen4 GT workarounds from init_clock_gating to workarounds
-:47: ERROR:SPACING: space required after that ',' (ctx:VxV)
#47: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:739:
+ wa_masked_en(wal,_3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED);
^
total: 1 errors, 0 warnings, 0 checks, 76 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/6] drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds
2020-06-11 8:01 [Intel-gfx] [PATCH 1/6] drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds Chris Wilson
` (5 preceding siblings ...)
2020-06-11 9:06 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] drm/i915/gt: Move hsw " Patchwork
@ 2020-06-11 9:07 ` Patchwork
2020-06-11 9:25 ` [Intel-gfx] [PATCH 1/6] " Mika Kuoppala
` (6 subsequent siblings)
13 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2020-06-11 9:07 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/6] drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds
URL : https://patchwork.freedesktop.org/series/78214/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_display.c:1222:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/display/intel_display.c:1225:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/display/intel_display.c:1228:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/display/intel_display.c:1231:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2275:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2276:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2277:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2278:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2279:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression
+drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression
+drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression
+drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [Intel-gfx] [PATCH 1/6] drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds
2020-06-11 8:01 [Intel-gfx] [PATCH 1/6] drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds Chris Wilson
` (6 preceding siblings ...)
2020-06-11 9:07 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2020-06-11 9:25 ` Mika Kuoppala
2020-06-11 9:28 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/6] " Patchwork
` (5 subsequent siblings)
13 siblings, 0 replies; 23+ messages in thread
From: Mika Kuoppala @ 2020-06-11 9:25 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: Chris Wilson
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Rescue the GT workarounds from being buried inside init_clock_gating so
> that we remember to apply them after a GT reset, and that they are
> included in our verification that the workarounds are applied.
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2011
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 48 +++++++++++++++++++++
> drivers/gpu/drm/i915/intel_pm.c | 39 +----------------
> 2 files changed, 50 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 3eec31c5a714..39f070bff09d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -178,6 +178,12 @@ wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
> wa_write_masked_or(wal, reg, set, set);
> }
>
> +static void
> +wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr)
> +{
> + wa_write_masked_or(wal, reg, clr, 0);
> +}
> +
> static void
> wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
> {
> @@ -708,6 +714,46 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq)
> return 0;
> }
>
> +static void
> +hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> +{
> + /* L3 caching of data atomics doesn't work -- disable it. */
> + wa_write_or(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
Just noted here is a change. We cleared everything else but this
previously.
-Mika
> +
> + wa_add(wal,
> + HSW_ROW_CHICKEN3, 0,
> + _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE),
> + 0 /* XXX does this reg exist? */);
> +
> + /* WaVSRefCountFullforceMissDisable:hsw */
> + wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME);
> +
> + wa_masked_dis(wal,
> + CACHE_MODE_0_GEN7,
> + /* WaDisable_RenderCache_OperationalFlush:hsw */
> + RC_OP_FLUSH_ENABLE |
> + /* enable HiZ Raw Stall Optimization */
> + HIZ_RAW_STALL_OPT_DISABLE);
> +
> + /* WaDisable4x2SubspanOptimization:hsw */
> + wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
> +
> + /*
> + * BSpec recommends 8x4 when MSAA is used,
> + * however in practice 16x4 seems fastest.
> + *
> + * Note that PS/WM thread counts depend on the WIZ hashing
> + * disable bit, which we don't touch here, but it's good
> + * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
> + */
> + wa_add(wal, GEN7_GT_MODE, 0,
> + _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4),
> + GEN6_WIZ_HASHING_16x4);
> +
> + /* WaSampleCChickenBitEnable:hsw */
> + wa_masked_en(wal, HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE);
> +}
> +
> static void
> gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> {
> @@ -985,6 +1031,8 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
> bxt_gt_workarounds_init(i915, wal);
> else if (IS_SKYLAKE(i915))
> skl_gt_workarounds_init(i915, wal);
> + else if (IS_HASWELL(i915))
> + hsw_gt_workarounds_init(i915, wal);
> else if (INTEL_GEN(i915) <= 8)
> return;
> else
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 26b670fa3f88..249ee720874c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7321,45 +7321,10 @@ static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
>
> static void hsw_init_clock_gating(struct drm_i915_private *dev_priv)
> {
> - /* L3 caching of data atomics doesn't work -- disable it. */
> - I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
> - I915_WRITE(HSW_ROW_CHICKEN3,
> - _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
> -
> /* This is required by WaCatErrorRejectionIssue:hsw */
> I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
> - I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
> - GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
> -
> - /* WaVSRefCountFullforceMissDisable:hsw */
> - I915_WRITE(GEN7_FF_THREAD_MODE,
> - I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
> -
> - /* WaDisable_RenderCache_OperationalFlush:hsw */
> - I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
> -
> - /* enable HiZ Raw Stall Optimization */
> - I915_WRITE(CACHE_MODE_0_GEN7,
> - _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
> -
> - /* WaDisable4x2SubspanOptimization:hsw */
> - I915_WRITE(CACHE_MODE_1,
> - _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
> -
> - /*
> - * BSpec recommends 8x4 when MSAA is used,
> - * however in practice 16x4 seems fastest.
> - *
> - * Note that PS/WM thread counts depend on the WIZ hashing
> - * disable bit, which we don't touch here, but it's good
> - * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
> - */
> - I915_WRITE(GEN7_GT_MODE,
> - _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
> -
> - /* WaSampleCChickenBitEnable:hsw */
> - I915_WRITE(HALF_SLICE_CHICKEN3,
> - _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
> + I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
> + GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
>
> /* WaSwitchSolVfFArbitrationPriority:hsw */
> I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds
2020-06-11 8:01 [Intel-gfx] [PATCH 1/6] drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds Chris Wilson
` (7 preceding siblings ...)
2020-06-11 9:25 ` [Intel-gfx] [PATCH 1/6] " Mika Kuoppala
@ 2020-06-11 9:28 ` Patchwork
2020-06-11 9:30 ` [Intel-gfx] [PATCH] " Chris Wilson
` (4 subsequent siblings)
13 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2020-06-11 9:28 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/6] drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds
URL : https://patchwork.freedesktop.org/series/78214/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8614 -> Patchwork_17925
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17925/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_17925:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@runner@aborted:
- {fi-kbl-7560u}: NOTRUN -> [FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17925/fi-kbl-7560u/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_17925 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s0:
- fi-tgl-u2: [PASS][2] -> [FAIL][3] ([i915#1888])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-tgl-u2/igt@gem_exec_suspend@basic-s0.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17925/fi-tgl-u2/igt@gem_exec_suspend@basic-s0.html
* igt@i915_module_load@reload:
- fi-byt-j1900: [PASS][4] -> [DMESG-WARN][5] ([i915#1982]) +1 similar issue
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-byt-j1900/igt@i915_module_load@reload.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17925/fi-byt-j1900/igt@i915_module_load@reload.html
- fi-icl-guc: [PASS][6] -> [DMESG-WARN][7] ([i915#1982])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-icl-guc/igt@i915_module_load@reload.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17925/fi-icl-guc/igt@i915_module_load@reload.html
- fi-icl-y: [PASS][8] -> [DMESG-WARN][9] ([i915#1982])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-icl-y/igt@i915_module_load@reload.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17925/fi-icl-y/igt@i915_module_load@reload.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [PASS][10] -> [DMESG-WARN][11] ([i915#1982])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17925/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_pm_rpm@module-reload:
- fi-glk-dsi: [PASS][12] -> [DMESG-WARN][13] ([i915#1982])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-glk-dsi/igt@i915_pm_rpm@module-reload.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17925/fi-glk-dsi/igt@i915_pm_rpm@module-reload.html
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-tgl-u2: [PASS][14] -> [DMESG-WARN][15] ([i915#402])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-tgl-u2/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17925/fi-tgl-u2/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
#### Possible fixes ####
* igt@i915_module_load@reload:
- fi-apl-guc: [DMESG-WARN][16] ([i915#1982]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-apl-guc/igt@i915_module_load@reload.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17925/fi-apl-guc/igt@i915_module_load@reload.html
* igt@i915_pm_rpm@module-reload:
- fi-byt-j1900: [DMESG-WARN][18] ([i915#1982]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17925/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
* igt@kms_busy@basic@flip:
- fi-kbl-x1275: [DMESG-WARN][20] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-kbl-x1275/igt@kms_busy@basic@flip.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17925/fi-kbl-x1275/igt@kms_busy@basic@flip.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- fi-icl-u2: [DMESG-WARN][22] ([i915#1982]) -> [PASS][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17925/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
#### Warnings ####
* igt@gem_exec_suspend@basic-s0:
- fi-kbl-x1275: [DMESG-WARN][24] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][25] ([i915#62] / [i915#92]) +4 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17925/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
* igt@kms_flip@basic-flip-vs-dpms@a-dp1:
- fi-kbl-x1275: [DMESG-WARN][26] ([i915#62] / [i915#92]) -> [DMESG-WARN][27] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-dpms@a-dp1.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17925/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-dpms@a-dp1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (49 -> 43)
------------------------------
Additional (1): fi-kbl-7560u
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_8614 -> Patchwork_17925
CI-20190529: 20190529
CI_DRM_8614: 207862f18909166ffcf9e288ff796b756ae82d1c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5702: d16ad07e7f2a028e14d61f570931c87fa5ce404c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17925: bb704549ca1937377b3595b79d74f18f875942c9 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
bb704549ca19 drm/i915/gt: Move gen4 GT workarounds from init_clock_gating to workarounds
04d5cd5657aa drm/i915/gt: Move ilk GT workarounds from init_clock_gating to workarounds
2bb63f1a6887 drm/i915/gt: Move snb GT workarounds from init_clock_gating to workarounds
a5568a200839 drm/i915/gt: Move vlv GT workarounds from init_clock_gating to workarounds
e66a89d1b959 drm/i915/gt: Move ivb GT workarounds from init_clock_gating to workarounds
d733ff00e147 drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17925/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread* [Intel-gfx] [PATCH] drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds
2020-06-11 8:01 [Intel-gfx] [PATCH 1/6] drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds Chris Wilson
` (8 preceding siblings ...)
2020-06-11 9:28 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/6] " Patchwork
@ 2020-06-11 9:30 ` Chris Wilson
2020-06-11 9:52 ` Mika Kuoppala
2020-06-11 9:56 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds (rev2) Patchwork
` (3 subsequent siblings)
13 siblings, 1 reply; 23+ messages in thread
From: Chris Wilson @ 2020-06-11 9:30 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
Rescue the GT workarounds from being buried inside init_clock_gating so
that we remember to apply them after a GT reset, and that they are
included in our verification that the workarounds are applied.
v2: Leave HSW_SCRATCH to set an explicit value, not or in our disable
bit.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2011
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 48 +++++++++++++++++++++
drivers/gpu/drm/i915/intel_pm.c | 39 +----------------
2 files changed, 50 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3eec31c5a714..fb337e2d8a27 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -178,6 +178,12 @@ wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
wa_write_masked_or(wal, reg, set, set);
}
+static void
+wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr)
+{
+ wa_write_masked_or(wal, reg, clr, 0);
+}
+
static void
wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
{
@@ -708,6 +714,46 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq)
return 0;
}
+static void
+hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
+{
+ /* L3 caching of data atomics doesn't work -- disable it. */
+ wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
+
+ wa_add(wal,
+ HSW_ROW_CHICKEN3, 0,
+ _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE),
+ 0 /* XXX does this reg exist? */);
+
+ /* WaVSRefCountFullforceMissDisable:hsw */
+ wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME);
+
+ wa_masked_dis(wal,
+ CACHE_MODE_0_GEN7,
+ /* WaDisable_RenderCache_OperationalFlush:hsw */
+ RC_OP_FLUSH_ENABLE |
+ /* enable HiZ Raw Stall Optimization */
+ HIZ_RAW_STALL_OPT_DISABLE);
+
+ /* WaDisable4x2SubspanOptimization:hsw */
+ wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
+
+ /*
+ * BSpec recommends 8x4 when MSAA is used,
+ * however in practice 16x4 seems fastest.
+ *
+ * Note that PS/WM thread counts depend on the WIZ hashing
+ * disable bit, which we don't touch here, but it's good
+ * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
+ */
+ wa_add(wal, GEN7_GT_MODE, 0,
+ _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4),
+ GEN6_WIZ_HASHING_16x4);
+
+ /* WaSampleCChickenBitEnable:hsw */
+ wa_masked_en(wal, HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE);
+}
+
static void
gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
@@ -985,6 +1031,8 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
bxt_gt_workarounds_init(i915, wal);
else if (IS_SKYLAKE(i915))
skl_gt_workarounds_init(i915, wal);
+ else if (IS_HASWELL(i915))
+ hsw_gt_workarounds_init(i915, wal);
else if (INTEL_GEN(i915) <= 8)
return;
else
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 26b670fa3f88..249ee720874c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7321,45 +7321,10 @@ static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
static void hsw_init_clock_gating(struct drm_i915_private *dev_priv)
{
- /* L3 caching of data atomics doesn't work -- disable it. */
- I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
- I915_WRITE(HSW_ROW_CHICKEN3,
- _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
-
/* This is required by WaCatErrorRejectionIssue:hsw */
I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
- I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
- GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
-
- /* WaVSRefCountFullforceMissDisable:hsw */
- I915_WRITE(GEN7_FF_THREAD_MODE,
- I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
-
- /* WaDisable_RenderCache_OperationalFlush:hsw */
- I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
-
- /* enable HiZ Raw Stall Optimization */
- I915_WRITE(CACHE_MODE_0_GEN7,
- _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
-
- /* WaDisable4x2SubspanOptimization:hsw */
- I915_WRITE(CACHE_MODE_1,
- _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
-
- /*
- * BSpec recommends 8x4 when MSAA is used,
- * however in practice 16x4 seems fastest.
- *
- * Note that PS/WM thread counts depend on the WIZ hashing
- * disable bit, which we don't touch here, but it's good
- * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
- */
- I915_WRITE(GEN7_GT_MODE,
- _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
-
- /* WaSampleCChickenBitEnable:hsw */
- I915_WRITE(HALF_SLICE_CHICKEN3,
- _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
+ I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
+ GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
/* WaSwitchSolVfFArbitrationPriority:hsw */
I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [Intel-gfx] [PATCH] drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds
2020-06-11 9:30 ` [Intel-gfx] [PATCH] " Chris Wilson
@ 2020-06-11 9:52 ` Mika Kuoppala
0 siblings, 0 replies; 23+ messages in thread
From: Mika Kuoppala @ 2020-06-11 9:52 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: Chris Wilson
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Rescue the GT workarounds from being buried inside init_clock_gating so
> that we remember to apply them after a GT reset, and that they are
> included in our verification that the workarounds are applied.
>
> v2: Leave HSW_SCRATCH to set an explicit value, not or in our disable
> bit.
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2011
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 48 +++++++++++++++++++++
> drivers/gpu/drm/i915/intel_pm.c | 39 +----------------
> 2 files changed, 50 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 3eec31c5a714..fb337e2d8a27 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -178,6 +178,12 @@ wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
> wa_write_masked_or(wal, reg, set, set);
> }
>
> +static void
> +wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr)
> +{
> + wa_write_masked_or(wal, reg, clr, 0);
> +}
> +
> static void
> wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
> {
> @@ -708,6 +714,46 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq)
> return 0;
> }
>
> +static void
> +hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> +{
> + /* L3 caching of data atomics doesn't work -- disable it. */
> + wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
> +
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> + wa_add(wal,
> + HSW_ROW_CHICKEN3, 0,
> + _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE),
> + 0 /* XXX does this reg exist? */);
> +
> + /* WaVSRefCountFullforceMissDisable:hsw */
> + wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME);
> +
> + wa_masked_dis(wal,
> + CACHE_MODE_0_GEN7,
> + /* WaDisable_RenderCache_OperationalFlush:hsw */
> + RC_OP_FLUSH_ENABLE |
> + /* enable HiZ Raw Stall Optimization */
> + HIZ_RAW_STALL_OPT_DISABLE);
> +
> + /* WaDisable4x2SubspanOptimization:hsw */
> + wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
> +
> + /*
> + * BSpec recommends 8x4 when MSAA is used,
> + * however in practice 16x4 seems fastest.
> + *
> + * Note that PS/WM thread counts depend on the WIZ hashing
> + * disable bit, which we don't touch here, but it's good
> + * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
> + */
> + wa_add(wal, GEN7_GT_MODE, 0,
> + _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4),
> + GEN6_WIZ_HASHING_16x4);
> +
> + /* WaSampleCChickenBitEnable:hsw */
> + wa_masked_en(wal, HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE);
> +}
> +
> static void
> gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> {
> @@ -985,6 +1031,8 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
> bxt_gt_workarounds_init(i915, wal);
> else if (IS_SKYLAKE(i915))
> skl_gt_workarounds_init(i915, wal);
> + else if (IS_HASWELL(i915))
> + hsw_gt_workarounds_init(i915, wal);
> else if (INTEL_GEN(i915) <= 8)
> return;
> else
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 26b670fa3f88..249ee720874c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7321,45 +7321,10 @@ static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
>
> static void hsw_init_clock_gating(struct drm_i915_private *dev_priv)
> {
> - /* L3 caching of data atomics doesn't work -- disable it. */
> - I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
> - I915_WRITE(HSW_ROW_CHICKEN3,
> - _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
> -
> /* This is required by WaCatErrorRejectionIssue:hsw */
> I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
> - I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
> - GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
> -
> - /* WaVSRefCountFullforceMissDisable:hsw */
> - I915_WRITE(GEN7_FF_THREAD_MODE,
> - I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
> -
> - /* WaDisable_RenderCache_OperationalFlush:hsw */
> - I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
> -
> - /* enable HiZ Raw Stall Optimization */
> - I915_WRITE(CACHE_MODE_0_GEN7,
> - _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
> -
> - /* WaDisable4x2SubspanOptimization:hsw */
> - I915_WRITE(CACHE_MODE_1,
> - _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
> -
> - /*
> - * BSpec recommends 8x4 when MSAA is used,
> - * however in practice 16x4 seems fastest.
> - *
> - * Note that PS/WM thread counts depend on the WIZ hashing
> - * disable bit, which we don't touch here, but it's good
> - * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
> - */
> - I915_WRITE(GEN7_GT_MODE,
> - _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
> -
> - /* WaSampleCChickenBitEnable:hsw */
> - I915_WRITE(HALF_SLICE_CHICKEN3,
> - _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
> + I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
> + GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
>
> /* WaSwitchSolVfFArbitrationPriority:hsw */
> I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
> --
> 2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds (rev2)
2020-06-11 8:01 [Intel-gfx] [PATCH 1/6] drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds Chris Wilson
` (9 preceding siblings ...)
2020-06-11 9:30 ` [Intel-gfx] [PATCH] " Chris Wilson
@ 2020-06-11 9:56 ` Patchwork
2020-06-11 9:58 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
13 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2020-06-11 9:56 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds (rev2)
URL : https://patchwork.freedesktop.org/series/78214/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a9a19ef20e69 drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds
961e1996e0a8 drm/i915/gt: Move ivb GT workarounds from init_clock_gating to workarounds
-:25: ERROR:SPACING: space required after that ',' (ctx:VxV)
#25: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:721:
+ wa_masked_en(wal,_3D_CHICKEN3, _3D_CHICKEN_SF_DISABLE_OBJEND_CULL);
^
total: 1 errors, 0 warnings, 0 checks, 153 lines checked
68e40d9f98c3 drm/i915/gt: Move vlv GT workarounds from init_clock_gating to workarounds
-:25: ERROR:SPACING: space required after that ',' (ctx:VxV)
#25: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:781:
+ wa_masked_en(wal,_3D_CHICKEN3, _3D_CHICKEN_SF_DISABLE_OBJEND_CULL);
^
total: 1 errors, 0 warnings, 0 checks, 161 lines checked
79f6193f4ff2 drm/i915/gt: Move snb GT workarounds from init_clock_gating to workarounds
3dde510c6178 drm/i915/gt: Move ilk GT workarounds from init_clock_gating to workarounds
-:24: ERROR:SPACING: space required after that ',' (ctx:VxV)
#24: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:720:
+ wa_masked_en(wal,_3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED);
^
total: 1 errors, 0 warnings, 0 checks, 42 lines checked
66c89c81b814 drm/i915/gt: Move gen4 GT workarounds from init_clock_gating to workarounds
-:47: ERROR:SPACING: space required after that ',' (ctx:VxV)
#47: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:739:
+ wa_masked_en(wal,_3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED);
^
total: 1 errors, 0 warnings, 0 checks, 76 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds (rev2)
2020-06-11 8:01 [Intel-gfx] [PATCH 1/6] drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds Chris Wilson
` (10 preceding siblings ...)
2020-06-11 9:56 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds (rev2) Patchwork
@ 2020-06-11 9:58 ` Patchwork
2020-06-11 10:21 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-06-11 13:43 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
13 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2020-06-11 9:58 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds (rev2)
URL : https://patchwork.freedesktop.org/series/78214/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_display.c:1222:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/display/intel_display.c:1225:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/display/intel_display.c:1228:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/display/intel_display.c:1231:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2275:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2276:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2277:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2278:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2279:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression
+drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression
+drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression
+drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds (rev2)
2020-06-11 8:01 [Intel-gfx] [PATCH 1/6] drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds Chris Wilson
` (11 preceding siblings ...)
2020-06-11 9:58 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2020-06-11 10:21 ` Patchwork
2020-06-11 13:43 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
13 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2020-06-11 10:21 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds (rev2)
URL : https://patchwork.freedesktop.org/series/78214/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8614 -> Patchwork_17926
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_17926:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@runner@aborted:
- {fi-kbl-7560u}: NOTRUN -> [FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/fi-kbl-7560u/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_17926 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s0:
- fi-tgl-u2: [PASS][2] -> [FAIL][3] ([i915#1888])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-tgl-u2/igt@gem_exec_suspend@basic-s0.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/fi-tgl-u2/igt@gem_exec_suspend@basic-s0.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [PASS][4] -> [DMESG-WARN][5] ([i915#1982])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_selftest@live@gem_contexts:
- fi-tgl-u2: [PASS][6] -> [INCOMPLETE][7] ([i915#1932])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-tgl-u2/igt@i915_selftest@live@gem_contexts.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/fi-tgl-u2/igt@i915_selftest@live@gem_contexts.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-icl-guc: [PASS][8] -> [DMESG-WARN][9] ([i915#1982])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-icl-guc/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/fi-icl-guc/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
#### Possible fixes ####
* igt@i915_module_load@reload:
- fi-apl-guc: [DMESG-WARN][10] ([i915#1982]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-apl-guc/igt@i915_module_load@reload.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/fi-apl-guc/igt@i915_module_load@reload.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- {fi-tgl-dsi}: [DMESG-WARN][12] ([i915#1982]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-tgl-dsi/igt@i915_pm_rpm@basic-pci-d3-state.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/fi-tgl-dsi/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_pm_rpm@module-reload:
- fi-byt-j1900: [DMESG-WARN][14] ([i915#1982]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@gt_lrc:
- fi-tgl-u2: [DMESG-FAIL][16] ([i915#1233]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-tgl-u2/igt@i915_selftest@live@gt_lrc.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/fi-tgl-u2/igt@i915_selftest@live@gt_lrc.html
* igt@kms_busy@basic@flip:
- fi-kbl-x1275: [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-kbl-x1275/igt@kms_busy@basic@flip.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/fi-kbl-x1275/igt@kms_busy@basic@flip.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-bsw-n3050: [DMESG-WARN][20] ([i915#1982]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
- fi-bsw-kefka: [DMESG-WARN][22] ([i915#1982]) -> [PASS][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_flip@basic-flip-vs-wf_vblank@b-edp1:
- fi-icl-u2: [DMESG-WARN][24] ([i915#1982]) -> [PASS][25] +1 similar issue
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@b-edp1.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@b-edp1.html
#### Warnings ####
* igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size:
- fi-kbl-x1275: [DMESG-WARN][26] ([i915#62] / [i915#92]) -> [DMESG-WARN][27] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html
* igt@kms_flip@basic-flip-vs-modeset@a-dp1:
- fi-kbl-x1275: [DMESG-WARN][28] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][29] ([i915#62] / [i915#92]) +5 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset@a-dp1.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset@a-dp1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1233]: https://gitlab.freedesktop.org/drm/intel/issues/1233
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1932]: https://gitlab.freedesktop.org/drm/intel/issues/1932
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (49 -> 43)
------------------------------
Additional (1): fi-kbl-7560u
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_8614 -> Patchwork_17926
CI-20190529: 20190529
CI_DRM_8614: 207862f18909166ffcf9e288ff796b756ae82d1c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5702: d16ad07e7f2a028e14d61f570931c87fa5ce404c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17926: 66c89c81b8144175aa4d9682e650323658fddcce @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
66c89c81b814 drm/i915/gt: Move gen4 GT workarounds from init_clock_gating to workarounds
3dde510c6178 drm/i915/gt: Move ilk GT workarounds from init_clock_gating to workarounds
79f6193f4ff2 drm/i915/gt: Move snb GT workarounds from init_clock_gating to workarounds
68e40d9f98c3 drm/i915/gt: Move vlv GT workarounds from init_clock_gating to workarounds
961e1996e0a8 drm/i915/gt: Move ivb GT workarounds from init_clock_gating to workarounds
a9a19ef20e69 drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds (rev2)
2020-06-11 8:01 [Intel-gfx] [PATCH 1/6] drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds Chris Wilson
` (12 preceding siblings ...)
2020-06-11 10:21 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-06-11 13:43 ` Patchwork
13 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2020-06-11 13:43 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds (rev2)
URL : https://patchwork.freedesktop.org/series/78214/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8614_full -> Patchwork_17926_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_17926_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_17926_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_17926_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_mmap_gtt@fault-concurrent:
- shard-iclb: [PASS][1] -> [CRASH][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-iclb1/igt@gem_mmap_gtt@fault-concurrent.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-iclb8/igt@gem_mmap_gtt@fault-concurrent.html
### Piglit changes ###
#### Possible regressions ####
* spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-bitand-neg-uint-uint (NEW):
- {pig-icl-1065g7}: NOTRUN -> [INCOMPLETE][3] +5 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/pig-icl-1065g7/spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-bitand-neg-uint-uint.html
* spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-div-float-vec4 (NEW):
- {pig-icl-1065g7}: NOTRUN -> [CRASH][4] +1 similar issue
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/pig-icl-1065g7/spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-div-float-vec4.html
New tests
---------
New tests have been introduced between CI_DRM_8614_full and Patchwork_17926_full:
### New Piglit tests (8) ###
* spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-assign-bitand-ivec3-ivec3:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-assign-bitor-int-int:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-bitand-neg-uint-uint:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-bitxor-neg-ivec3-ivec3:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-bitxor-not-int-ivec2:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-div-float-vec4:
- Statuses : 1 crash(s)
- Exec time: [0.28] s
* spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-mult-mat3-mat4x3:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_tessellation_shader@execution@built-in-functions@tcs-step-float-vec2:
- Statuses : 1 crash(s)
- Exec time: [0.26] s
Known issues
------------
Here are the changes found in Patchwork_17926_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@engines-mixed-process@vcs1:
- shard-tglb: [PASS][5] -> [FAIL][6] ([i915#1528])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-tglb5/igt@gem_ctx_persistence@engines-mixed-process@vcs1.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-tglb2/igt@gem_ctx_persistence@engines-mixed-process@vcs1.html
* igt@gem_exec_reloc@basic-concurrent0:
- shard-glk: [PASS][7] -> [FAIL][8] ([i915#1930])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-glk6/igt@gem_exec_reloc@basic-concurrent0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-glk2/igt@gem_exec_reloc@basic-concurrent0.html
* igt@gem_fence_thrash@bo-write-verify-y:
- shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#93] / [i915#95]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-kbl3/igt@gem_fence_thrash@bo-write-verify-y.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-kbl6/igt@gem_fence_thrash@bo-write-verify-y.html
* igt@kms_addfb_basic@bad-pitch-32:
- shard-snb: [PASS][11] -> [TIMEOUT][12] ([i915#1958]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-snb2/igt@kms_addfb_basic@bad-pitch-32.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-snb4/igt@kms_addfb_basic@bad-pitch-32.html
* igt@kms_atomic@atomic-invalid-params:
- shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#95]) +15 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-apl3/igt@kms_atomic@atomic-invalid-params.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-apl6/igt@kms_atomic@atomic-invalid-params.html
* igt@kms_big_fb@linear-8bpp-rotate-180:
- shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#1982])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-apl4/igt@kms_big_fb@linear-8bpp-rotate-180.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-apl2/igt@kms_big_fb@linear-8bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-0:
- shard-iclb: [PASS][17] -> [DMESG-WARN][18] ([i915#1982])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-iclb3/igt@kms_big_fb@y-tiled-64bpp-rotate-0.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-iclb3/igt@kms_big_fb@y-tiled-64bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-180:
- shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#1982])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-kbl3/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-kbl6/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html
* igt@kms_color@pipe-b-ctm-negative:
- shard-skl: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) +10 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-skl2/igt@kms_color@pipe-b-ctm-negative.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-skl9/igt@kms_color@pipe-b-ctm-negative.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([i915#180]) +4 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk: [PASS][25] -> [FAIL][26] ([i915#72])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-glk6/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-glk2/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic:
- shard-skl: [PASS][27] -> [FAIL][28] ([IGT#5])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][29] -> [FAIL][30] ([i915#79])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-suspend@a-dp1:
- shard-apl: [PASS][31] -> [DMESG-WARN][32] ([i915#180]) +3 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-apl2/igt@kms_flip@flip-vs-suspend@a-dp1.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-apl6/igt@kms_flip@flip-vs-suspend@a-dp1.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [PASS][33] -> [SKIP][34] ([fdo#109441]) +2 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-iclb6/igt@kms_psr@psr2_no_drrs.html
* igt@kms_setmode@basic:
- shard-skl: [PASS][35] -> [FAIL][36] ([i915#31])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-skl10/igt@kms_setmode@basic.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-skl8/igt@kms_setmode@basic.html
* igt@perf@blocking-parameterized:
- shard-iclb: [PASS][37] -> [FAIL][38] ([i915#1542])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-iclb2/igt@perf@blocking-parameterized.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-iclb4/igt@perf@blocking-parameterized.html
* igt@perf@polling-parameterized:
- shard-tglb: [PASS][39] -> [FAIL][40] ([i915#1542])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-tglb8/igt@perf@polling-parameterized.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-tglb5/igt@perf@polling-parameterized.html
#### Possible fixes ####
* igt@gem_exec_fence@parallel@rcs0:
- shard-tglb: [FAIL][41] ([i915#1893]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-tglb8/igt@gem_exec_fence@parallel@rcs0.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-tglb5/igt@gem_exec_fence@parallel@rcs0.html
* igt@gem_exec_suspend@basic-s3:
- shard-kbl: [DMESG-WARN][43] ([i915#180]) -> [PASS][44] +2 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-kbl7/igt@gem_exec_suspend@basic-s3.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-kbl2/igt@gem_exec_suspend@basic-s3.html
* igt@gem_exec_whisper@basic-contexts-forked-all:
- shard-glk: [DMESG-WARN][45] ([i915#118] / [i915#95]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-glk2/igt@gem_exec_whisper@basic-contexts-forked-all.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-glk9/igt@gem_exec_whisper@basic-contexts-forked-all.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-180:
- shard-glk: [DMESG-FAIL][47] ([i915#118] / [i915#95]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-glk8/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-glk7/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html
* igt@kms_cursor_legacy@cursor-vs-flip-varying-size:
- shard-skl: [DMESG-WARN][49] ([i915#1982]) -> [PASS][50] +9 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-skl2/igt@kms_cursor_legacy@cursor-vs-flip-varying-size.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-skl9/igt@kms_cursor_legacy@cursor-vs-flip-varying-size.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-pwrite:
- shard-tglb: [DMESG-WARN][51] ([i915#1982]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-pwrite.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-pwrite.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [FAIL][53] ([i915#1188]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-skl10/igt@kms_hdr@bpc-switch-dpms.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-skl7/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-kbl: [INCOMPLETE][55] ([i915#155]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-kbl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-kbl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [FAIL][57] ([fdo#108145] / [i915#265]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [SKIP][59] ([fdo#109441]) -> [PASS][60] +2 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-iclb1/igt@kms_psr@psr2_sprite_plane_move.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [DMESG-WARN][61] ([i915#180]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-apl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-apl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@perf_pmu@other-init-3:
- shard-tglb: [DMESG-WARN][63] ([i915#402]) -> [PASS][64] +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-tglb7/igt@perf_pmu@other-init-3.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-tglb8/igt@perf_pmu@other-init-3.html
* igt@syncobj_wait@wait-all-for-submit-complex:
- shard-apl: [DMESG-WARN][65] ([i915#95]) -> [PASS][66] +13 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-apl7/igt@syncobj_wait@wait-all-for-submit-complex.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-apl8/igt@syncobj_wait@wait-all-for-submit-complex.html
#### Warnings ####
* igt@gem_eio@in-flight-suspend:
- shard-kbl: [DMESG-WARN][67] ([i915#180] / [i915#93] / [i915#95]) -> [DMESG-WARN][68] ([i915#93] / [i915#95])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-kbl4/igt@gem_eio@in-flight-suspend.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-kbl4/igt@gem_eio@in-flight-suspend.html
* igt@gem_exec_reloc@basic-concurrent16:
- shard-snb: [FAIL][69] ([i915#1930]) -> [TIMEOUT][70] ([i915#1958])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-snb2/igt@gem_exec_reloc@basic-concurrent16.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-snb4/igt@gem_exec_reloc@basic-concurrent16.html
- shard-apl: [TIMEOUT][71] ([i915#1635]) -> [INCOMPLETE][72] ([i915#1635] / [i915#1958])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-apl4/igt@gem_exec_reloc@basic-concurrent16.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-apl2/igt@gem_exec_reloc@basic-concurrent16.html
* igt@i915_pm_dc@dc6-psr:
- shard-tglb: [SKIP][73] ([i915#468]) -> [FAIL][74] ([i915#1899])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-tglb2/igt@i915_pm_dc@dc6-psr.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-tglb3/igt@i915_pm_dc@dc6-psr.html
* igt@i915_suspend@forcewake:
- shard-kbl: [DMESG-WARN][75] ([i915#93] / [i915#95]) -> [DMESG-WARN][76] ([i915#180] / [i915#93] / [i915#95])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-kbl1/igt@i915_suspend@forcewake.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-kbl1/igt@i915_suspend@forcewake.html
* igt@kms_content_protection@lic:
- shard-apl: [TIMEOUT][77] ([i915#1319] / [i915#1635]) -> [TIMEOUT][78] ([i915#1319]) +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-apl3/igt@kms_content_protection@lic.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-apl2/igt@kms_content_protection@lic.html
* igt@kms_plane_alpha_blend@pipe-d-alpha-transparent-fb:
- shard-snb: [SKIP][79] ([fdo#109271]) -> [TIMEOUT][80] ([i915#1958]) +3 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-snb2/igt@kms_plane_alpha_blend@pipe-d-alpha-transparent-fb.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-snb4/igt@kms_plane_alpha_blend@pipe-d-alpha-transparent-fb.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1893]: https://gitlab.freedesktop.org/drm/intel/issues/1893
[i915#1899]: https://gitlab.freedesktop.org/drm/intel/issues/1899
[i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930
[i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
[i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_8614 -> Patchwork_17926
CI-20190529: 20190529
CI_DRM_8614: 207862f18909166ffcf9e288ff796b756ae82d1c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5702: d16ad07e7f2a028e14d61f570931c87fa5ce404c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17926: 66c89c81b8144175aa4d9682e650323658fddcce @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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