From: Thomas Gleixner <tglx@linutronix.de>
To: "Singh\, Balbir" <sblbir@amazon.com>,
"linux-kernel\@vger.kernel.org" <linux-kernel@vger.kernel.org>
Cc: "keescook\@chromium.org" <keescook@chromium.org>,
"tony.luck\@intel.com" <tony.luck@intel.com>,
"benh\@kernel.crashing.org" <benh@kernel.crashing.org>,
"jpoimboe\@redhat.com" <jpoimboe@redhat.com>,
"x86\@kernel.org" <x86@kernel.org>,
"dave.hansen\@intel.com" <dave.hansen@intel.com>
Subject: Re: [PATCH v3 3/5] arch/x86/mm: Refactor cond_ibpb() to support other use cases
Date: Sat, 18 Apr 2020 11:59:48 +0200 [thread overview]
Message-ID: <87pnc5xgff.fsf@nanos.tec.linutronix.de> (raw)
In-Reply-To: <12023cc73a6344ed7499e09492a6934c1dfaf044.camel@amazon.com>
"Singh, Balbir" <sblbir@amazon.com> writes:
> On Fri, 2020-04-17 at 15:07 +0200, Thomas Gleixner wrote:
>>
>> Balbir Singh <sblbir@amazon.com> writes:
>> >
>> > /*
>> > - * Use bit 0 to mangle the TIF_SPEC_IB state into the mm pointer which is
>> > - * stored in cpu_tlb_state.last_user_mm_ibpb.
>> > + * Bits to mangle the TIF_SPEC_IB state into the mm pointer which is
>> > + * stored in cpu_tlb_state.last_user_mm_spec.
>> > */
>> > #define LAST_USER_MM_IBPB 0x1UL
>> > +#define LAST_USER_MM_SPEC_MASK (LAST_USER_MM_IBPB)
>> >
>> > /* Reinitialize tlbstate. */
>> > - this_cpu_write(cpu_tlbstate.last_user_mm_ibpb, LAST_USER_MM_IBPB);
>> > + this_cpu_write(cpu_tlbstate.last_user_mm_spec, LAST_USER_MM_IBPB);
>>
>> Shouldn't that be LAST_USER_MM_MASK?
>>
> No, that crashes the system for SW flushes, because it tries to flush the L1D
> via the software loop and early enough we don't have the l1d_flush_pages
> allocated. LAST_USER_MM_MASK has LAST_USER_MM_FLUSH_L1D bit set.
You can trivially prevent this by checking l1d_flush_pages != NULL.
Thanks,
tglx
next prev parent reply other threads:[~2020-04-18 10:00 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-08 9:02 [PATCH v3 0/5] Optionally flush L1D on context switch Balbir Singh
2020-04-08 9:02 ` [PATCH v3 1/5] arch/x86/kvm: Refactor l1d flush lifecycle management Balbir Singh
2020-04-17 12:57 ` Thomas Gleixner
2020-04-17 22:34 ` Singh, Balbir
2020-04-08 9:02 ` [PATCH v3 2/5] arch/x86: Refactor tlbflush and l1d flush Balbir Singh
2020-04-17 13:03 ` Thomas Gleixner
2020-04-17 22:58 ` Singh, Balbir
2020-04-08 9:02 ` [PATCH v3 3/5] arch/x86/mm: Refactor cond_ibpb() to support other use cases Balbir Singh
2020-04-17 13:07 ` Thomas Gleixner
2020-04-17 23:02 ` Singh, Balbir
2020-04-18 9:59 ` Thomas Gleixner [this message]
2020-04-21 3:46 ` Singh, Balbir
2020-04-21 9:02 ` Thomas Gleixner
2020-04-08 9:02 ` [PATCH v3 4/5] arch/x86: Optionally flush L1D on context switch Balbir Singh
2020-04-17 14:41 ` Thomas Gleixner
2020-04-18 1:30 ` Singh, Balbir
2020-04-18 10:17 ` Thomas Gleixner
2020-04-20 0:24 ` Singh, Balbir
2020-04-08 9:02 ` [PATCH v3 5/5] arch/x86: Add L1D flushing Documentation Balbir Singh
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