From: "Singh, Balbir" <sblbir@amazon.com>
To: "tglx@linutronix.de" <tglx@linutronix.de>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Cc: "keescook@chromium.org" <keescook@chromium.org>,
"tony.luck@intel.com" <tony.luck@intel.com>,
"benh@kernel.crashing.org" <benh@kernel.crashing.org>,
"jpoimboe@redhat.com" <jpoimboe@redhat.com>,
"x86@kernel.org" <x86@kernel.org>,
"dave.hansen@intel.com" <dave.hansen@intel.com>
Subject: Re: [PATCH v3 4/5] arch/x86: Optionally flush L1D on context switch
Date: Mon, 20 Apr 2020 00:24:57 +0000 [thread overview]
Message-ID: <eb69188fead8b96a4a7cfbfe4c586c19ca233819.camel@amazon.com> (raw)
In-Reply-To: <87mu79xflj.fsf@nanos.tec.linutronix.de>
On Sat, 2020-04-18 at 12:17 +0200, Thomas Gleixner wrote:
>
>
> "Singh, Balbir" <sblbir@amazon.com> writes:
> > On Fri, 2020-04-17 at 16:41 +0200, Thomas Gleixner wrote:
> > > Balbir Singh <sblbir@amazon.com> writes:
> > > static void *l1d_flush_pages;
> > > static DEFINE_MUTEX(l1d_flush_mutex);
> > >
> > > int l1d_flush_init(void)
> > > {
> > > int ret;
> > >
> > > if (static_cpu_has(X86_FEATURE_FLUSH_L1D) || l1d_flush_pages)
> > > return 0;
> > >
> > > mutex_lock(&l1d_flush_mutex);
> > > if (!l1d_flush_pages)
> > > l1d_flush_pages = l1d_flush_alloc_pages();
> > > ret = l1d_flush_pages ? 0 : -ENOMEM;
> > > mutex_unlock(&l1d_flush_mutex);
> > > return ret;
> > > }
> > > EXPORT_SYMBOL_GPL(l1d_flush_init);
> > >
> > > which removes the export of l1d_flush_alloc_pages() and gets rid of the
> > > cleanup counterpart. In a real world deployment unloading of VMX if used
> > > once is unlikely and with the task based one you end up with these pages
> > > 'leaked' anyway if used once.
> > >
> >
> > I don't want the patches to be enforce that one cannot unload the kvm
> > module,
> > but I can refactor those bits a bit more
>
> Not freeing the l1d flush pages does not prevent unloading the kvm
> module. It just keeps the around. It's the same problem with your L1D
> flush for tasks. If one tasks uses it then the pages stay around until
> the system reboots.
Yes, Fair enough, you also seem to suggest that the same set of pages can be
shared across VMX and L1D flushes (which is fine by me), I suspect at some
point we'd need to to per NUMA node allocations, but lets not prematurely
optimize.
>
> > > If any other architecture enables this, then it will have _ALL_ of this
> > > code duplicated. So we should rather have:
> >
> > But that is being a bit prescriptive to arch's to implement their L1D
> > flushing
> > using TIF flags, arch's should be free to use bits in struct_mm for their
> > arch
> > if they feel so.
> > > - All architectures have to use TIF_SPEC_FLUSH_L1D if they want to
> > > support the prctl.
> > >
> >
> > That is a concern (see above), should we enforce this?
>
> Fair enough, but it's trivial enough to have:
>
> static inline void arch_task_l1d_flush_update(bool enable)
> static inline bool arch_task_l1d_flush_state(void)
>
> and the rest of the logic is just identical.
>
OK, so you'd still like to see the logic move to lib/l1d_flush.c? Let me get
working on that and see what the changes look like
Thanks for the review,
Balbir Singh
next prev parent reply other threads:[~2020-04-20 0:25 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-08 9:02 [PATCH v3 0/5] Optionally flush L1D on context switch Balbir Singh
2020-04-08 9:02 ` [PATCH v3 1/5] arch/x86/kvm: Refactor l1d flush lifecycle management Balbir Singh
2020-04-17 12:57 ` Thomas Gleixner
2020-04-17 22:34 ` Singh, Balbir
2020-04-08 9:02 ` [PATCH v3 2/5] arch/x86: Refactor tlbflush and l1d flush Balbir Singh
2020-04-17 13:03 ` Thomas Gleixner
2020-04-17 22:58 ` Singh, Balbir
2020-04-08 9:02 ` [PATCH v3 3/5] arch/x86/mm: Refactor cond_ibpb() to support other use cases Balbir Singh
2020-04-17 13:07 ` Thomas Gleixner
2020-04-17 23:02 ` Singh, Balbir
2020-04-18 9:59 ` Thomas Gleixner
2020-04-21 3:46 ` Singh, Balbir
2020-04-21 9:02 ` Thomas Gleixner
2020-04-08 9:02 ` [PATCH v3 4/5] arch/x86: Optionally flush L1D on context switch Balbir Singh
2020-04-17 14:41 ` Thomas Gleixner
2020-04-18 1:30 ` Singh, Balbir
2020-04-18 10:17 ` Thomas Gleixner
2020-04-20 0:24 ` Singh, Balbir [this message]
2020-04-08 9:02 ` [PATCH v3 5/5] arch/x86: Add L1D flushing Documentation Balbir Singh
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