[PATCH 0/1] ARM:OMAP3: Misc off mode fixes

[PATCH 0/1] ARM:OMAP3: Misc off mode fixes

[Kalle Jokiniemi]

Here's a set of patches to fix some off mode problems in ES3.0 and
ES3.1 devices. Should apply on top of pm branch.

Kalle Jokiniemi (3):
      ARM:OMAP3: Enable SDRC workaround for ES3.1
      ARM: OMAP3: Fix secure sram saving
      ARM: OMAP3: Enable IO-CHAIN wakeup

[PATCH 1/3] ARM:OMAP3: Enable SDRC workaround for ES3.1

[Kalle Jokiniemi]

Enable a workaround to manually restart the SDRC
auto-refresh after wake-up from off mode also on
ES3.1 silicon revision chips.

Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi@digia.com>
---
 arch/arm/mach-omap2/control.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 31284c6..a0429fe 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -209,7 +209,8 @@ void omap3_save_scratchpad_contents(void)
 
 	/* Populate the Scratchpad contents */
 	scratchpad_contents.boot_config_ptr = 0x0;
-	if (omap_rev() != OMAP3430_REV_ES3_0)
+	if (omap_rev() != OMAP3430_REV_ES3_0 &&
+					omap_rev() != OMAP3430_REV_ES3_1)
 		scratchpad_contents.public_restore_ptr =
 			virt_to_phys(get_restore_pointer());
 	else
-- 
1.5.4.3

[PATCH 2/3] ARM: OMAP3: Fix secure sram saving

[Kalle Jokiniemi]

The secure sram context save uses dma channels 0 and 1.
In order to avoid collision between kernel DMA transfers and
ROM code dma transfers, we need to reserve DMA channels 0
1 on high security devices.

A bug in ROM code leaves dma irq status bits uncleared.
Hence those irq status bits need to be cleared when restoring
DMA context after off mode.

There was also a faulty parameter given to PPA in the secure
ram context save assembly code, which caused interrupts to
be enabled during secure ram context save. This caused the
save to fail sometimes, which resulted the saved context
to be corrupted, but also left DMA channels in secure mode.
The secure mode DMA channels caused "DMA secure error with
device 0" errors to be displayed.

Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi@digia.com>
Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
---
 arch/arm/mach-omap2/pm34xx.c    |    3 ---
 arch/arm/mach-omap2/sleep34xx.S |    2 +-
 arch/arm/plat-omap/dma.c        |   22 ++++++++++++++++++----
 3 files changed, 19 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index c21d4e9..7bbbcce 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -144,9 +144,6 @@ static void omap3_save_secure_ram_context(u32 target_mpu_state)
 	u32 ret;
 
 	if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
-		/* Disable dma irq before calling secure rom code API */
-		omap_dma_disable_irq(0);
-		omap_dma_disable_irq(1);
 		/*
 		 * MPU next state must be set to POWER_ON temporarily,
 		 * otherwise the WFI executed inside the ROM code
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 33ee85b..0a58c30 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -138,7 +138,7 @@ save_secure_ram_debug:
 	mov	r0, #25			@ set service ID for PPA
 	mov	r12, r0			@ copy secure service ID in r12
 	mov	r1, #0			@ set task id for ROM code in r1
-	mov	r2, #7			@ set some flags in r2, r6
+	mov	r2, #4			@ set some flags in r2, r6
 	mov	r6, #0xff
 	mcr	p15, 0, r0, c7, c10, 4	@ data write barrier
 	mcr	p15, 0, r0, c7, c10, 5	@ data memory barrier
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 94b3e4d..a040dbc 100755
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -2322,14 +2322,21 @@ EXPORT_SYMBOL(omap_dma_global_context_save);
 
 void omap_dma_global_context_restore(void)
 {
-	dma_write(0x2, OCP_SYSCONFIG);
-	while (!__raw_readl(omap_dma_base + OMAP_DMA4_SYSSTATUS))
-		;
 	dma_write(omap_dma_global_context.dma_gcr, GCR);
 	dma_write(omap_dma_global_context.dma_ocp_sysconfig,
 		OCP_SYSCONFIG);
 	dma_write(omap_dma_global_context.dma_irqenable_l0,
 		IRQENABLE_L0);
+
+	/*
+	 * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
+	 * after secure sram context save and restore. Hence we need to
+	 * manually clear those IRQs to avoid spurious interrupts. This
+	 * affects only secure devices.
+	 */
+	if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
+		dma_write(0x3 , IRQSTATUS_L0);
+	}
 }
 EXPORT_SYMBOL(omap_dma_global_context_restore);
 
@@ -2465,8 +2472,8 @@ static int __init omap_init_dma(void)
 	if (cpu_class_is_omap2())
 		setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq);
 
-	/* Enable smartidle idlemodes and autoidle */
 	if (cpu_is_omap34xx()) {
+		/* Enable smartidle idlemodes and autoidle */
 		u32 v = dma_read(OCP_SYSCONFIG);
 		v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK |
 				DMA_SYSCONFIG_SIDLEMODE_MASK |
@@ -2475,6 +2482,13 @@ static int __init omap_init_dma(void)
 			DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
 			DMA_SYSCONFIG_AUTOIDLE);
 		dma_write(v , OCP_SYSCONFIG);
+		/* reserve dma channels 0 and 1 in high security devices */
+		if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
+			printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
+					"HS ROM code\n");
+			dma_chan[0].dev_id = 0;
+			dma_chan[1].dev_id = 1;
+		}
 	}
 
 
-- 
1.5.4.3

[PATCH 3/3] ARM: OMAP3: Enable IO-CHAIN wakeup

[Kalle Jokiniemi]

OMAP 3430 ES3.1 chips have a separate bit for IO daisy-chain
wake up enabling. It needs to be enabled when entering
retention or off state, otherwise waking up might not work
in all situations.

Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi@digia.com>
---
 arch/arm/mach-omap2/pm34xx.c           |   37 +++++++++++++++++++++++++++++--
 arch/arm/mach-omap2/prm-regbits-34xx.h |    2 +
 2 files changed, 36 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 7bbbcce..4345df1 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -101,6 +101,34 @@ static inline void omap3_per_restore_context(void)
 	omap3_gpio_restore_context();
 }
 
+static void omap3_enable_io_chain(void)
+{
+	int timeout = 0;
+
+	if (omap_rev() >= OMAP3430_REV_ES3_1) {
+		prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN);
+		/* Do a readback to assure write has been done */
+		prm_read_mod_reg(WKUP_MOD, PM_WKEN);
+
+		while (!(prm_read_mod_reg(WKUP_MOD, PM_WKST) &
+						OMAP3430_ST_IO_CHAIN)) {
+			timeout++;
+			if (timeout > 1000) {
+				printk(KERN_ERR "Wake up daisy chain "
+						"activation failed.\n");
+				return;
+			}
+		prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN, WKUP_MOD, PM_WKST);
+		}
+	}
+}
+
+static void omap3_disable_io_chain(void)
+{
+	if (omap_rev() >= OMAP3430_REV_ES3_1)
+		prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN);
+}
+
 static void omap3_core_save_context(void)
 {
 	u32 control_padconf_off;
@@ -358,8 +386,9 @@ void omap_sram_idle(void)
 			omap3_core_save_context();
 			omap3_prcm_save_context();
 		}
-		/* Enable IO-PAD wakeup */
+		/* Enable IO-PAD and IO-CHAIN wakeups */
 		prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
+		omap3_enable_io_chain();
 	}
 
 	/*
@@ -425,9 +454,11 @@ void omap_sram_idle(void)
 			pwrdm_set_next_pwrst(per_pwrdm, PWRDM_POWER_OFF);
 	}
 
-	/* Disable IO-PAD wakeup */
-	if (core_next_state < PWRDM_POWER_ON)
+	/* Disable IO-PAD and IO-CHAIN wakeup */
+	if (core_next_state < PWRDM_POWER_ON) {
 		prm_clear_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
+		omap3_disable_io_chain();
+	}
 
 	/* Enable smartreflex after WFI */
 	enable_smartreflex(SR1);
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
index cb648f9..06fee29 100644
--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -365,6 +365,7 @@
 /* PM_PREPWSTST_GFX specific bits */
 
 /* PM_WKEN_WKUP specific bits */
+#define OMAP3430_EN_IO_CHAIN				(1 << 16)
 #define OMAP3430_EN_IO					(1 << 8)
 #define OMAP3430_EN_GPIO1				(1 << 3)
 
@@ -373,6 +374,7 @@
 /* PM_IVA2GRPSEL_WKUP specific bits */
 
 /* PM_WKST_WKUP specific bits */
+#define OMAP3430_ST_IO_CHAIN				(1 << 16)
 #define OMAP3430_ST_IO					(1 << 8)
 
 /* PRM_CLKSEL */
-- 
1.5.4.3

Re: [PATCH 3/3] ARM: OMAP3: Enable IO-CHAIN wakeup

[Kevin Hilman]

Kalle Jokiniemi <kalle.jokiniemi@digia.com> writes:

> OMAP 3430 ES3.1 chips have a separate bit for IO daisy-chain
> wake up enabling. It needs to be enabled when entering
> retention or off state, otherwise waking up might not work
> in all situations.
>
> Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi@digia.com>

Thanks, pushed after...

> ---
>  arch/arm/mach-omap2/pm34xx.c           |   37 +++++++++++++++++++++++++++++--
>  arch/arm/mach-omap2/prm-regbits-34xx.h |    2 +
>  2 files changed, 36 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index 7bbbcce..4345df1 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -101,6 +101,34 @@ static inline void omap3_per_restore_context(void)
>  	omap3_gpio_restore_context();
>  }
>  
> +static void omap3_enable_io_chain(void)
> +{
> +	int timeout = 0;
> +
> +	if (omap_rev() >= OMAP3430_REV_ES3_1) {
> +		prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN);
> +		/* Do a readback to assure write has been done */
> +		prm_read_mod_reg(WKUP_MOD, PM_WKEN);
> +
> +		while (!(prm_read_mod_reg(WKUP_MOD, PM_WKST) &
> +						OMAP3430_ST_IO_CHAIN)) {
> +			timeout++;
> +			if (timeout > 1000) {
> +				printk(KERN_ERR "Wake up daisy chain "
> +						"activation failed.\n");
> +				return;
> +			}
> +		prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN, WKUP_MOD, PM_WKST);

fixing this screwy indent.

Kevin

Re: [PATCH 2/3] ARM: OMAP3: Fix secure sram saving

[Kevin Hilman]

Kalle Jokiniemi <kalle.jokiniemi@digia.com> writes:

> The secure sram context save uses dma channels 0 and 1.
> In order to avoid collision between kernel DMA transfers and
> ROM code dma transfers, we need to reserve DMA channels 0
> 1 on high security devices.
>
> A bug in ROM code leaves dma irq status bits uncleared.
> Hence those irq status bits need to be cleared when restoring
> DMA context after off mode.
>
> There was also a faulty parameter given to PPA in the secure
> ram context save assembly code, which caused interrupts to
> be enabled during secure ram context save. This caused the
> save to fail sometimes, which resulted the saved context
> to be corrupted, but also left DMA channels in secure mode.
> The secure mode DMA channels caused "DMA secure error with
> device 0" errors to be displayed.
>
> Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi@digia.com>
> Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>

Thanks, pushing after fixing this minor checkpatch warning:

WARNING: braces {} are not necessary for single statement blocks
#82: FILE: arch/arm/plat-omap/dma.c:2337:
+	if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
+		dma_write(0x3 , IRQSTATUS_L0);
+	}

Kevin

Re: [PATCH 1/3] ARM:OMAP3: Enable SDRC workaround for ES3.1

[Kevin Hilman]

Kalle Jokiniemi <kalle.jokiniemi@digia.com> writes:

> Enable a workaround to manually restart the SDRC
> auto-refresh after wake-up from off mode also on
> ES3.1 silicon revision chips.
>
> Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi@digia.com>

Thanks, pushing to PM branch.

Kevin