From: Cornelia Huck <cohuck@redhat.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org,
Eric Auger <eric.auger@redhat.com>,
Sebastian Ott <sebott@redhat.com>,
Jonathan Cameron <jonathan.cameron@huawei.com>,
Alireza Sanaee <alireza.sanaee@huawei.com>
Subject: Re: [PATCH v2 0/3] arm: demuxed ID registers (CCSIDR_EL1)
Date: Thu, 05 Feb 2026 17:50:46 +0100 [thread overview]
Message-ID: <87qzqzrv6h.fsf@redhat.com> (raw)
In-Reply-To: <CAFEAcA9SvgjUvwLb8VjOzyDNy_g0E30wpUKSN=ENfm3HXx_-SA@mail.gmail.com>
On Thu, Feb 05 2026, Peter Maydell <peter.maydell@linaro.org> wrote:
> On Wed, 4 Feb 2026 at 13:32, Cornelia Huck <cohuck@redhat.com> wrote:
>> RFC because there are still some open questions:
>
>> - There's a slight disagreement between the current code (providing 16
>> entries for CCSIDR_EL1) and the KVM code (providing (7 cache levels) *
>> (data/unified, instruction) = 14 entries.) With FEAT_MTE2, we might be
>> needing 7 more entries.
>
> This is because architecturally the CCSELR_EL1 register is:
> bit 4 : TnD (tag-not-data)
> bits [3:1] : level
> bit 0 : InD (instruction-not-data)
>
> but the 'level' field has 0b111 as Reserved, and KVM doesn't
> (currently) handle the FEAT_MTE2 TnD bit, so from KVM's point
> of view only 0..13 are valid values here.
>
> The architecture says that if you set CSSELR_EL1 to an invalid
> setting then reading CCSIDR_EL1 can be:
> * a NOP
> * UNDEF
> * return an UNKNOWN value
>
> For TCG we opted to permit any indexes 0..15, so that we treat
> the architecturally invalid 0b1110 and 0b1111 the same way as
> we treat "you picked a level this particular CPU doesn't implement"
> (and return a 0 from our cpu->cssidr[] array). Otherwise we would
> have had to add an extra check for "and level isn't invalid".
That makes sense.
>
> TCG also doesn't do anything with the FEAT_MTE2 TnD bit: looks
> like we missed that functionality when we added MTE2 emulation.
> Setting TnD and InD at once isn't a valid combination, so we
> could either extend our cpu->ccsidr[] array to 32 words (and
> live with 8 of the extras being unused), or else add a new
> 8-word array for the MTE tag-cache ID values.
Whatever we do, it would be easiest if KVM and TCG followed a similar
approach, so we don't end up having to special case the code.
As KVM also supports setting (virtual) CCSIDR_EL1 values, I think just
extending the array would be easiest, so that QEMU can just keep
everything in one place.
prev parent reply other threads:[~2026-02-05 16:51 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-04 13:32 [PATCH v2 0/3] arm: demuxed ID registers (CCSIDR_EL1) Cornelia Huck
2026-02-04 13:32 ` [PATCH v2 1/3] arm: handle demuxed ID registers Cornelia Huck
2026-02-05 3:24 ` Richard Henderson
2026-04-01 8:17 ` Cornelia Huck
2026-04-01 16:26 ` Eric Auger
2026-04-02 14:55 ` Cornelia Huck
2026-02-04 13:32 ` [PATCH v2 2/3] arm: handle CCSIDR_EL1 as a demuxed register Cornelia Huck
2026-04-01 16:46 ` Eric Auger
2026-04-02 15:04 ` Cornelia Huck
2026-02-04 13:32 ` [PATCH v2 3/3] arm/kvm: get demuxed ID registers from kvm Cornelia Huck
2026-04-01 17:00 ` Eric Auger
2026-04-02 15:19 ` Cornelia Huck
2026-02-05 11:52 ` [PATCH v2 0/3] arm: demuxed ID registers (CCSIDR_EL1) Peter Maydell
2026-02-05 16:50 ` Cornelia Huck [this message]
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