[Intel-gfx] [PATCH v7 0/8] Add DSC PPS readout

[Intel-gfx] [PATCH v7 0/8] Add DSC PPS readout

[Suraj Kandpal]

Up until now we only verified one or two of the dsc pps
params like bits_per_component and bits_per_pixel this
patch series aim to readout almost all PPS param and get
them compared.
Along with that some work on making a common function to
read and write PPS param regiters is also done.

--v2
-Remove duplicated code and create function that fetches register
and reuse that. [Jani]
-move WARN_ON one abstraction layer up. [Jani]
-Split patch so that refactor and a new functionality is not added
in the same patch. [Jani]
-Add a new refactor patch so that bit shifting can be done in a
clean way. [Jani]

--v3
-Fix the typo in patch 2 [Jani]
-Get both dsc_reg regardless of dsc_eng_no. [Jani]
-Remove usage of num_vdsc_instances. [Ankit]
-Add macro to further optimize intel_dsc_get_pps_reg

--v4
-Manipulate register addresses rather than creating a macro to
manipulate variable name based on pps [Ankit]

--v5
-Use an array to fill the dsc registers instead of individual register
[Ankit]
-Get only dsc register that are required.

--v6
-make intel_get_no_vdsc_inst_per_pipe func static

--v7
-shorten func name for getting vdsc instances per pipe [Ankit]
-send no vdsc instances to dsc read and write reg funcs [Ankit]

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>

Suraj Kandpal (8):
  drm/i915/vdsc: Refactor dsc register field macro
  drm/i915/vdsc: Add a check for dsc split cases
  drm/i915/vdsc: Add func to get no. of vdsc instances per pipe
  drm/i915/vdsc: Add function to read any PPS register
  drm/i915/vdsc: Add function to write in PPS register
  drm/i915/vdsc: Remove unused dsc registers
  drm/i915/vdsc: Fill the intel_dsc_get_pps_config function
  drm/i915/display: Compare the readout dsc pps params

 drivers/gpu/drm/i915/display/intel_display.c  |  31 ++
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 524 +++++++++---------
 .../gpu/drm/i915/display/intel_vdsc_regs.h    | 366 ++++--------
 3 files changed, 392 insertions(+), 529 deletions(-)

-- 
2.25.1

[Intel-gfx] [PATCH v7 1/8] drm/i915/vdsc: Refactor dsc register field macro

[Suraj Kandpal]

This patch refactors dsc register related macros that prepares
the values to be written in the register. The current bit shifting
looks bad and going forward will not serve our purpose to readout
dsc register field values the change was suggested by Jani Nikula.

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 .../gpu/drm/i915/display/intel_vdsc_regs.h    | 98 +++++++++++++------
 1 file changed, 70 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
index b71f00b5c761..785ede31116e 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
@@ -57,7 +57,8 @@
 #define MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
 							   _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB, \
 							   _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC)
-#define DSC_SL_BPG_OFFSET(offset)		((offset) << 27)
+#define DSC_SL_BPG_OFFSET_MASK			REG_GENMASK(31, 27)
+#define DSC_SL_BPG_OFFSET(offset)		REG_FIELD_PREP(DSC_SL_BPG_OFFSET_MASK, offset)
 
 #define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB	0x782B8
 #define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB	0x783B8
@@ -69,8 +70,10 @@
 #define MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
 							   _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB, \
 							   _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC)
-#define DSC_NSL_BPG_OFFSET(offset)		((offset) << 16)
-#define DSC_SL_OFFSET_ADJ(offset)		((offset) << 0)
+#define DSC_NSL_BPG_OFFSET_MASK			REG_GENMASK(31, 16)
+#define DSC_SL_OFFSET_ADJ_MASK			REG_GENMASK(15, 0)
+#define DSC_NSL_BPG_OFFSET(offset)		REG_FIELD_PREP(DSC_NSL_BPG_OFFSET_MASK, offset)
+#define DSC_SL_OFFSET_ADJ(offset)		REG_FIELD_PREP(DSC_SL_OFFSET_ADJ_MASK, offset)
 
 /* Icelake Display Stream Compression Registers */
 #define DSCA_PICTURE_PARAMETER_SET_0		_MMIO(0x6B200)
@@ -123,8 +126,10 @@
 #define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
 					    _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \
 					    _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC)
-#define  DSC_PIC_WIDTH(pic_width)	((pic_width) << 16)
-#define  DSC_PIC_HEIGHT(pic_height)	((pic_height) << 0)
+#define  DSC_PIC_WIDTH_MASK		REG_GENMASK(31, 16)
+#define  DSC_PIC_HEIGHT_MASK		REG_GENMASK(15, 0)
+#define  DSC_PIC_WIDTH(pic_width)	REG_FIELD_PREP(DSC_PIC_WIDTH_MASK, pic_width)
+#define  DSC_PIC_HEIGHT(pic_height)	REG_FIELD_PREP(DSC_PIC_HEIGHT_MASK, pic_height)
 
 #define DSCA_PICTURE_PARAMETER_SET_3		_MMIO(0x6B20C)
 #define DSCC_PICTURE_PARAMETER_SET_3		_MMIO(0x6BA0C)
@@ -138,8 +143,10 @@
 #define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC)
-#define  DSC_SLICE_WIDTH(slice_width)   ((slice_width) << 16)
-#define  DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
+#define  DSC_SLICE_WIDTH_MASK			REG_GENMASK(31, 16)
+#define  DSC_SLICE_HEIGHT_MASK			REG_GENMASK(15, 0)
+#define  DSC_SLICE_WIDTH(slice_width)		REG_FIELD_PREP(DSC_SLICE_WIDTH_MASK, slice_width)
+#define  DSC_SLICE_HEIGHT(slice_height)		REG_FIELD_PREP(DSC_SLICE_HEIGHT_MASK, slice_height)
 
 #define DSCA_PICTURE_PARAMETER_SET_4		_MMIO(0x6B210)
 #define DSCC_PICTURE_PARAMETER_SET_4		_MMIO(0x6BA10)
@@ -153,8 +160,12 @@
 #define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)
-#define  DSC_INITIAL_DEC_DELAY(dec_delay)       ((dec_delay) << 16)
-#define  DSC_INITIAL_XMIT_DELAY(xmit_delay)     ((xmit_delay) << 0)
+#define  DSC_INITIAL_DEC_DELAY_MASK		REG_GENMASK(31, 16)
+#define  DSC_INITIAL_XMIT_DELAY_MASK		REG_GENMASK(9, 0)
+#define  DSC_INITIAL_DEC_DELAY(dec_delay)       REG_FIELD_PREP(DSC_INITIAL_DEC_DELAY_MASK, \
+							       dec_delay)
+#define  DSC_INITIAL_XMIT_DELAY(xmit_delay)     REG_FIELD_PREP(DSC_INITIAL_XMIT_DELAY_MASK, \
+							       xmit_delay)
 
 #define DSCA_PICTURE_PARAMETER_SET_5		_MMIO(0x6B214)
 #define DSCC_PICTURE_PARAMETER_SET_5		_MMIO(0x6BA14)
@@ -168,8 +179,10 @@
 #define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
-#define  DSC_SCALE_DEC_INT(scale_dec)	((scale_dec) << 16)
-#define  DSC_SCALE_INC_INT(scale_inc)		((scale_inc) << 0)
+#define  DSC_SCALE_DEC_INT_MASK			REG_GENMASK(27, 16)
+#define  DSC_SCALE_INC_INT_MASK			REG_GENMASK(15, 0)
+#define  DSC_SCALE_DEC_INT(scale_dec)		REG_FIELD_PREP(DSC_SCALE_DEC_INT_MASK, scale_dec)
+#define  DSC_SCALE_INC_INT(scale_inc)		REG_FIELD_PREP(DSC_SCALE_INC_INT_MASK, scale_inc)
 
 #define DSCA_PICTURE_PARAMETER_SET_6		_MMIO(0x6B218)
 #define DSCC_PICTURE_PARAMETER_SET_6		_MMIO(0x6BA18)
@@ -183,10 +196,16 @@
 #define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC)
-#define  DSC_FLATNESS_MAX_QP(max_qp)		((max_qp) << 24)
-#define  DSC_FLATNESS_MIN_QP(min_qp)		((min_qp) << 16)
-#define  DSC_FIRST_LINE_BPG_OFFSET(offset)	((offset) << 8)
-#define  DSC_INITIAL_SCALE_VALUE(value)		((value) << 0)
+#define  DSC_FLATNESS_MAX_QP_MASK		REG_GENMASK(28, 24)
+#define  DSC_FLATNESS_MIN_QP_MASK		REG_GENMASK(20, 16)
+#define  DSC_FIRST_LINE_BPG_OFFSET_MASK		REG_GENMASK(12, 8)
+#define  DSC_INITIAL_SCALE_VALUE_MASK		REG_GENMASK(5, 0)
+#define  DSC_FLATNESS_MAX_QP(max_qp)		REG_FIELD_PREP(DSC_FLATNESS_MAX_QP_MASK, max_qp)
+#define  DSC_FLATNESS_MIN_QP(min_qp)		REG_FIELD_PREP(DSC_FLATNESS_MIN_QP_MASK, min_qp)
+#define  DSC_FIRST_LINE_BPG_OFFSET(offset)	REG_FIELD_PREP(DSC_FIRST_LINE_BPG_OFFSET_MASK, \
+							       offset)
+#define  DSC_INITIAL_SCALE_VALUE(value)		REG_FIELD_PREP(DSC_INITIAL_SCALE_VALUE_MASK, \
+							       value)
 
 #define DSCA_PICTURE_PARAMETER_SET_7		_MMIO(0x6B21C)
 #define DSCC_PICTURE_PARAMETER_SET_7		_MMIO(0x6BA1C)
@@ -200,8 +219,11 @@
 #define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
 							    _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \
 							    _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC)
-#define  DSC_NFL_BPG_OFFSET(bpg_offset)		((bpg_offset) << 16)
-#define  DSC_SLICE_BPG_OFFSET(bpg_offset)	((bpg_offset) << 0)
+#define  DSC_NFL_BPG_OFFSET_MASK		REG_GENMASK(31, 16)
+#define  DSC_SLICE_BPG_OFFSET_MASK		REG_GENMASK(15, 0)
+#define  DSC_NFL_BPG_OFFSET(bpg_offset)		REG_FIELD_PREP(DSC_NFL_BPG_OFFSET_MASK, bpg_offset)
+#define  DSC_SLICE_BPG_OFFSET(bpg_offset)	REG_FIELD_PREP(DSC_SLICE_BPG_OFFSET_MASK, \
+							       bpg_offset)
 
 #define DSCA_PICTURE_PARAMETER_SET_8		_MMIO(0x6B220)
 #define DSCC_PICTURE_PARAMETER_SET_8		_MMIO(0x6BA20)
@@ -215,8 +237,12 @@
 #define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC)
-#define  DSC_INITIAL_OFFSET(initial_offset)		((initial_offset) << 16)
-#define  DSC_FINAL_OFFSET(final_offset)			((final_offset) << 0)
+#define  DSC_INITIAL_OFFSET_MASK		REG_GENMASK(31, 16)
+#define  DSC_FINAL_OFFSET_MASK			REG_GENMASK(15, 0)
+#define  DSC_INITIAL_OFFSET(initial_offset)	REG_FIELD_PREP(DSC_INITIAL_OFFSET_MASK, \
+							       initial_offset)
+#define  DSC_FINAL_OFFSET(final_offset)		REG_FIELD_PREP(DSC_FINAL_OFFSET_MASK, \
+							       final_offset)
 
 #define DSCA_PICTURE_PARAMETER_SET_9		_MMIO(0x6B224)
 #define DSCC_PICTURE_PARAMETER_SET_9		_MMIO(0x6BA24)
@@ -230,8 +256,12 @@
 #define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC)
-#define  DSC_RC_EDGE_FACTOR(rc_edge_fact)	((rc_edge_fact) << 16)
-#define  DSC_RC_MODEL_SIZE(rc_model_size)	((rc_model_size) << 0)
+#define  DSC_RC_EDGE_FACTOR_MASK		REG_GENMASK(19, 16)
+#define  DSC_RC_MODEL_SIZE_MASK			REG_GENMASK(15, 0)
+#define  DSC_RC_EDGE_FACTOR(rc_edge_fact)	REG_FIELD_PREP(DSC_RC_EDGE_FACTOR_MASK, \
+							       rc_edge_fact)
+#define  DSC_RC_MODEL_SIZE(rc_model_size)	REG_FIELD_PREP(DSC_RC_MODEL_SIZE_MASK, \
+							       rc_model_size)
 
 #define DSCA_PICTURE_PARAMETER_SET_10		_MMIO(0x6B228)
 #define DSCC_PICTURE_PARAMETER_SET_10		_MMIO(0x6BA28)
@@ -245,10 +275,16 @@
 #define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC)
-#define  DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low)		((rc_tgt_off_low) << 20)
-#define  DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high)	((rc_tgt_off_high) << 16)
-#define  DSC_RC_QUANT_INC_LIMIT1(lim)			((lim) << 8)
-#define  DSC_RC_QUANT_INC_LIMIT0(lim)			((lim) << 0)
+#define  DSC_RC_TGT_OFF_LOW_MASK			REG_GENMASK(23, 20)
+#define  DSC_RC_TGT_OFF_HIGH_MASK			REG_GENMASK(19, 16)
+#define  DSC_RC_QUANT_INC_LIMIT1_MASK			REG_GENMASK(12, 8)
+#define  DSC_RC_QUANT_INC_LIMIT0_MASK			REG_GENMASK(4, 0)
+#define  DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low)		REG_FIELD_PREP(DSC_RC_TGT_OFF_LOW_MASK, \
+								       rc_tgt_off_low)
+#define  DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high)	REG_FIELD_PREP(DSC_RC_TGT_OFF_HIGH_MASK, \
+								       rc_tgt_off_high)
+#define  DSC_RC_QUANT_INC_LIMIT1(lim)		REG_FIELD_PREP(DSC_RC_QUANT_INC_LIMIT1_MASK, lim)
+#define  DSC_RC_QUANT_INC_LIMIT0(lim)		REG_FIELD_PREP(DSC_RC_QUANT_INC_LIMIT0_MASK, lim)
 
 #define DSCA_PICTURE_PARAMETER_SET_11		_MMIO(0x6B22C)
 #define DSCC_PICTURE_PARAMETER_SET_11		_MMIO(0x6BA2C)
@@ -327,9 +363,15 @@
 #define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
-#define  DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame)	((slice_row_per_frame) << 20)
-#define  DSC_SLICE_PER_LINE(slice_per_line)		((slice_per_line) << 16)
-#define  DSC_SLICE_CHUNK_SIZE(slice_chunk_size)		((slice_chunk_size) << 0)
+#define  DSC_SLICE_ROW_PR_FRME_MASK			REG_GENMASK(31, 20)
+#define  DSC_SLICE_PER_LINE_MASK			REG_GENMASK(18, 16)
+#define  DSC_SLICE_CHUNK_SIZE_MASK			REG_GENMASK(15, 0)
+#define  DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame)	REG_FIELD_PREP(DSC_SLICE_ROW_PR_FRME_MASK, \
+								       slice_row_per_frame)
+#define  DSC_SLICE_PER_LINE(slice_per_line)		REG_FIELD_PREP(DSC_SLICE_PER_LINE_MASK, \
+								       slice_per_line)
+#define  DSC_SLICE_CHUNK_SIZE(slice_chunk_size)		REG_FIELD_PREP(DSC_SLICE_CHUNK_SIZE_MASK, \
+								       slice_chunk_size)
 
 /* Icelake Rate Control Buffer Threshold Registers */
 #define DSCA_RC_BUF_THRESH_0			_MMIO(0x6B230)
-- 
2.25.1

[Intel-gfx] [PATCH v7 2/8] drm/i915/vdsc: Add a check for dsc split cases

[Suraj Kandpal]

In intel_vdsc_get_config we only read the primary dsc engine register
and not take into account if the other dsc engine is in use and if
both registers have the same value or not this patche fixes that by
adding a check.

--v3
-Remove superfluos new line [Jani]
-Fix register naming [Jani]

--v5
-pps_temp0/pps_temp1 can be assigned where they are used [Ankit]

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vdsc.c | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 9d76c2756784..4437ade8fa87 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -996,7 +996,7 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
 	enum pipe pipe = crtc->pipe;
 	enum intel_display_power_domain power_domain;
 	intel_wakeref_t wakeref;
-	u32 dss_ctl1, dss_ctl2, pps0 = 0, pps1 = 0;
+	u32 dss_ctl1, dss_ctl2, pps0 = 0, pps1 = 0, pps_temp0, pps_temp1;
 
 	if (!intel_dsc_source_support(crtc_state))
 		return;
@@ -1022,11 +1022,23 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
 	/* PPS0 & PPS1 */
 	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
 		pps1 = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1);
+		if (crtc_state->dsc.dsc_split) {
+			pps_temp1 = intel_de_read(dev_priv, DSCC_PICTURE_PARAMETER_SET_1);
+			drm_WARN_ON(&dev_priv->drm, pps1 != pps_temp1);
+		}
 	} else {
 		pps0 = intel_de_read(dev_priv,
 				     ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe));
 		pps1 = intel_de_read(dev_priv,
 				     ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
+		if (crtc_state->dsc.dsc_split) {
+			pps_temp0 = intel_de_read(dev_priv,
+						  ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe));
+			pps_temp1 = intel_de_read(dev_priv,
+						  ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe));
+			drm_WARN_ON(&dev_priv->drm, pps0 != pps_temp0);
+			drm_WARN_ON(&dev_priv->drm, pps1 != pps_temp1);
+		}
 	}
 
 	vdsc_cfg->bits_per_pixel = pps1;
-- 
2.25.1

[Intel-gfx] [PATCH v7 3/8] drm/i915/vdsc: Add func to get no. of vdsc instances per pipe

[Suraj Kandpal]

We have a function that gets us the total of the vdsc engines being
used but not the no. of vdsc instances being used by each pipe.

--v6
-Change function to static

--v7
-Shorten name to intel_dsc_get_vdsc_per_pipe

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vdsc.c | 78 +++++++++++++----------
 1 file changed, 44 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 4437ade8fa87..dc86514d9e17 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -350,9 +350,14 @@ intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
 		return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
 }
 
+static int intel_dsc_get_vdsc_per_pipe(const struct intel_crtc_state *crtc_state)
+{
+	return crtc_state->dsc.dsc_split ? 2 : 1;
+}
+
 int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state)
 {
-	int num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1;
+	int num_vdsc_instances = intel_dsc_get_vdsc_per_pipe(crtc_state);
 
 	if (crtc_state->bigjoiner_pipes)
 		num_vdsc_instances *= 2;
@@ -372,6 +377,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 	u32 rc_range_params_dword[8];
 	int i = 0;
 	int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
+	int no_vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
 
 	/* Populate PICTURE_PARAMETER_SET_0 registers */
 	pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
@@ -401,14 +407,14 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 		 * If 2 VDSC instances are needed, configure PPS for second
 		 * VDSC
 		 */
-		if (crtc_state->dsc.dsc_split)
+		if (no_vdsc_instances_per_pipe > 1)
 			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_0,
 				       pps_val);
 	} else {
 		intel_de_write(dev_priv,
 			       ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe),
 			       pps_val);
-		if (crtc_state->dsc.dsc_split)
+		if (no_vdsc_instances_per_pipe > 1)
 			intel_de_write(dev_priv,
 				       ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe),
 				       pps_val);
@@ -425,14 +431,14 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 		 * If 2 VDSC instances are needed, configure PPS for second
 		 * VDSC
 		 */
-		if (crtc_state->dsc.dsc_split)
+		if (no_vdsc_instances_per_pipe > 1)
 			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_1,
 				       pps_val);
 	} else {
 		intel_de_write(dev_priv,
 			       ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe),
 			       pps_val);
-		if (crtc_state->dsc.dsc_split)
+		if (no_vdsc_instances_per_pipe > 1)
 			intel_de_write(dev_priv,
 				       ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe),
 				       pps_val);
@@ -450,14 +456,14 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 		 * If 2 VDSC instances are needed, configure PPS for second
 		 * VDSC
 		 */
-		if (crtc_state->dsc.dsc_split)
+		if (no_vdsc_instances_per_pipe > 1)
 			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_2,
 				       pps_val);
 	} else {
 		intel_de_write(dev_priv,
 			       ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe),
 			       pps_val);
-		if (crtc_state->dsc.dsc_split)
+		if (no_vdsc_instances_per_pipe > 1)
 			intel_de_write(dev_priv,
 				       ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe),
 				       pps_val);
@@ -475,14 +481,14 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 		 * If 2 VDSC instances are needed, configure PPS for second
 		 * VDSC
 		 */
-		if (crtc_state->dsc.dsc_split)
+		if (no_vdsc_instances_per_pipe > 1)
 			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_3,
 				       pps_val);
 	} else {
 		intel_de_write(dev_priv,
 			       ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe),
 			       pps_val);
-		if (crtc_state->dsc.dsc_split)
+		if (no_vdsc_instances_per_pipe > 1)
 			intel_de_write(dev_priv,
 				       ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe),
 				       pps_val);
@@ -500,14 +506,14 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 		 * If 2 VDSC instances are needed, configure PPS for second
 		 * VDSC
 		 */
-		if (crtc_state->dsc.dsc_split)
+		if (no_vdsc_instances_per_pipe > 1)
 			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_4,
 				       pps_val);
 	} else {
 		intel_de_write(dev_priv,
 			       ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe),
 			       pps_val);
-		if (crtc_state->dsc.dsc_split)
+		if (no_vdsc_instances_per_pipe > 1)
 			intel_de_write(dev_priv,
 				       ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe),
 				       pps_val);
@@ -525,14 +531,14 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 		 * If 2 VDSC instances are needed, configure PPS for second
 		 * VDSC
 		 */
-		if (crtc_state->dsc.dsc_split)
+		if (no_vdsc_instances_per_pipe > 1)
 			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_5,
 				       pps_val);
 	} else {
 		intel_de_write(dev_priv,
 			       ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe),
 			       pps_val);
-		if (crtc_state->dsc.dsc_split)
+		if (no_vdsc_instances_per_pipe > 1)
 			intel_de_write(dev_priv,
 				       ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe),
 				       pps_val);
@@ -552,14 +558,14 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 		 * If 2 VDSC instances are needed, configure PPS for second
 		 * VDSC
 		 */
-		if (crtc_state->dsc.dsc_split)
+		if (no_vdsc_instances_per_pipe > 1)
 			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_6,
 				       pps_val);
 	} else {
 		intel_de_write(dev_priv,
 			       ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe),
 			       pps_val);
-		if (crtc_state->dsc.dsc_split)
+		if (no_vdsc_instances_per_pipe > 1)
 			intel_de_write(dev_priv,
 				       ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe),
 				       pps_val);
@@ -577,14 +583,14 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 		 * If 2 VDSC instances are needed, configure PPS for second
 		 * VDSC
 		 */
-		if (crtc_state->dsc.dsc_split)
+		if (no_vdsc_instances_per_pipe > 1)
 			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_7,
 				       pps_val);
 	} else {
 		intel_de_write(dev_priv,
 			       ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe),
 			       pps_val);
-		if (crtc_state->dsc.dsc_split)
+		if (no_vdsc_instances_per_pipe > 1)
 			intel_de_write(dev_priv,
 				       ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe),
 				       pps_val);
@@ -602,14 +608,14 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 		 * If 2 VDSC instances are needed, configure PPS for second
 		 * VDSC
 		 */
-		if (crtc_state->dsc.dsc_split)
+		if (no_vdsc_instances_per_pipe > 1)
 			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_8,
 				       pps_val);
 	} else {
 		intel_de_write(dev_priv,
 			       ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe),
 			       pps_val);
-		if (crtc_state->dsc.dsc_split)
+		if (no_vdsc_instances_per_pipe > 1)
 			intel_de_write(dev_priv,
 				       ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe),
 				       pps_val);
@@ -627,14 +633,14 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 		 * If 2 VDSC instances are needed, configure PPS for second
 		 * VDSC
 		 */
-		if (crtc_state->dsc.dsc_split)
+		if (no_vdsc_instances_per_pipe > 1)
 			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_9,
 				       pps_val);
 	} else {
 		intel_de_write(dev_priv,
 			       ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe),
 			       pps_val);
-		if (crtc_state->dsc.dsc_split)
+		if (no_vdsc_instances_per_pipe > 1)
 			intel_de_write(dev_priv,
 				       ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe),
 				       pps_val);
@@ -654,14 +660,14 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 		 * If 2 VDSC instances are needed, configure PPS for second
 		 * VDSC
 		 */
-		if (crtc_state->dsc.dsc_split)
+		if (no_vdsc_instances_per_pipe > 1)
 			intel_de_write(dev_priv,
 				       DSCC_PICTURE_PARAMETER_SET_10, pps_val);
 	} else {
 		intel_de_write(dev_priv,
 			       ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe),
 			       pps_val);
-		if (crtc_state->dsc.dsc_split)
+		if (no_vdsc_instances_per_pipe > 1)
 			intel_de_write(dev_priv,
 				       ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe),
 				       pps_val);
@@ -682,14 +688,14 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 		 * If 2 VDSC instances are needed, configure PPS for second
 		 * VDSC
 		 */
-		if (crtc_state->dsc.dsc_split)
+		if (no_vdsc_instances_per_pipe > 1)
 			intel_de_write(dev_priv,
 				       DSCC_PICTURE_PARAMETER_SET_16, pps_val);
 	} else {
 		intel_de_write(dev_priv,
 			       ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe),
 			       pps_val);
-		if (crtc_state->dsc.dsc_split)
+		if (no_vdsc_instances_per_pipe > 1)
 			intel_de_write(dev_priv,
 				       ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe),
 				       pps_val);
@@ -703,7 +709,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 		intel_de_write(dev_priv,
 			       MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe),
 			       pps_val);
-		if (crtc_state->dsc.dsc_split)
+		if (no_vdsc_instances_per_pipe > 1)
 			intel_de_write(dev_priv,
 				       MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe),
 				       pps_val);
@@ -716,7 +722,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 		intel_de_write(dev_priv,
 			       MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe),
 			       pps_val);
-		if (crtc_state->dsc.dsc_split)
+		if (no_vdsc_instances_per_pipe > 1)
 			intel_de_write(dev_priv,
 				       MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe),
 				       pps_val);
@@ -740,7 +746,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 			       rc_buf_thresh_dword[2]);
 		intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1_UDW,
 			       rc_buf_thresh_dword[3]);
-		if (crtc_state->dsc.dsc_split) {
+		if (no_vdsc_instances_per_pipe > 1) {
 			intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0,
 				       rc_buf_thresh_dword[0]);
 			intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0_UDW,
@@ -759,7 +765,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 			       rc_buf_thresh_dword[2]);
 		intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),
 			       rc_buf_thresh_dword[3]);
-		if (crtc_state->dsc.dsc_split) {
+		if (no_vdsc_instances_per_pipe > 1) {
 			intel_de_write(dev_priv,
 				       ICL_DSC1_RC_BUF_THRESH_0(pipe),
 				       rc_buf_thresh_dword[0]);
@@ -805,7 +811,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 			       rc_range_params_dword[6]);
 		intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3_UDW,
 			       rc_range_params_dword[7]);
-		if (crtc_state->dsc.dsc_split) {
+		if (no_vdsc_instances_per_pipe > 1) {
 			intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_0,
 				       rc_range_params_dword[0]);
 			intel_de_write(dev_priv,
@@ -848,7 +854,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 		intel_de_write(dev_priv,
 			       ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe),
 			       rc_range_params_dword[7]);
-		if (crtc_state->dsc.dsc_split) {
+		if (no_vdsc_instances_per_pipe > 1) {
 			intel_de_write(dev_priv,
 				       ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe),
 				       rc_range_params_dword[0]);
@@ -954,6 +960,7 @@ void intel_dsc_enable(const struct intel_crtc_state *crtc_state)
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	u32 dss_ctl1_val = 0;
 	u32 dss_ctl2_val = 0;
+	int no_vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
 
 	if (!crtc_state->dsc.compression_enable)
 		return;
@@ -961,7 +968,7 @@ void intel_dsc_enable(const struct intel_crtc_state *crtc_state)
 	intel_dsc_pps_configure(crtc_state);
 
 	dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
-	if (crtc_state->dsc.dsc_split) {
+	if (no_vdsc_instances_per_pipe > 1) {
 		dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
 		dss_ctl1_val |= JOINER_ENABLE;
 	}
@@ -997,6 +1004,7 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
 	enum intel_display_power_domain power_domain;
 	intel_wakeref_t wakeref;
 	u32 dss_ctl1, dss_ctl2, pps0 = 0, pps1 = 0, pps_temp0, pps_temp1;
+	int no_vdsc_instances_per_pipe;
 
 	if (!intel_dsc_source_support(crtc_state))
 		return;
@@ -1019,10 +1027,12 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
 
 	/* FIXME: add more state readout as needed */
 
+	no_vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
+
 	/* PPS0 & PPS1 */
 	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
 		pps1 = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1);
-		if (crtc_state->dsc.dsc_split) {
+		if (no_vdsc_instances_per_pipe > 1) {
 			pps_temp1 = intel_de_read(dev_priv, DSCC_PICTURE_PARAMETER_SET_1);
 			drm_WARN_ON(&dev_priv->drm, pps1 != pps_temp1);
 		}
@@ -1031,7 +1041,7 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
 				     ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe));
 		pps1 = intel_de_read(dev_priv,
 				     ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
-		if (crtc_state->dsc.dsc_split) {
+		if (no_vdsc_instances_per_pipe > 1) {
 			pps_temp0 = intel_de_read(dev_priv,
 						  ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe));
 			pps_temp1 = intel_de_read(dev_priv,
-- 
2.25.1

[Intel-gfx] [PATCH v7 4/8] drm/i915/vdsc: Add function to read any PPS register

[Suraj Kandpal]

Add function to read any PPS register based on the
intel_dsc_pps enum provided. Add a function which will call the
new pps read function and place it in crtc state. Only PPS0 and
PPS1 are readout the rest of the registers will be read in upcoming
patches.

--v2
-Changes in read function as PPS enum is removed
-Initialize pps_val as 0 in pps_read func itself [Jani]
-Create a function that gets the required register and call that
in the common read function [Jani]
-Move the drm_WARN_ON one abstraction layer above [Jani]

--v3
-Send both reg values regardless of dsc engine no [Jani]
-Don't use num_vdsc_instances stick to dsc_split field [Ankit]

--v4
-Manipulate the reg values instead of creating MACRO to change
name of pps [Ankit]

--v5
-Read dsc reg values using array rather than individual variables
[Ankit]
-Loop the verification of all dsc engine reads to future proof it
[Ankit]
-Keep the fix me comment in this patch and remove it in later one
where we add other readouts [Ankit]
-Add switch statement that fills in the required registers based on
no of vdsc engines per pipe.

--v7
-Pass no of vdsc instances from read_reg function [Ankit]
-Fix issue where arrays do not get freed on return for read_and_verify
func [Ankit]

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 129 +++++++++++++-----
 .../gpu/drm/i915/display/intel_vdsc_regs.h    |  12 ++
 2 files changed, 105 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index dc86514d9e17..aa93228ca7af 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -365,6 +365,28 @@ int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state)
 	return num_vdsc_instances;
 }
 
+static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int pps,
+				  i915_reg_t *dsc_reg, int no_vdsc_per_pipe)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	enum pipe pipe = crtc->pipe;
+	bool pipe_dsc;
+
+	pipe_dsc = is_pipe_dsc(crtc, cpu_transcoder);
+
+	switch (no_vdsc_per_pipe) {
+	case 2:
+		dsc_reg[1] = pipe_dsc ? ICL_DSC1_PPS_REG(pipe, pps) : DSCC_PPS_REG(pps);
+		fallthrough;
+	case 1:
+		dsc_reg[0] = pipe_dsc ? ICL_DSC0_PPS_REG(pipe, pps) : DSCA_PPS_REG(pps);
+		break;
+	default:
+		MISSING_CASE(no_vdsc_per_pipe);
+	}
+}
+
 static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -994,17 +1016,83 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
 	}
 }
 
+static int intel_dsc_read_pps_reg(struct intel_crtc_state *crtc_state,
+				  int pps, u32 *pps_val)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+	const int no_vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
+	i915_reg_t *dsc_reg;
+	u32 *pps_temp;
+	int i, ret = 0;
+
+	dsc_reg = kcalloc(no_vdsc_per_pipe, sizeof(dsc_reg), GFP_KERNEL);
+	if (!dsc_reg)
+		return -ENOMEM;
+
+	pps_temp = kcalloc(no_vdsc_per_pipe, sizeof(pps_temp), GFP_KERNEL);
+	if (!pps_temp) {
+		kfree(dsc_reg);
+		return -ENOMEM;
+	}
+
+	*pps_val = 0;
+	intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, no_vdsc_per_pipe);
+	*pps_val = intel_de_read(i915, dsc_reg[0]);
+	if (no_vdsc_per_pipe > 1) {
+		for (i = 0; i < no_vdsc_per_pipe - 1; i++) {
+			pps_temp[i] = intel_de_read(i915, dsc_reg[i]);
+			pps_temp[i + 1] = intel_de_read(i915, dsc_reg[i + 1]);
+			if (pps_temp[i] != pps_temp[i + 1]) {
+				ret = 1;
+				break;
+			}
+		}
+	}
+
+	kfree(dsc_reg);
+	kfree(pps_temp);
+	return ret;
+}
+
+static void intel_dsc_read_and_verify_pps_reg(struct intel_crtc_state *crtc_state,
+					      int pps, u32 *pps_val)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+	int ret;
+
+	ret = intel_dsc_read_pps_reg(crtc_state, pps, pps_val);
+	drm_WARN_ON(&i915->drm, ret);
+}
+
+static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
+{
+	struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
+	u32 pps_temp1, pps_temp2;
+
+	/* FIXME: add more state readout as needed */
+
+	/* Readout PPS_0 and PPS_1 registers */
+	intel_dsc_read_and_verify_pps_reg(crtc_state, 0, &pps_temp1);
+	intel_dsc_read_and_verify_pps_reg(crtc_state, 1, &pps_temp2);
+
+	vdsc_cfg->bits_per_pixel = pps_temp2;
+
+	if (pps_temp1 & DSC_NATIVE_420_ENABLE)
+		vdsc_cfg->bits_per_pixel >>= 1;
+
+	crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
+}
+
 void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
-	enum pipe pipe = crtc->pipe;
 	enum intel_display_power_domain power_domain;
 	intel_wakeref_t wakeref;
-	u32 dss_ctl1, dss_ctl2, pps0 = 0, pps1 = 0, pps_temp0, pps_temp1;
-	int no_vdsc_instances_per_pipe;
+	u32 dss_ctl1, dss_ctl2;
 
 	if (!intel_dsc_source_support(crtc_state))
 		return;
@@ -1025,38 +1113,7 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
 	crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&
 		(dss_ctl1 & JOINER_ENABLE);
 
-	/* FIXME: add more state readout as needed */
-
-	no_vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
-
-	/* PPS0 & PPS1 */
-	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
-		pps1 = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1);
-		if (no_vdsc_instances_per_pipe > 1) {
-			pps_temp1 = intel_de_read(dev_priv, DSCC_PICTURE_PARAMETER_SET_1);
-			drm_WARN_ON(&dev_priv->drm, pps1 != pps_temp1);
-		}
-	} else {
-		pps0 = intel_de_read(dev_priv,
-				     ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe));
-		pps1 = intel_de_read(dev_priv,
-				     ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
-		if (no_vdsc_instances_per_pipe > 1) {
-			pps_temp0 = intel_de_read(dev_priv,
-						  ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe));
-			pps_temp1 = intel_de_read(dev_priv,
-						  ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe));
-			drm_WARN_ON(&dev_priv->drm, pps0 != pps_temp0);
-			drm_WARN_ON(&dev_priv->drm, pps1 != pps_temp1);
-		}
-	}
-
-	vdsc_cfg->bits_per_pixel = pps1;
-
-	if (pps0 & DSC_NATIVE_420_ENABLE)
-		vdsc_cfg->bits_per_pixel >>= 1;
-
-	crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
+	intel_dsc_get_pps_config(crtc_state);
 out:
 	intel_display_power_put(dev_priv, power_domain, wakeref);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
index 785ede31116e..862dc708c5fc 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
@@ -78,6 +78,10 @@
 /* Icelake Display Stream Compression Registers */
 #define DSCA_PICTURE_PARAMETER_SET_0		_MMIO(0x6B200)
 #define DSCC_PICTURE_PARAMETER_SET_0		_MMIO(0x6BA00)
+#define DSCA_PPS_0				0x6B200
+#define DSCC_PPS_0				0x6BA00
+#define DSCA_PPS_REG(pps)			_MMIO(DSCA_PPS_0 + (pps) * 4)
+#define DSCC_PPS_REG(pps)			_MMIO(DSCC_PPS_0 + (pps) * 4)
 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB	0x78270
 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB	0x78370
 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC	0x78470
@@ -88,6 +92,14 @@
 #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
+#define ICL_DSC0_PPS_0(pipe)			_PICK_EVEN((pipe) - PIPE_B, \
+							   _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
+							   _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
+#define ICL_DSC1_PPS_0(pipe)			_PICK_EVEN((pipe) - PIPE_B, \
+							   _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
+							   _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
+#define  ICL_DSC0_PPS_REG(pipe, pps)		_MMIO(ICL_DSC0_PPS_0(pipe) + ((pps) * 4))
+#define  ICL_DSC1_PPS_REG(pipe, pps)		_MMIO(ICL_DSC1_PPS_0(pipe) + ((pps) * 4))
 #define  DSC_NATIVE_422_ENABLE		BIT(23)
 #define  DSC_NATIVE_420_ENABLE		BIT(22)
 #define  DSC_ALT_ICH_SEL		(1 << 20)
-- 
2.25.1

Re: [Intel-gfx] [PATCH v7 4/8] drm/i915/vdsc: Add function to read any PPS register

[Jani Nikula]

On Tue, 08 Aug 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Add function to read any PPS register based on the
> intel_dsc_pps enum provided. Add a function which will call the
> new pps read function and place it in crtc state. Only PPS0 and
> PPS1 are readout the rest of the registers will be read in upcoming
> patches.
>
> --v2
> -Changes in read function as PPS enum is removed
> -Initialize pps_val as 0 in pps_read func itself [Jani]
> -Create a function that gets the required register and call that
> in the common read function [Jani]
> -Move the drm_WARN_ON one abstraction layer above [Jani]
>
> --v3
> -Send both reg values regardless of dsc engine no [Jani]
> -Don't use num_vdsc_instances stick to dsc_split field [Ankit]
>
> --v4
> -Manipulate the reg values instead of creating MACRO to change
> name of pps [Ankit]
>
> --v5
> -Read dsc reg values using array rather than individual variables
> [Ankit]
> -Loop the verification of all dsc engine reads to future proof it
> [Ankit]
> -Keep the fix me comment in this patch and remove it in later one
> where we add other readouts [Ankit]
> -Add switch statement that fills in the required registers based on
> no of vdsc engines per pipe.
>
> --v7
> -Pass no of vdsc instances from read_reg function [Ankit]
> -Fix issue where arrays do not get freed on return for read_and_verify
> func [Ankit]
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_vdsc.c     | 129 +++++++++++++-----
>  .../gpu/drm/i915/display/intel_vdsc_regs.h    |  12 ++
>  2 files changed, 105 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index dc86514d9e17..aa93228ca7af 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -365,6 +365,28 @@ int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state)
>  	return num_vdsc_instances;
>  }
>  
> +static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int pps,
> +				  i915_reg_t *dsc_reg, int no_vdsc_per_pipe)
> +{
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	enum pipe pipe = crtc->pipe;
> +	bool pipe_dsc;

Matter of taste, but to me that's four local variables too many for
small things like this.

> +
> +	pipe_dsc = is_pipe_dsc(crtc, cpu_transcoder);
> +
> +	switch (no_vdsc_per_pipe) {
> +	case 2:
> +		dsc_reg[1] = pipe_dsc ? ICL_DSC1_PPS_REG(pipe, pps) : DSCC_PPS_REG(pps);
> +		fallthrough;
> +	case 1:
> +		dsc_reg[0] = pipe_dsc ? ICL_DSC0_PPS_REG(pipe, pps) : DSCA_PPS_REG(pps);
> +		break;
> +	default:
> +		MISSING_CASE(no_vdsc_per_pipe);
> +	}
> +}
> +
>  static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -994,17 +1016,83 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
>  	}
>  }
>  
> +static int intel_dsc_read_pps_reg(struct intel_crtc_state *crtc_state,
> +				  int pps, u32 *pps_val)
> +{
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> +	const int no_vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
> +	i915_reg_t *dsc_reg;
> +	u32 *pps_temp;
> +	int i, ret = 0;
> +
> +	dsc_reg = kcalloc(no_vdsc_per_pipe, sizeof(dsc_reg), GFP_KERNEL);
> +	if (!dsc_reg)
> +		return -ENOMEM;
> +
> +	pps_temp = kcalloc(no_vdsc_per_pipe, sizeof(pps_temp), GFP_KERNEL);
> +	if (!pps_temp) {
> +		kfree(dsc_reg);
> +		return -ENOMEM;
> +	}

no_vdsc_per_pipe is at most 2. Temporary dynamic allocation is way
overkill here.

> +
> +	*pps_val = 0;
> +	intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, no_vdsc_per_pipe);
> +	*pps_val = intel_de_read(i915, dsc_reg[0]);
> +	if (no_vdsc_per_pipe > 1) {
> +		for (i = 0; i < no_vdsc_per_pipe - 1; i++) {
> +			pps_temp[i] = intel_de_read(i915, dsc_reg[i]);
> +			pps_temp[i + 1] = intel_de_read(i915, dsc_reg[i + 1]);
> +			if (pps_temp[i] != pps_temp[i + 1]) {
> +				ret = 1;
> +				break;
> +			}
> +		}
> +	}

What is going on here? Feels like this has grown way more complicated
than it needs to be since I last looked at this series. :(

> +
> +	kfree(dsc_reg);
> +	kfree(pps_temp);
> +	return ret;
> +}
> +
> +static void intel_dsc_read_and_verify_pps_reg(struct intel_crtc_state *crtc_state,
> +					      int pps, u32 *pps_val)
> +{
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> +	int ret;
> +
> +	ret = intel_dsc_read_pps_reg(crtc_state, pps, pps_val);
> +	drm_WARN_ON(&i915->drm, ret);
> +}
> +
> +static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
> +{
> +	struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
> +	u32 pps_temp1, pps_temp2;
> +
> +	/* FIXME: add more state readout as needed */
> +
> +	/* Readout PPS_0 and PPS_1 registers */
> +	intel_dsc_read_and_verify_pps_reg(crtc_state, 0, &pps_temp1);
> +	intel_dsc_read_and_verify_pps_reg(crtc_state, 1, &pps_temp2);
> +
> +	vdsc_cfg->bits_per_pixel = pps_temp2;
> +
> +	if (pps_temp1 & DSC_NATIVE_420_ENABLE)
> +		vdsc_cfg->bits_per_pixel >>= 1;
> +
> +	crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
> +}
> +
>  void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> -	enum pipe pipe = crtc->pipe;
>  	enum intel_display_power_domain power_domain;
>  	intel_wakeref_t wakeref;
> -	u32 dss_ctl1, dss_ctl2, pps0 = 0, pps1 = 0, pps_temp0, pps_temp1;
> -	int no_vdsc_instances_per_pipe;
> +	u32 dss_ctl1, dss_ctl2;
>  
>  	if (!intel_dsc_source_support(crtc_state))
>  		return;
> @@ -1025,38 +1113,7 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
>  	crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&
>  		(dss_ctl1 & JOINER_ENABLE);
>  
> -	/* FIXME: add more state readout as needed */
> -
> -	no_vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
> -
> -	/* PPS0 & PPS1 */
> -	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
> -		pps1 = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1);
> -		if (no_vdsc_instances_per_pipe > 1) {
> -			pps_temp1 = intel_de_read(dev_priv, DSCC_PICTURE_PARAMETER_SET_1);
> -			drm_WARN_ON(&dev_priv->drm, pps1 != pps_temp1);
> -		}
> -	} else {
> -		pps0 = intel_de_read(dev_priv,
> -				     ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe));
> -		pps1 = intel_de_read(dev_priv,
> -				     ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
> -		if (no_vdsc_instances_per_pipe > 1) {
> -			pps_temp0 = intel_de_read(dev_priv,
> -						  ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe));
> -			pps_temp1 = intel_de_read(dev_priv,
> -						  ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe));
> -			drm_WARN_ON(&dev_priv->drm, pps0 != pps_temp0);
> -			drm_WARN_ON(&dev_priv->drm, pps1 != pps_temp1);
> -		}
> -	}
> -
> -	vdsc_cfg->bits_per_pixel = pps1;
> -
> -	if (pps0 & DSC_NATIVE_420_ENABLE)
> -		vdsc_cfg->bits_per_pixel >>= 1;
> -
> -	crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
> +	intel_dsc_get_pps_config(crtc_state);
>  out:
>  	intel_display_power_put(dev_priv, power_domain, wakeref);
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> index 785ede31116e..862dc708c5fc 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> @@ -78,6 +78,10 @@
>  /* Icelake Display Stream Compression Registers */
>  #define DSCA_PICTURE_PARAMETER_SET_0		_MMIO(0x6B200)
>  #define DSCC_PICTURE_PARAMETER_SET_0		_MMIO(0x6BA00)
> +#define DSCA_PPS_0				0x6B200
> +#define DSCC_PPS_0				0x6BA00
> +#define DSCA_PPS_REG(pps)			_MMIO(DSCA_PPS_0 + (pps) * 4)
> +#define DSCC_PPS_REG(pps)			_MMIO(DSCC_PPS_0 + (pps) * 4)
>  #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB	0x78270
>  #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB	0x78370
>  #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC	0x78470
> @@ -88,6 +92,14 @@
>  #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
>  							   _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
>  							   _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
> +#define ICL_DSC0_PPS_0(pipe)			_PICK_EVEN((pipe) - PIPE_B, \
> +							   _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
> +							   _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
> +#define ICL_DSC1_PPS_0(pipe)			_PICK_EVEN((pipe) - PIPE_B, \
> +							   _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
> +							   _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
> +#define  ICL_DSC0_PPS_REG(pipe, pps)		_MMIO(ICL_DSC0_PPS_0(pipe) + ((pps) * 4))
> +#define  ICL_DSC1_PPS_REG(pipe, pps)		_MMIO(ICL_DSC1_PPS_0(pipe) + ((pps) * 4))
>  #define  DSC_NATIVE_422_ENABLE		BIT(23)
>  #define  DSC_NATIVE_420_ENABLE		BIT(22)
>  #define  DSC_ALT_ICH_SEL		(1 << 20)

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v7 4/8] drm/i915/vdsc: Add function to read any PPS register

[Kandpal, Suraj]

> 
> On Tue, 08 Aug 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> > Add function to read any PPS register based on the intel_dsc_pps enum
> > provided. Add a function which will call the new pps read function and
> > place it in crtc state. Only PPS0 and
> > PPS1 are readout the rest of the registers will be read in upcoming
> > patches.
> >
> > --v2
> > -Changes in read function as PPS enum is removed -Initialize pps_val
> > as 0 in pps_read func itself [Jani] -Create a function that gets the
> > required register and call that in the common read function [Jani]
> > -Move the drm_WARN_ON one abstraction layer above [Jani]
> >
> > --v3
> > -Send both reg values regardless of dsc engine no [Jani] -Don't use
> > num_vdsc_instances stick to dsc_split field [Ankit]
> >
> > --v4
> > -Manipulate the reg values instead of creating MACRO to change name of
> > pps [Ankit]
> >
> > --v5
> > -Read dsc reg values using array rather than individual variables
> > [Ankit] -Loop the verification of all dsc engine reads to future proof
> > it [Ankit] -Keep the fix me comment in this patch and remove it in
> > later one where we add other readouts [Ankit] -Add switch statement
> > that fills in the required registers based on no of vdsc engines per
> > pipe.
> >
> > --v7
> > -Pass no of vdsc instances from read_reg function [Ankit] -Fix issue
> > where arrays do not get freed on return for read_and_verify func
> > [Ankit]
> >
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_vdsc.c     | 129 +++++++++++++-----
> >  .../gpu/drm/i915/display/intel_vdsc_regs.h    |  12 ++
> >  2 files changed, 105 insertions(+), 36 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > index dc86514d9e17..aa93228ca7af 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > @@ -365,6 +365,28 @@ int intel_dsc_get_num_vdsc_instances(const
> struct intel_crtc_state *crtc_state)
> >  	return num_vdsc_instances;
> >  }
> >
> > +static void intel_dsc_get_pps_reg(const struct intel_crtc_state
> *crtc_state, int pps,
> > +				  i915_reg_t *dsc_reg, int no_vdsc_per_pipe)
> {
> > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > +	enum pipe pipe = crtc->pipe;
> > +	bool pipe_dsc;
> 
> Matter of taste, but to me that's four local variables too many for small things
> like this.
> 
> > +
> > +	pipe_dsc = is_pipe_dsc(crtc, cpu_transcoder);
> > +
> > +	switch (no_vdsc_per_pipe) {
> > +	case 2:
> > +		dsc_reg[1] = pipe_dsc ? ICL_DSC1_PPS_REG(pipe, pps) :
> DSCC_PPS_REG(pps);
> > +		fallthrough;
> > +	case 1:
> > +		dsc_reg[0] = pipe_dsc ? ICL_DSC0_PPS_REG(pipe, pps) :
> DSCA_PPS_REG(pps);
> > +		break;
> > +	default:
> > +		MISSING_CASE(no_vdsc_per_pipe);
> > +	}
> > +}
> > +
> >  static void intel_dsc_pps_configure(const struct intel_crtc_state
> > *crtc_state)  {
> >  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > @@ -994,17 +1016,83 @@ void intel_dsc_disable(const struct
> intel_crtc_state *old_crtc_state)
> >  	}
> >  }
> >
> > +static int intel_dsc_read_pps_reg(struct intel_crtc_state *crtc_state,
> > +				  int pps, u32 *pps_val)
> > +{
> > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > +	const int no_vdsc_per_pipe =
> intel_dsc_get_vdsc_per_pipe(crtc_state);
> > +	i915_reg_t *dsc_reg;
> > +	u32 *pps_temp;
> > +	int i, ret = 0;
> > +
> > +	dsc_reg = kcalloc(no_vdsc_per_pipe, sizeof(dsc_reg), GFP_KERNEL);
> > +	if (!dsc_reg)
> > +		return -ENOMEM;
> > +
> > +	pps_temp = kcalloc(no_vdsc_per_pipe, sizeof(pps_temp),
> GFP_KERNEL);
> > +	if (!pps_temp) {
> > +		kfree(dsc_reg);
> > +		return -ENOMEM;
> > +	}
> 
> no_vdsc_per_pipe is at most 2. Temporary dynamic allocation is way overkill
> here.

Yes but Ankit was of the thought that we can future proof this going forward if by any chance we get more dsc engines

> 
> > +
> > +	*pps_val = 0;
> > +	intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, no_vdsc_per_pipe);
> > +	*pps_val = intel_de_read(i915, dsc_reg[0]);
> > +	if (no_vdsc_per_pipe > 1) {
> > +		for (i = 0; i < no_vdsc_per_pipe - 1; i++) {
> > +			pps_temp[i] = intel_de_read(i915, dsc_reg[i]);
> > +			pps_temp[i + 1] = intel_de_read(i915, dsc_reg[i + 1]);
> > +			if (pps_temp[i] != pps_temp[i + 1]) {
> > +				ret = 1;
> > +				break;
> > +			}
> > +		}
> > +	}
> 
> What is going on here? Feels like this has grown way more complicated than
> it needs to be since I last looked at this series. :(

In case of more than 2 vdsc engines (just for future proofing) this loops looks at all the registers being used for
that pipe and makes sure everyone has the same value

Regards,
Suraj Kandpal
> 
> > +
> > +	kfree(dsc_reg);
> > +	kfree(pps_temp);
> > +	return ret;
> > +}
> > +
> > +static void intel_dsc_read_and_verify_pps_reg(struct intel_crtc_state
> *crtc_state,
> > +					      int pps, u32 *pps_val)
> > +{
> > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > +	int ret;
> > +
> > +	ret = intel_dsc_read_pps_reg(crtc_state, pps, pps_val);
> > +	drm_WARN_ON(&i915->drm, ret);
> > +}
> > +
> > +static void intel_dsc_get_pps_config(struct intel_crtc_state
> > +*crtc_state) {
> > +	struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
> > +	u32 pps_temp1, pps_temp2;
> > +
> > +	/* FIXME: add more state readout as needed */
> > +
> > +	/* Readout PPS_0 and PPS_1 registers */
> > +	intel_dsc_read_and_verify_pps_reg(crtc_state, 0, &pps_temp1);
> > +	intel_dsc_read_and_verify_pps_reg(crtc_state, 1, &pps_temp2);
> > +
> > +	vdsc_cfg->bits_per_pixel = pps_temp2;
> > +
> > +	if (pps_temp1 & DSC_NATIVE_420_ENABLE)
> > +		vdsc_cfg->bits_per_pixel >>= 1;
> > +
> > +	crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4; }
> > +
> >  void intel_dsc_get_config(struct intel_crtc_state *crtc_state)  {
> >  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > -	struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
> >  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > -	enum pipe pipe = crtc->pipe;
> >  	enum intel_display_power_domain power_domain;
> >  	intel_wakeref_t wakeref;
> > -	u32 dss_ctl1, dss_ctl2, pps0 = 0, pps1 = 0, pps_temp0, pps_temp1;
> > -	int no_vdsc_instances_per_pipe;
> > +	u32 dss_ctl1, dss_ctl2;
> >
> >  	if (!intel_dsc_source_support(crtc_state))
> >  		return;
> > @@ -1025,38 +1113,7 @@ void intel_dsc_get_config(struct intel_crtc_state
> *crtc_state)
> >  	crtc_state->dsc.dsc_split = (dss_ctl2 &
> RIGHT_BRANCH_VDSC_ENABLE) &&
> >  		(dss_ctl1 & JOINER_ENABLE);
> >
> > -	/* FIXME: add more state readout as needed */
> > -
> > -	no_vdsc_instances_per_pipe =
> intel_dsc_get_vdsc_per_pipe(crtc_state);
> > -
> > -	/* PPS0 & PPS1 */
> > -	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
> > -		pps1 = intel_de_read(dev_priv,
> DSCA_PICTURE_PARAMETER_SET_1);
> > -		if (no_vdsc_instances_per_pipe > 1) {
> > -			pps_temp1 = intel_de_read(dev_priv,
> DSCC_PICTURE_PARAMETER_SET_1);
> > -			drm_WARN_ON(&dev_priv->drm, pps1 !=
> pps_temp1);
> > -		}
> > -	} else {
> > -		pps0 = intel_de_read(dev_priv,
> > -
> ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe));
> > -		pps1 = intel_de_read(dev_priv,
> > -
> ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
> > -		if (no_vdsc_instances_per_pipe > 1) {
> > -			pps_temp0 = intel_de_read(dev_priv,
> > -
> ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe));
> > -			pps_temp1 = intel_de_read(dev_priv,
> > -
> ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe));
> > -			drm_WARN_ON(&dev_priv->drm, pps0 !=
> pps_temp0);
> > -			drm_WARN_ON(&dev_priv->drm, pps1 !=
> pps_temp1);
> > -		}
> > -	}
> > -
> > -	vdsc_cfg->bits_per_pixel = pps1;
> > -
> > -	if (pps0 & DSC_NATIVE_420_ENABLE)
> > -		vdsc_cfg->bits_per_pixel >>= 1;
> > -
> > -	crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
> > +	intel_dsc_get_pps_config(crtc_state);
> >  out:
> >  	intel_display_power_put(dev_priv, power_domain, wakeref);  } diff
> > --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> > b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> > index 785ede31116e..862dc708c5fc 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> > @@ -78,6 +78,10 @@
> >  /* Icelake Display Stream Compression Registers */
> >  #define DSCA_PICTURE_PARAMETER_SET_0		_MMIO(0x6B200)
> >  #define DSCC_PICTURE_PARAMETER_SET_0		_MMIO(0x6BA00)
> > +#define DSCA_PPS_0				0x6B200
> > +#define DSCC_PPS_0				0x6BA00
> > +#define DSCA_PPS_REG(pps)			_MMIO(DSCA_PPS_0
> + (pps) * 4)
> > +#define DSCC_PPS_REG(pps)			_MMIO(DSCC_PPS_0
> + (pps) * 4)
> >  #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB	0x78270
> >  #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB	0x78370
> >  #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC	0x78470
> > @@ -88,6 +92,14 @@
> >  #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe)
> 	_MMIO_PIPE((pipe) - PIPE_B, \
> >
> _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
> >
> _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
> > +#define ICL_DSC0_PPS_0(pipe)			_PICK_EVEN((pipe) -
> PIPE_B, \
> > +
> _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
> > +
> _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
> > +#define ICL_DSC1_PPS_0(pipe)			_PICK_EVEN((pipe) -
> PIPE_B, \
> > +
> _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
> > +
> _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
> > +#define  ICL_DSC0_PPS_REG(pipe, pps)
> 	_MMIO(ICL_DSC0_PPS_0(pipe) + ((pps) * 4))
> > +#define  ICL_DSC1_PPS_REG(pipe, pps)
> 	_MMIO(ICL_DSC1_PPS_0(pipe) + ((pps) * 4))
> >  #define  DSC_NATIVE_422_ENABLE		BIT(23)
> >  #define  DSC_NATIVE_420_ENABLE		BIT(22)
> >  #define  DSC_ALT_ICH_SEL		(1 << 20)
> 
> --
> Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v7 4/8] drm/i915/vdsc: Add function to read any PPS register

[Kandpal, Suraj]

++ Ankit
> >
> > On Tue, 08 Aug 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> > > Add function to read any PPS register based on the intel_dsc_pps
> > > enum provided. Add a function which will call the new pps read
> > > function and place it in crtc state. Only PPS0 and
> > > PPS1 are readout the rest of the registers will be read in upcoming
> > > patches.
> > >
> > > --v2
> > > -Changes in read function as PPS enum is removed -Initialize pps_val
> > > as 0 in pps_read func itself [Jani] -Create a function that gets the
> > > required register and call that in the common read function [Jani]
> > > -Move the drm_WARN_ON one abstraction layer above [Jani]
> > >
> > > --v3
> > > -Send both reg values regardless of dsc engine no [Jani] -Don't use
> > > num_vdsc_instances stick to dsc_split field [Ankit]
> > >
> > > --v4
> > > -Manipulate the reg values instead of creating MACRO to change name
> > > of pps [Ankit]
> > >
> > > --v5
> > > -Read dsc reg values using array rather than individual variables
> > > [Ankit] -Loop the verification of all dsc engine reads to future
> > > proof it [Ankit] -Keep the fix me comment in this patch and remove
> > > it in later one where we add other readouts [Ankit] -Add switch
> > > statement that fills in the required registers based on no of vdsc
> > > engines per pipe.
> > >
> > > --v7
> > > -Pass no of vdsc instances from read_reg function [Ankit] -Fix issue
> > > where arrays do not get freed on return for read_and_verify func
> > > [Ankit]
> > >
> > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_vdsc.c     | 129 +++++++++++++-----
> > >  .../gpu/drm/i915/display/intel_vdsc_regs.h    |  12 ++
> > >  2 files changed, 105 insertions(+), 36 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > > b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > > index dc86514d9e17..aa93228ca7af 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > > @@ -365,6 +365,28 @@ int intel_dsc_get_num_vdsc_instances(const
> > struct intel_crtc_state *crtc_state)
> > >  	return num_vdsc_instances;
> > >  }
> > >
> > > +static void intel_dsc_get_pps_reg(const struct intel_crtc_state
> > *crtc_state, int pps,
> > > +				  i915_reg_t *dsc_reg, int no_vdsc_per_pipe)
> > {
> > > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > > +	enum pipe pipe = crtc->pipe;
> > > +	bool pipe_dsc;
> >
> > Matter of taste, but to me that's four local variables too many for
> > small things like this.
> >
> > > +
> > > +	pipe_dsc = is_pipe_dsc(crtc, cpu_transcoder);
> > > +
> > > +	switch (no_vdsc_per_pipe) {
> > > +	case 2:
> > > +		dsc_reg[1] = pipe_dsc ? ICL_DSC1_PPS_REG(pipe, pps) :
> > DSCC_PPS_REG(pps);
> > > +		fallthrough;
> > > +	case 1:
> > > +		dsc_reg[0] = pipe_dsc ? ICL_DSC0_PPS_REG(pipe, pps) :
> > DSCA_PPS_REG(pps);
> > > +		break;
> > > +	default:
> > > +		MISSING_CASE(no_vdsc_per_pipe);
> > > +	}
> > > +}
> > > +
> > >  static void intel_dsc_pps_configure(const struct intel_crtc_state
> > > *crtc_state)  {
> > >  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > @@ -994,17 +1016,83 @@ void intel_dsc_disable(const struct
> > intel_crtc_state *old_crtc_state)
> > >  	}
> > >  }
> > >
> > > +static int intel_dsc_read_pps_reg(struct intel_crtc_state *crtc_state,
> > > +				  int pps, u32 *pps_val)
> > > +{
> > > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > > +	const int no_vdsc_per_pipe =
> > intel_dsc_get_vdsc_per_pipe(crtc_state);
> > > +	i915_reg_t *dsc_reg;
> > > +	u32 *pps_temp;
> > > +	int i, ret = 0;
> > > +
> > > +	dsc_reg = kcalloc(no_vdsc_per_pipe, sizeof(dsc_reg), GFP_KERNEL);
> > > +	if (!dsc_reg)
> > > +		return -ENOMEM;
> > > +
> > > +	pps_temp = kcalloc(no_vdsc_per_pipe, sizeof(pps_temp),
> > GFP_KERNEL);
> > > +	if (!pps_temp) {
> > > +		kfree(dsc_reg);
> > > +		return -ENOMEM;
> > > +	}
> >
> > no_vdsc_per_pipe is at most 2. Temporary dynamic allocation is way
> > overkill here.
> 
> Yes but Ankit was of the thought that we can future proof this going forward
> if by any chance we get more dsc engines
> 
> >
> > > +
> > > +	*pps_val = 0;
> > > +	intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, no_vdsc_per_pipe);
> > > +	*pps_val = intel_de_read(i915, dsc_reg[0]);
> > > +	if (no_vdsc_per_pipe > 1) {
> > > +		for (i = 0; i < no_vdsc_per_pipe - 1; i++) {
> > > +			pps_temp[i] = intel_de_read(i915, dsc_reg[i]);
> > > +			pps_temp[i + 1] = intel_de_read(i915, dsc_reg[i + 1]);
> > > +			if (pps_temp[i] != pps_temp[i + 1]) {
> > > +				ret = 1;
> > > +				break;
> > > +			}
> > > +		}
> > > +	}
> >
> > What is going on here? Feels like this has grown way more complicated
> > than it needs to be since I last looked at this series. :(
> 
> In case of more than 2 vdsc engines (just for future proofing) this loops looks
> at all the registers being used for that pipe and makes sure everyone has the
> same value
> 
> Regards,
> Suraj Kandpal
> >
> > > +
> > > +	kfree(dsc_reg);
> > > +	kfree(pps_temp);
> > > +	return ret;
> > > +}
> > > +
> > > +static void intel_dsc_read_and_verify_pps_reg(struct
> > > +intel_crtc_state
> > *crtc_state,
> > > +					      int pps, u32 *pps_val)
> > > +{
> > > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > > +	int ret;
> > > +
> > > +	ret = intel_dsc_read_pps_reg(crtc_state, pps, pps_val);
> > > +	drm_WARN_ON(&i915->drm, ret);
> > > +}
> > > +
> > > +static void intel_dsc_get_pps_config(struct intel_crtc_state
> > > +*crtc_state) {
> > > +	struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
> > > +	u32 pps_temp1, pps_temp2;
> > > +
> > > +	/* FIXME: add more state readout as needed */
> > > +
> > > +	/* Readout PPS_0 and PPS_1 registers */
> > > +	intel_dsc_read_and_verify_pps_reg(crtc_state, 0, &pps_temp1);
> > > +	intel_dsc_read_and_verify_pps_reg(crtc_state, 1, &pps_temp2);
> > > +
> > > +	vdsc_cfg->bits_per_pixel = pps_temp2;
> > > +
> > > +	if (pps_temp1 & DSC_NATIVE_420_ENABLE)
> > > +		vdsc_cfg->bits_per_pixel >>= 1;
> > > +
> > > +	crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4; }
> > > +
> > >  void intel_dsc_get_config(struct intel_crtc_state *crtc_state)  {
> > >  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > >  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > > -	struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
> > >  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > > -	enum pipe pipe = crtc->pipe;
> > >  	enum intel_display_power_domain power_domain;
> > >  	intel_wakeref_t wakeref;
> > > -	u32 dss_ctl1, dss_ctl2, pps0 = 0, pps1 = 0, pps_temp0, pps_temp1;
> > > -	int no_vdsc_instances_per_pipe;
> > > +	u32 dss_ctl1, dss_ctl2;
> > >
> > >  	if (!intel_dsc_source_support(crtc_state))
> > >  		return;
> > > @@ -1025,38 +1113,7 @@ void intel_dsc_get_config(struct
> > > intel_crtc_state
> > *crtc_state)
> > >  	crtc_state->dsc.dsc_split = (dss_ctl2 &
> > RIGHT_BRANCH_VDSC_ENABLE) &&
> > >  		(dss_ctl1 & JOINER_ENABLE);
> > >
> > > -	/* FIXME: add more state readout as needed */
> > > -
> > > -	no_vdsc_instances_per_pipe =
> > intel_dsc_get_vdsc_per_pipe(crtc_state);
> > > -
> > > -	/* PPS0 & PPS1 */
> > > -	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
> > > -		pps1 = intel_de_read(dev_priv,
> > DSCA_PICTURE_PARAMETER_SET_1);
> > > -		if (no_vdsc_instances_per_pipe > 1) {
> > > -			pps_temp1 = intel_de_read(dev_priv,
> > DSCC_PICTURE_PARAMETER_SET_1);
> > > -			drm_WARN_ON(&dev_priv->drm, pps1 !=
> > pps_temp1);
> > > -		}
> > > -	} else {
> > > -		pps0 = intel_de_read(dev_priv,
> > > -
> > ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe));
> > > -		pps1 = intel_de_read(dev_priv,
> > > -
> > ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
> > > -		if (no_vdsc_instances_per_pipe > 1) {
> > > -			pps_temp0 = intel_de_read(dev_priv,
> > > -
> > ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe));
> > > -			pps_temp1 = intel_de_read(dev_priv,
> > > -
> > ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe));
> > > -			drm_WARN_ON(&dev_priv->drm, pps0 !=
> > pps_temp0);
> > > -			drm_WARN_ON(&dev_priv->drm, pps1 !=
> > pps_temp1);
> > > -		}
> > > -	}
> > > -
> > > -	vdsc_cfg->bits_per_pixel = pps1;
> > > -
> > > -	if (pps0 & DSC_NATIVE_420_ENABLE)
> > > -		vdsc_cfg->bits_per_pixel >>= 1;
> > > -
> > > -	crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
> > > +	intel_dsc_get_pps_config(crtc_state);
> > >  out:
> > >  	intel_display_power_put(dev_priv, power_domain, wakeref);  } diff
> > > --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> > > b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> > > index 785ede31116e..862dc708c5fc 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> > > @@ -78,6 +78,10 @@
> > >  /* Icelake Display Stream Compression Registers */
> > >  #define DSCA_PICTURE_PARAMETER_SET_0
> 	_MMIO(0x6B200)
> > >  #define DSCC_PICTURE_PARAMETER_SET_0
> 	_MMIO(0x6BA00)
> > > +#define DSCA_PPS_0				0x6B200
> > > +#define DSCC_PPS_0				0x6BA00
> > > +#define DSCA_PPS_REG(pps)			_MMIO(DSCA_PPS_0
> > + (pps) * 4)
> > > +#define DSCC_PPS_REG(pps)			_MMIO(DSCC_PPS_0
> > + (pps) * 4)
> > >  #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB	0x78270
> > >  #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB	0x78370
> > >  #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC	0x78470
> > > @@ -88,6 +92,14 @@
> > >  #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe)
> > 	_MMIO_PIPE((pipe) - PIPE_B, \
> > >
> > _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
> > >
> > _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
> > > +#define ICL_DSC0_PPS_0(pipe)			_PICK_EVEN((pipe) -
> > PIPE_B, \
> > > +
> > _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
> > > +
> > _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
> > > +#define ICL_DSC1_PPS_0(pipe)			_PICK_EVEN((pipe) -
> > PIPE_B, \
> > > +
> > _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
> > > +
> > _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
> > > +#define  ICL_DSC0_PPS_REG(pipe, pps)
> > 	_MMIO(ICL_DSC0_PPS_0(pipe) + ((pps) * 4))
> > > +#define  ICL_DSC1_PPS_REG(pipe, pps)
> > 	_MMIO(ICL_DSC1_PPS_0(pipe) + ((pps) * 4))
> > >  #define  DSC_NATIVE_422_ENABLE		BIT(23)
> > >  #define  DSC_NATIVE_420_ENABLE		BIT(22)
> > >  #define  DSC_ALT_ICH_SEL		(1 << 20)
> >
> > --
> > Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v7 4/8] drm/i915/vdsc: Add function to read any PPS register

[Jani Nikula]

On Wed, 16 Aug 2023, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
>> 
>> On Tue, 08 Aug 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
>> > Add function to read any PPS register based on the intel_dsc_pps enum
>> > provided. Add a function which will call the new pps read function and
>> > place it in crtc state. Only PPS0 and
>> > PPS1 are readout the rest of the registers will be read in upcoming
>> > patches.
>> >
>> > --v2
>> > -Changes in read function as PPS enum is removed -Initialize pps_val
>> > as 0 in pps_read func itself [Jani] -Create a function that gets the
>> > required register and call that in the common read function [Jani]
>> > -Move the drm_WARN_ON one abstraction layer above [Jani]
>> >
>> > --v3
>> > -Send both reg values regardless of dsc engine no [Jani] -Don't use
>> > num_vdsc_instances stick to dsc_split field [Ankit]
>> >
>> > --v4
>> > -Manipulate the reg values instead of creating MACRO to change name of
>> > pps [Ankit]
>> >
>> > --v5
>> > -Read dsc reg values using array rather than individual variables
>> > [Ankit] -Loop the verification of all dsc engine reads to future proof
>> > it [Ankit] -Keep the fix me comment in this patch and remove it in
>> > later one where we add other readouts [Ankit] -Add switch statement
>> > that fills in the required registers based on no of vdsc engines per
>> > pipe.
>> >
>> > --v7
>> > -Pass no of vdsc instances from read_reg function [Ankit] -Fix issue
>> > where arrays do not get freed on return for read_and_verify func
>> > [Ankit]
>> >
>> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/display/intel_vdsc.c     | 129 +++++++++++++-----
>> >  .../gpu/drm/i915/display/intel_vdsc_regs.h    |  12 ++
>> >  2 files changed, 105 insertions(+), 36 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> > b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> > index dc86514d9e17..aa93228ca7af 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> > @@ -365,6 +365,28 @@ int intel_dsc_get_num_vdsc_instances(const
>> struct intel_crtc_state *crtc_state)
>> >  	return num_vdsc_instances;
>> >  }
>> >
>> > +static void intel_dsc_get_pps_reg(const struct intel_crtc_state
>> *crtc_state, int pps,
>> > +				  i915_reg_t *dsc_reg, int no_vdsc_per_pipe)
>> {
>> > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> > +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>> > +	enum pipe pipe = crtc->pipe;
>> > +	bool pipe_dsc;
>> 
>> Matter of taste, but to me that's four local variables too many for small things
>> like this.
>> 
>> > +
>> > +	pipe_dsc = is_pipe_dsc(crtc, cpu_transcoder);
>> > +
>> > +	switch (no_vdsc_per_pipe) {
>> > +	case 2:
>> > +		dsc_reg[1] = pipe_dsc ? ICL_DSC1_PPS_REG(pipe, pps) :
>> DSCC_PPS_REG(pps);
>> > +		fallthrough;
>> > +	case 1:
>> > +		dsc_reg[0] = pipe_dsc ? ICL_DSC0_PPS_REG(pipe, pps) :
>> DSCA_PPS_REG(pps);
>> > +		break;
>> > +	default:
>> > +		MISSING_CASE(no_vdsc_per_pipe);
>> > +	}
>> > +}
>> > +
>> >  static void intel_dsc_pps_configure(const struct intel_crtc_state
>> > *crtc_state)  {
>> >  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> > @@ -994,17 +1016,83 @@ void intel_dsc_disable(const struct
>> intel_crtc_state *old_crtc_state)
>> >  	}
>> >  }
>> >
>> > +static int intel_dsc_read_pps_reg(struct intel_crtc_state *crtc_state,
>> > +				  int pps, u32 *pps_val)
>> > +{
>> > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> > +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>> > +	const int no_vdsc_per_pipe =
>> intel_dsc_get_vdsc_per_pipe(crtc_state);
>> > +	i915_reg_t *dsc_reg;
>> > +	u32 *pps_temp;
>> > +	int i, ret = 0;
>> > +
>> > +	dsc_reg = kcalloc(no_vdsc_per_pipe, sizeof(dsc_reg), GFP_KERNEL);
>> > +	if (!dsc_reg)
>> > +		return -ENOMEM;
>> > +
>> > +	pps_temp = kcalloc(no_vdsc_per_pipe, sizeof(pps_temp),
>> GFP_KERNEL);
>> > +	if (!pps_temp) {
>> > +		kfree(dsc_reg);
>> > +		return -ENOMEM;
>> > +	}
>> 
>> no_vdsc_per_pipe is at most 2. Temporary dynamic allocation is way overkill
>> here.
>
> Yes but Ankit was of the thought that we can future proof this going forward if by any chance we get more dsc engines

Keep it simple. There's going to have to be quite a few engines per pipe
before this needs to be dynamically allocated. This is also future
proof, and we'll only need to update one value to expand to more.

	i915_reg_t dsc_reg[2];

	drm_WARN_ON_ONCE(&i915->drm, ARRAY_SIZE(dsc_reg) < intel_dsc_get_vdsc_per_pipe(crtc_state));

	intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, ARRAY_SIZE(dsc_reg));

	for (i = 0; i < min(ARRAY_SIZE(dsc_reg), intel_dsc_get_vdsc_per_pipe(crtc_state)); i++) {
        	u32 val;

	        val = intel_de_read(i915, dsc_reg[i])

                if (i == 0)
                	*pps_val = val;
                else if (val != *pps_val)
                	return -EINVAL;
	}

	return 0;

Adjust intel_dsc_get_pps_reg() accordingly to respect size of the
dsc_reg destination:

static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int pps,
				  i915_reg_t *dsc_reg, int dsc_reg_size)

>
>> 
>> > +
>> > +	*pps_val = 0;
>> > +	intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, no_vdsc_per_pipe);
>> > +	*pps_val = intel_de_read(i915, dsc_reg[0]);
>> > +	if (no_vdsc_per_pipe > 1) {
>> > +		for (i = 0; i < no_vdsc_per_pipe - 1; i++) {
>> > +			pps_temp[i] = intel_de_read(i915, dsc_reg[i]);
>> > +			pps_temp[i + 1] = intel_de_read(i915, dsc_reg[i + 1]);
>> > +			if (pps_temp[i] != pps_temp[i + 1]) {
>> > +				ret = 1;

Please don't use random magic numbers for return codes.

>> > +				break;
>> > +			}
>> > +		}
>> > +	}
>> 
>> What is going on here? Feels like this has grown way more complicated than
>> it needs to be since I last looked at this series. :(
>
> In case of more than 2 vdsc engines (just for future proofing) this loops looks at all the registers being used for
> that pipe and makes sure everyone has the same value

Right. But for that you only need to store one value to compare, not all
of them.

Always try to find the simple solution!


BR,
Jani.

>
> Regards,
> Suraj Kandpal
>> 
>> > +
>> > +	kfree(dsc_reg);
>> > +	kfree(pps_temp);
>> > +	return ret;
>> > +}
>> > +
>> > +static void intel_dsc_read_and_verify_pps_reg(struct intel_crtc_state
>> *crtc_state,
>> > +					      int pps, u32 *pps_val)
>> > +{
>> > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> > +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>> > +	int ret;
>> > +
>> > +	ret = intel_dsc_read_pps_reg(crtc_state, pps, pps_val);
>> > +	drm_WARN_ON(&i915->drm, ret);
>> > +}
>> > +
>> > +static void intel_dsc_get_pps_config(struct intel_crtc_state
>> > +*crtc_state) {
>> > +	struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
>> > +	u32 pps_temp1, pps_temp2;
>> > +
>> > +	/* FIXME: add more state readout as needed */
>> > +
>> > +	/* Readout PPS_0 and PPS_1 registers */
>> > +	intel_dsc_read_and_verify_pps_reg(crtc_state, 0, &pps_temp1);
>> > +	intel_dsc_read_and_verify_pps_reg(crtc_state, 1, &pps_temp2);
>> > +
>> > +	vdsc_cfg->bits_per_pixel = pps_temp2;
>> > +
>> > +	if (pps_temp1 & DSC_NATIVE_420_ENABLE)
>> > +		vdsc_cfg->bits_per_pixel >>= 1;
>> > +
>> > +	crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4; }
>> > +
>> >  void intel_dsc_get_config(struct intel_crtc_state *crtc_state)  {
>> >  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> >  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> > -	struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
>> >  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>> > -	enum pipe pipe = crtc->pipe;
>> >  	enum intel_display_power_domain power_domain;
>> >  	intel_wakeref_t wakeref;
>> > -	u32 dss_ctl1, dss_ctl2, pps0 = 0, pps1 = 0, pps_temp0, pps_temp1;
>> > -	int no_vdsc_instances_per_pipe;
>> > +	u32 dss_ctl1, dss_ctl2;
>> >
>> >  	if (!intel_dsc_source_support(crtc_state))
>> >  		return;
>> > @@ -1025,38 +1113,7 @@ void intel_dsc_get_config(struct intel_crtc_state
>> *crtc_state)
>> >  	crtc_state->dsc.dsc_split = (dss_ctl2 &
>> RIGHT_BRANCH_VDSC_ENABLE) &&
>> >  		(dss_ctl1 & JOINER_ENABLE);
>> >
>> > -	/* FIXME: add more state readout as needed */
>> > -
>> > -	no_vdsc_instances_per_pipe =
>> intel_dsc_get_vdsc_per_pipe(crtc_state);
>> > -
>> > -	/* PPS0 & PPS1 */
>> > -	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
>> > -		pps1 = intel_de_read(dev_priv,
>> DSCA_PICTURE_PARAMETER_SET_1);
>> > -		if (no_vdsc_instances_per_pipe > 1) {
>> > -			pps_temp1 = intel_de_read(dev_priv,
>> DSCC_PICTURE_PARAMETER_SET_1);
>> > -			drm_WARN_ON(&dev_priv->drm, pps1 !=
>> pps_temp1);
>> > -		}
>> > -	} else {
>> > -		pps0 = intel_de_read(dev_priv,
>> > -
>> ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe));
>> > -		pps1 = intel_de_read(dev_priv,
>> > -
>> ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
>> > -		if (no_vdsc_instances_per_pipe > 1) {
>> > -			pps_temp0 = intel_de_read(dev_priv,
>> > -
>> ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe));
>> > -			pps_temp1 = intel_de_read(dev_priv,
>> > -
>> ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe));
>> > -			drm_WARN_ON(&dev_priv->drm, pps0 !=
>> pps_temp0);
>> > -			drm_WARN_ON(&dev_priv->drm, pps1 !=
>> pps_temp1);
>> > -		}
>> > -	}
>> > -
>> > -	vdsc_cfg->bits_per_pixel = pps1;
>> > -
>> > -	if (pps0 & DSC_NATIVE_420_ENABLE)
>> > -		vdsc_cfg->bits_per_pixel >>= 1;
>> > -
>> > -	crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
>> > +	intel_dsc_get_pps_config(crtc_state);
>> >  out:
>> >  	intel_display_power_put(dev_priv, power_domain, wakeref);  } diff
>> > --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
>> > b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
>> > index 785ede31116e..862dc708c5fc 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
>> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
>> > @@ -78,6 +78,10 @@
>> >  /* Icelake Display Stream Compression Registers */
>> >  #define DSCA_PICTURE_PARAMETER_SET_0		_MMIO(0x6B200)
>> >  #define DSCC_PICTURE_PARAMETER_SET_0		_MMIO(0x6BA00)
>> > +#define DSCA_PPS_0				0x6B200
>> > +#define DSCC_PPS_0				0x6BA00
>> > +#define DSCA_PPS_REG(pps)			_MMIO(DSCA_PPS_0
>> + (pps) * 4)
>> > +#define DSCC_PPS_REG(pps)			_MMIO(DSCC_PPS_0
>> + (pps) * 4)
>> >  #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB	0x78270
>> >  #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB	0x78370
>> >  #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC	0x78470
>> > @@ -88,6 +92,14 @@
>> >  #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe)
>> 	_MMIO_PIPE((pipe) - PIPE_B, \
>> >
>> _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
>> >
>> _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
>> > +#define ICL_DSC0_PPS_0(pipe)			_PICK_EVEN((pipe) -
>> PIPE_B, \
>> > +
>> _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
>> > +
>> _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
>> > +#define ICL_DSC1_PPS_0(pipe)			_PICK_EVEN((pipe) -
>> PIPE_B, \
>> > +
>> _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
>> > +
>> _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
>> > +#define  ICL_DSC0_PPS_REG(pipe, pps)
>> 	_MMIO(ICL_DSC0_PPS_0(pipe) + ((pps) * 4))
>> > +#define  ICL_DSC1_PPS_REG(pipe, pps)
>> 	_MMIO(ICL_DSC1_PPS_0(pipe) + ((pps) * 4))
>> >  #define  DSC_NATIVE_422_ENABLE		BIT(23)
>> >  #define  DSC_NATIVE_420_ENABLE		BIT(22)
>> >  #define  DSC_ALT_ICH_SEL		(1 << 20)
>> 
>> --
>> Jani Nikula, Intel Open Source Graphics Center

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v7 4/8] drm/i915/vdsc: Add function to read any PPS register

[Kandpal, Suraj]

> 
> On Wed, 16 Aug 2023, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
> >>
> >> On Tue, 08 Aug 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> >> > Add function to read any PPS register based on the intel_dsc_pps
> >> > enum provided. Add a function which will call the new pps read
> >> > function and place it in crtc state. Only PPS0 and
> >> > PPS1 are readout the rest of the registers will be read in upcoming
> >> > patches.
> >> >
> >> > --v2
> >> > -Changes in read function as PPS enum is removed -Initialize
> >> > pps_val as 0 in pps_read func itself [Jani] -Create a function that
> >> > gets the required register and call that in the common read
> >> > function [Jani] -Move the drm_WARN_ON one abstraction layer above
> >> > [Jani]
> >> >
> >> > --v3
> >> > -Send both reg values regardless of dsc engine no [Jani] -Don't use
> >> > num_vdsc_instances stick to dsc_split field [Ankit]
> >> >
> >> > --v4
> >> > -Manipulate the reg values instead of creating MACRO to change name
> >> > of pps [Ankit]
> >> >
> >> > --v5
> >> > -Read dsc reg values using array rather than individual variables
> >> > [Ankit] -Loop the verification of all dsc engine reads to future
> >> > proof it [Ankit] -Keep the fix me comment in this patch and remove
> >> > it in later one where we add other readouts [Ankit] -Add switch
> >> > statement that fills in the required registers based on no of vdsc
> >> > engines per pipe.
> >> >
> >> > --v7
> >> > -Pass no of vdsc instances from read_reg function [Ankit] -Fix
> >> > issue where arrays do not get freed on return for read_and_verify
> >> > func [Ankit]
> >> >
> >> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> >> > ---
> >> >  drivers/gpu/drm/i915/display/intel_vdsc.c     | 129 +++++++++++++-----
> >> >  .../gpu/drm/i915/display/intel_vdsc_regs.h    |  12 ++
> >> >  2 files changed, 105 insertions(+), 36 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> >> > b/drivers/gpu/drm/i915/display/intel_vdsc.c
> >> > index dc86514d9e17..aa93228ca7af 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> >> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> >> > @@ -365,6 +365,28 @@ int intel_dsc_get_num_vdsc_instances(const
> >> struct intel_crtc_state *crtc_state)
> >> >  	return num_vdsc_instances;
> >> >  }
> >> >
> >> > +static void intel_dsc_get_pps_reg(const struct intel_crtc_state
> >> *crtc_state, int pps,
> >> > +				  i915_reg_t *dsc_reg, int no_vdsc_per_pipe)
> >> {
> >> > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >> > +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> >> > +	enum pipe pipe = crtc->pipe;
> >> > +	bool pipe_dsc;
> >>
> >> Matter of taste, but to me that's four local variables too many for
> >> small things like this.
> >>
> >> > +
> >> > +	pipe_dsc = is_pipe_dsc(crtc, cpu_transcoder);
> >> > +
> >> > +	switch (no_vdsc_per_pipe) {
> >> > +	case 2:
> >> > +		dsc_reg[1] = pipe_dsc ? ICL_DSC1_PPS_REG(pipe, pps) :
> >> DSCC_PPS_REG(pps);
> >> > +		fallthrough;
> >> > +	case 1:
> >> > +		dsc_reg[0] = pipe_dsc ? ICL_DSC0_PPS_REG(pipe, pps) :
> >> DSCA_PPS_REG(pps);
> >> > +		break;
> >> > +	default:
> >> > +		MISSING_CASE(no_vdsc_per_pipe);
> >> > +	}
> >> > +}
> >> > +
> >> >  static void intel_dsc_pps_configure(const struct intel_crtc_state
> >> > *crtc_state)  {
> >> >  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >> > @@ -994,17 +1016,83 @@ void intel_dsc_disable(const struct
> >> intel_crtc_state *old_crtc_state)
> >> >  	}
> >> >  }
> >> >
> >> > +static int intel_dsc_read_pps_reg(struct intel_crtc_state *crtc_state,
> >> > +				  int pps, u32 *pps_val)
> >> > +{
> >> > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >> > +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> >> > +	const int no_vdsc_per_pipe =
> >> intel_dsc_get_vdsc_per_pipe(crtc_state);
> >> > +	i915_reg_t *dsc_reg;
> >> > +	u32 *pps_temp;
> >> > +	int i, ret = 0;
> >> > +
> >> > +	dsc_reg = kcalloc(no_vdsc_per_pipe, sizeof(dsc_reg), GFP_KERNEL);
> >> > +	if (!dsc_reg)
> >> > +		return -ENOMEM;
> >> > +
> >> > +	pps_temp = kcalloc(no_vdsc_per_pipe, sizeof(pps_temp),
> >> GFP_KERNEL);
> >> > +	if (!pps_temp) {
> >> > +		kfree(dsc_reg);
> >> > +		return -ENOMEM;
> >> > +	}
> >>
> >> no_vdsc_per_pipe is at most 2. Temporary dynamic allocation is way
> >> overkill here.
> >
> > Yes but Ankit was of the thought that we can future proof this going
> > forward if by any chance we get more dsc engines
> 
> Keep it simple. There's going to have to be quite a few engines per pipe
> before this needs to be dynamically allocated. This is also future proof, and
> we'll only need to update one value to expand to more.
> 
> 	i915_reg_t dsc_reg[2];
> 
> 	drm_WARN_ON_ONCE(&i915->drm, ARRAY_SIZE(dsc_reg) <
> intel_dsc_get_vdsc_per_pipe(crtc_state));
> 
> 	intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg,
> ARRAY_SIZE(dsc_reg));
> 
> 	for (i = 0; i < min(ARRAY_SIZE(dsc_reg),
> intel_dsc_get_vdsc_per_pipe(crtc_state)); i++) {
>         	u32 val;
> 
> 	        val = intel_de_read(i915, dsc_reg[i])
> 
>                 if (i == 0)
>                 	*pps_val = val;
>                 else if (val != *pps_val)
>                 	return -EINVAL;
> 	}
> 
> 	return 0;
> 
> Adjust intel_dsc_get_pps_reg() accordingly to respect size of the dsc_reg
> destination:
> 
> static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state,
> int pps,
> 				  i915_reg_t *dsc_reg, int dsc_reg_size)
> 

Sure got it will work on this and float a new version


> >
> >>
> >> > +
> >> > +	*pps_val = 0;
> >> > +	intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, no_vdsc_per_pipe);
> >> > +	*pps_val = intel_de_read(i915, dsc_reg[0]);
> >> > +	if (no_vdsc_per_pipe > 1) {
> >> > +		for (i = 0; i < no_vdsc_per_pipe - 1; i++) {
> >> > +			pps_temp[i] = intel_de_read(i915, dsc_reg[i]);
> >> > +			pps_temp[i + 1] = intel_de_read(i915, dsc_reg[i + 1]);
> >> > +			if (pps_temp[i] != pps_temp[i + 1]) {
> >> > +				ret = 1;
> 
> Please don't use random magic numbers for return codes.
> 

Okay will return a -EINVAL here in that case as pointed out above

> >> > +				break;
> >> > +			}
> >> > +		}
> >> > +	}
> >>
> >> What is going on here? Feels like this has grown way more complicated
> >> than it needs to be since I last looked at this series. :(
> >
> > In case of more than 2 vdsc engines (just for future proofing) this
> > loops looks at all the registers being used for that pipe and makes
> > sure everyone has the same value
> 
> Right. But for that you only need to store one value to compare, not all of
> them.
> 
> Always try to find the simple solution!
> 

Sure Jani will keep that in mind and will also fix this in the next revision.

Regards,
Suraj Kandpal
> 
> BR,
> Jani.
> 
> >
> > Regards,
> > Suraj Kandpal
> >>
> >> > +
> >> > +	kfree(dsc_reg);
> >> > +	kfree(pps_temp);
> >> > +	return ret;
> >> > +}
> >> > +
> >> > +static void intel_dsc_read_and_verify_pps_reg(struct
> >> > +intel_crtc_state
> >> *crtc_state,
> >> > +					      int pps, u32 *pps_val)
> >> > +{
> >> > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >> > +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> >> > +	int ret;
> >> > +
> >> > +	ret = intel_dsc_read_pps_reg(crtc_state, pps, pps_val);
> >> > +	drm_WARN_ON(&i915->drm, ret);
> >> > +}
> >> > +
> >> > +static void intel_dsc_get_pps_config(struct intel_crtc_state
> >> > +*crtc_state) {
> >> > +	struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
> >> > +	u32 pps_temp1, pps_temp2;
> >> > +
> >> > +	/* FIXME: add more state readout as needed */
> >> > +
> >> > +	/* Readout PPS_0 and PPS_1 registers */
> >> > +	intel_dsc_read_and_verify_pps_reg(crtc_state, 0, &pps_temp1);
> >> > +	intel_dsc_read_and_verify_pps_reg(crtc_state, 1, &pps_temp2);
> >> > +
> >> > +	vdsc_cfg->bits_per_pixel = pps_temp2;
> >> > +
> >> > +	if (pps_temp1 & DSC_NATIVE_420_ENABLE)
> >> > +		vdsc_cfg->bits_per_pixel >>= 1;
> >> > +
> >> > +	crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4; }
> >> > +
> >> >  void intel_dsc_get_config(struct intel_crtc_state *crtc_state)  {
> >> >  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >> >  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >> > -	struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
> >> >  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> >> > -	enum pipe pipe = crtc->pipe;
> >> >  	enum intel_display_power_domain power_domain;
> >> >  	intel_wakeref_t wakeref;
> >> > -	u32 dss_ctl1, dss_ctl2, pps0 = 0, pps1 = 0, pps_temp0, pps_temp1;
> >> > -	int no_vdsc_instances_per_pipe;
> >> > +	u32 dss_ctl1, dss_ctl2;
> >> >
> >> >  	if (!intel_dsc_source_support(crtc_state))
> >> >  		return;
> >> > @@ -1025,38 +1113,7 @@ void intel_dsc_get_config(struct
> >> > intel_crtc_state
> >> *crtc_state)
> >> >  	crtc_state->dsc.dsc_split = (dss_ctl2 &
> >> RIGHT_BRANCH_VDSC_ENABLE) &&
> >> >  		(dss_ctl1 & JOINER_ENABLE);
> >> >
> >> > -	/* FIXME: add more state readout as needed */
> >> > -
> >> > -	no_vdsc_instances_per_pipe =
> >> intel_dsc_get_vdsc_per_pipe(crtc_state);
> >> > -
> >> > -	/* PPS0 & PPS1 */
> >> > -	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
> >> > -		pps1 = intel_de_read(dev_priv,
> >> DSCA_PICTURE_PARAMETER_SET_1);
> >> > -		if (no_vdsc_instances_per_pipe > 1) {
> >> > -			pps_temp1 = intel_de_read(dev_priv,
> >> DSCC_PICTURE_PARAMETER_SET_1);
> >> > -			drm_WARN_ON(&dev_priv->drm, pps1 !=
> >> pps_temp1);
> >> > -		}
> >> > -	} else {
> >> > -		pps0 = intel_de_read(dev_priv,
> >> > -
> >> ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe));
> >> > -		pps1 = intel_de_read(dev_priv,
> >> > -
> >> ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
> >> > -		if (no_vdsc_instances_per_pipe > 1) {
> >> > -			pps_temp0 = intel_de_read(dev_priv,
> >> > -
> >> ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe));
> >> > -			pps_temp1 = intel_de_read(dev_priv,
> >> > -
> >> ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe));
> >> > -			drm_WARN_ON(&dev_priv->drm, pps0 !=
> >> pps_temp0);
> >> > -			drm_WARN_ON(&dev_priv->drm, pps1 !=
> >> pps_temp1);
> >> > -		}
> >> > -	}
> >> > -
> >> > -	vdsc_cfg->bits_per_pixel = pps1;
> >> > -
> >> > -	if (pps0 & DSC_NATIVE_420_ENABLE)
> >> > -		vdsc_cfg->bits_per_pixel >>= 1;
> >> > -
> >> > -	crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
> >> > +	intel_dsc_get_pps_config(crtc_state);
> >> >  out:
> >> >  	intel_display_power_put(dev_priv, power_domain, wakeref);  } diff
> >> > --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> >> > b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> >> > index 785ede31116e..862dc708c5fc 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> >> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> >> > @@ -78,6 +78,10 @@
> >> >  /* Icelake Display Stream Compression Registers */
> >> >  #define DSCA_PICTURE_PARAMETER_SET_0
> 	_MMIO(0x6B200)
> >> >  #define DSCC_PICTURE_PARAMETER_SET_0
> 	_MMIO(0x6BA00)
> >> > +#define DSCA_PPS_0				0x6B200
> >> > +#define DSCC_PPS_0				0x6BA00
> >> > +#define DSCA_PPS_REG(pps)			_MMIO(DSCA_PPS_0
> >> + (pps) * 4)
> >> > +#define DSCC_PPS_REG(pps)			_MMIO(DSCC_PPS_0
> >> + (pps) * 4)
> >> >  #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB	0x78270
> >> >  #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB	0x78370
> >> >  #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC	0x78470
> >> > @@ -88,6 +92,14 @@
> >> >  #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe)
> >> 	_MMIO_PIPE((pipe) - PIPE_B, \
> >> >
> >> _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
> >> >
> >> _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
> >> > +#define ICL_DSC0_PPS_0(pipe)			_PICK_EVEN((pipe) -
> >> PIPE_B, \
> >> > +
> >> _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
> >> > +
> >> _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
> >> > +#define ICL_DSC1_PPS_0(pipe)			_PICK_EVEN((pipe) -
> >> PIPE_B, \
> >> > +
> >> _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
> >> > +
> >> _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
> >> > +#define  ICL_DSC0_PPS_REG(pipe, pps)
> >> 	_MMIO(ICL_DSC0_PPS_0(pipe) + ((pps) * 4))
> >> > +#define  ICL_DSC1_PPS_REG(pipe, pps)
> >> 	_MMIO(ICL_DSC1_PPS_0(pipe) + ((pps) * 4))
> >> >  #define  DSC_NATIVE_422_ENABLE		BIT(23)
> >> >  #define  DSC_NATIVE_420_ENABLE		BIT(22)
> >> >  #define  DSC_ALT_ICH_SEL		(1 << 20)
> >>
> >> --
> >> Jani Nikula, Intel Open Source Graphics Center
> 
> --
> Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v7 4/8] drm/i915/vdsc: Add function to read any PPS register

[Nautiyal, Ankit K]

On 8/16/2023 3:46 PM, Jani Nikula wrote:
> On Wed, 16 Aug 2023, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
>>> On Tue, 08 Aug 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
>>>> Add function to read any PPS register based on the intel_dsc_pps enum
>>>> provided. Add a function which will call the new pps read function and
>>>> place it in crtc state. Only PPS0 and
>>>> PPS1 are readout the rest of the registers will be read in upcoming
>>>> patches.
>>>>
>>>> --v2
>>>> -Changes in read function as PPS enum is removed -Initialize pps_val
>>>> as 0 in pps_read func itself [Jani] -Create a function that gets the
>>>> required register and call that in the common read function [Jani]
>>>> -Move the drm_WARN_ON one abstraction layer above [Jani]
>>>>
>>>> --v3
>>>> -Send both reg values regardless of dsc engine no [Jani] -Don't use
>>>> num_vdsc_instances stick to dsc_split field [Ankit]
>>>>
>>>> --v4
>>>> -Manipulate the reg values instead of creating MACRO to change name of
>>>> pps [Ankit]
>>>>
>>>> --v5
>>>> -Read dsc reg values using array rather than individual variables
>>>> [Ankit] -Loop the verification of all dsc engine reads to future proof
>>>> it [Ankit] -Keep the fix me comment in this patch and remove it in
>>>> later one where we add other readouts [Ankit] -Add switch statement
>>>> that fills in the required registers based on no of vdsc engines per
>>>> pipe.
>>>>
>>>> --v7
>>>> -Pass no of vdsc instances from read_reg function [Ankit] -Fix issue
>>>> where arrays do not get freed on return for read_and_verify func
>>>> [Ankit]
>>>>
>>>> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
>>>> ---
>>>>   drivers/gpu/drm/i915/display/intel_vdsc.c     | 129 +++++++++++++-----
>>>>   .../gpu/drm/i915/display/intel_vdsc_regs.h    |  12 ++
>>>>   2 files changed, 105 insertions(+), 36 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
>>>> b/drivers/gpu/drm/i915/display/intel_vdsc.c
>>>> index dc86514d9e17..aa93228ca7af 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>>>> @@ -365,6 +365,28 @@ int intel_dsc_get_num_vdsc_instances(const
>>> struct intel_crtc_state *crtc_state)
>>>>   	return num_vdsc_instances;
>>>>   }
>>>>
>>>> +static void intel_dsc_get_pps_reg(const struct intel_crtc_state
>>> *crtc_state, int pps,
>>>> +				  i915_reg_t *dsc_reg, int no_vdsc_per_pipe)
>>> {
>>>> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>>>> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>>>> +	enum pipe pipe = crtc->pipe;
>>>> +	bool pipe_dsc;
>>> Matter of taste, but to me that's four local variables too many for small things
>>> like this.
>>>
>>>> +
>>>> +	pipe_dsc = is_pipe_dsc(crtc, cpu_transcoder);
>>>> +
>>>> +	switch (no_vdsc_per_pipe) {

Forgot to mention earlier, perhaps vdsc_per_pipe?


>>>> +	case 2:
>>>> +		dsc_reg[1] = pipe_dsc ? ICL_DSC1_PPS_REG(pipe, pps) :
>>> DSCC_PPS_REG(pps);
>>>> +		fallthrough;
>>>> +	case 1:
>>>> +		dsc_reg[0] = pipe_dsc ? ICL_DSC0_PPS_REG(pipe, pps) :
>>> DSCA_PPS_REG(pps);
>>>> +		break;
>>>> +	default:
>>>> +		MISSING_CASE(no_vdsc_per_pipe);
>>>> +	}
>>>> +}
>>>> +
>>>>   static void intel_dsc_pps_configure(const struct intel_crtc_state
>>>> *crtc_state)  {
>>>>   	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>>>> @@ -994,17 +1016,83 @@ void intel_dsc_disable(const struct
>>> intel_crtc_state *old_crtc_state)
>>>>   	}
>>>>   }
>>>>
>>>> +static int intel_dsc_read_pps_reg(struct intel_crtc_state *crtc_state,
>>>> +				  int pps, u32 *pps_val)
>>>> +{
>>>> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>>>> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>>>> +	const int no_vdsc_per_pipe =
>>> intel_dsc_get_vdsc_per_pipe(crtc_state);
>>>> +	i915_reg_t *dsc_reg;
>>>> +	u32 *pps_temp;
>>>> +	int i, ret = 0;
>>>> +
>>>> +	dsc_reg = kcalloc(no_vdsc_per_pipe, sizeof(dsc_reg), GFP_KERNEL);
>>>> +	if (!dsc_reg)
>>>> +		return -ENOMEM;
>>>> +
>>>> +	pps_temp = kcalloc(no_vdsc_per_pipe, sizeof(pps_temp),
>>> GFP_KERNEL);
>>>> +	if (!pps_temp) {
>>>> +		kfree(dsc_reg);
>>>> +		return -ENOMEM;
>>>> +	}
>>> no_vdsc_per_pipe is at most 2. Temporary dynamic allocation is way overkill
>>> here.
>> Yes but Ankit was of the thought that we can future proof this going forward if by any chance we get more dsc engines
> Keep it simple. There's going to have to be quite a few engines per pipe
> before this needs to be dynamically allocated. This is also future
> proof, and we'll only need to update one value to expand to more.


I agree. I just wanted to avoid, 2 dsc_regs, (dsc_reg1, and dsc_reg2) 
sent as an argument, and have an array instead.


Regards,

Ankit

>
> 	i915_reg_t dsc_reg[2];
>
> 	drm_WARN_ON_ONCE(&i915->drm, ARRAY_SIZE(dsc_reg) < intel_dsc_get_vdsc_per_pipe(crtc_state));
>
> 	intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, ARRAY_SIZE(dsc_reg));
>
> 	for (i = 0; i < min(ARRAY_SIZE(dsc_reg), intel_dsc_get_vdsc_per_pipe(crtc_state)); i++) {
>          	u32 val;
>
> 	        val = intel_de_read(i915, dsc_reg[i])
>
>                  if (i == 0)
>                  	*pps_val = val;
>                  else if (val != *pps_val)
>                  	return -EINVAL;
> 	}
>
> 	return 0;
>
> Adjust intel_dsc_get_pps_reg() accordingly to respect size of the
> dsc_reg destination:
>
> static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int pps,
> 				  i915_reg_t *dsc_reg, int dsc_reg_size)
>
>>>> +
>>>> +	*pps_val = 0;
>>>> +	intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, no_vdsc_per_pipe);
>>>> +	*pps_val = intel_de_read(i915, dsc_reg[0]);
>>>> +	if (no_vdsc_per_pipe > 1) {
>>>> +		for (i = 0; i < no_vdsc_per_pipe - 1; i++) {
>>>> +			pps_temp[i] = intel_de_read(i915, dsc_reg[i]);
>>>> +			pps_temp[i + 1] = intel_de_read(i915, dsc_reg[i + 1]);
>>>> +			if (pps_temp[i] != pps_temp[i + 1]) {
>>>> +				ret = 1;
> Please don't use random magic numbers for return codes.
>
>>>> +				break;
>>>> +			}
>>>> +		}
>>>> +	}
>>> What is going on here? Feels like this has grown way more complicated than
>>> it needs to be since I last looked at this series. :(
>> In case of more than 2 vdsc engines (just for future proofing) this loops looks at all the registers being used for
>> that pipe and makes sure everyone has the same value
> Right. But for that you only need to store one value to compare, not all
> of them.
>
> Always try to find the simple solution!
>
>
> BR,
> Jani.
>
>> Regards,
>> Suraj Kandpal
>>>> +
>>>> +	kfree(dsc_reg);
>>>> +	kfree(pps_temp);
>>>> +	return ret;
>>>> +}
>>>> +
>>>> +static void intel_dsc_read_and_verify_pps_reg(struct intel_crtc_state
>>> *crtc_state,
>>>> +					      int pps, u32 *pps_val)
>>>> +{
>>>> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>>>> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>>>> +	int ret;
>>>> +
>>>> +	ret = intel_dsc_read_pps_reg(crtc_state, pps, pps_val);
>>>> +	drm_WARN_ON(&i915->drm, ret);
>>>> +}
>>>> +
>>>> +static void intel_dsc_get_pps_config(struct intel_crtc_state
>>>> +*crtc_state) {
>>>> +	struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
>>>> +	u32 pps_temp1, pps_temp2;
>>>> +
>>>> +	/* FIXME: add more state readout as needed */
>>>> +
>>>> +	/* Readout PPS_0 and PPS_1 registers */
>>>> +	intel_dsc_read_and_verify_pps_reg(crtc_state, 0, &pps_temp1);
>>>> +	intel_dsc_read_and_verify_pps_reg(crtc_state, 1, &pps_temp2);
>>>> +
>>>> +	vdsc_cfg->bits_per_pixel = pps_temp2;
>>>> +
>>>> +	if (pps_temp1 & DSC_NATIVE_420_ENABLE)
>>>> +		vdsc_cfg->bits_per_pixel >>= 1;
>>>> +
>>>> +	crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4; }
>>>> +
>>>>   void intel_dsc_get_config(struct intel_crtc_state *crtc_state)  {
>>>>   	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>>>>   	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>>>> -	struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
>>>>   	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>>>> -	enum pipe pipe = crtc->pipe;
>>>>   	enum intel_display_power_domain power_domain;
>>>>   	intel_wakeref_t wakeref;
>>>> -	u32 dss_ctl1, dss_ctl2, pps0 = 0, pps1 = 0, pps_temp0, pps_temp1;
>>>> -	int no_vdsc_instances_per_pipe;
>>>> +	u32 dss_ctl1, dss_ctl2;
>>>>
>>>>   	if (!intel_dsc_source_support(crtc_state))
>>>>   		return;
>>>> @@ -1025,38 +1113,7 @@ void intel_dsc_get_config(struct intel_crtc_state
>>> *crtc_state)
>>>>   	crtc_state->dsc.dsc_split = (dss_ctl2 &
>>> RIGHT_BRANCH_VDSC_ENABLE) &&
>>>>   		(dss_ctl1 & JOINER_ENABLE);
>>>>
>>>> -	/* FIXME: add more state readout as needed */
>>>> -
>>>> -	no_vdsc_instances_per_pipe =
>>> intel_dsc_get_vdsc_per_pipe(crtc_state);
>>>> -
>>>> -	/* PPS0 & PPS1 */
>>>> -	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
>>>> -		pps1 = intel_de_read(dev_priv,
>>> DSCA_PICTURE_PARAMETER_SET_1);
>>>> -		if (no_vdsc_instances_per_pipe > 1) {
>>>> -			pps_temp1 = intel_de_read(dev_priv,
>>> DSCC_PICTURE_PARAMETER_SET_1);
>>>> -			drm_WARN_ON(&dev_priv->drm, pps1 !=
>>> pps_temp1);
>>>> -		}
>>>> -	} else {
>>>> -		pps0 = intel_de_read(dev_priv,
>>>> -
>>> ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe));
>>>> -		pps1 = intel_de_read(dev_priv,
>>>> -
>>> ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
>>>> -		if (no_vdsc_instances_per_pipe > 1) {
>>>> -			pps_temp0 = intel_de_read(dev_priv,
>>>> -
>>> ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe));
>>>> -			pps_temp1 = intel_de_read(dev_priv,
>>>> -
>>> ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe));
>>>> -			drm_WARN_ON(&dev_priv->drm, pps0 !=
>>> pps_temp0);
>>>> -			drm_WARN_ON(&dev_priv->drm, pps1 !=
>>> pps_temp1);
>>>> -		}
>>>> -	}
>>>> -
>>>> -	vdsc_cfg->bits_per_pixel = pps1;
>>>> -
>>>> -	if (pps0 & DSC_NATIVE_420_ENABLE)
>>>> -		vdsc_cfg->bits_per_pixel >>= 1;
>>>> -
>>>> -	crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
>>>> +	intel_dsc_get_pps_config(crtc_state);
>>>>   out:
>>>>   	intel_display_power_put(dev_priv, power_domain, wakeref);  } diff
>>>> --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
>>>> b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
>>>> index 785ede31116e..862dc708c5fc 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
>>>> +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
>>>> @@ -78,6 +78,10 @@
>>>>   /* Icelake Display Stream Compression Registers */
>>>>   #define DSCA_PICTURE_PARAMETER_SET_0		_MMIO(0x6B200)
>>>>   #define DSCC_PICTURE_PARAMETER_SET_0		_MMIO(0x6BA00)
>>>> +#define DSCA_PPS_0				0x6B200
>>>> +#define DSCC_PPS_0				0x6BA00
>>>> +#define DSCA_PPS_REG(pps)			_MMIO(DSCA_PPS_0
>>> + (pps) * 4)
>>>> +#define DSCC_PPS_REG(pps)			_MMIO(DSCC_PPS_0
>>> + (pps) * 4)
>>>>   #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB	0x78270
>>>>   #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB	0x78370
>>>>   #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC	0x78470
>>>> @@ -88,6 +92,14 @@
>>>>   #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe)
>>> 	_MMIO_PIPE((pipe) - PIPE_B, \
>>> _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
>>> _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
>>>> +#define ICL_DSC0_PPS_0(pipe)			_PICK_EVEN((pipe) -
>>> PIPE_B, \
>>>> +
>>> _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
>>>> +
>>> _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
>>>> +#define ICL_DSC1_PPS_0(pipe)			_PICK_EVEN((pipe) -
>>> PIPE_B, \
>>>> +
>>> _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
>>>> +
>>> _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
>>>> +#define  ICL_DSC0_PPS_REG(pipe, pps)
>>> 	_MMIO(ICL_DSC0_PPS_0(pipe) + ((pps) * 4))
>>>> +#define  ICL_DSC1_PPS_REG(pipe, pps)
>>> 	_MMIO(ICL_DSC1_PPS_0(pipe) + ((pps) * 4))
>>>>   #define  DSC_NATIVE_422_ENABLE		BIT(23)
>>>>   #define  DSC_NATIVE_420_ENABLE		BIT(22)
>>>>   #define  DSC_ALT_ICH_SEL		(1 << 20)
>>> --
>>> Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH v7 5/8] drm/i915/vdsc: Add function to write in PPS register

[Suraj Kandpal]

Now that we have a function that reads any PPS register based
on intel_dsc_pps enum provided lets create a function that can
write on any PPS.

--v2
-Changes need as PPS enum was dropped
-Remove duplicated code in intel_dsc_write_pps_reg [Jani]

--v3
-Use dsc_split instead of num_vdsc_instances [Ankit]

--v5
-Changes to implement the new dsc_reg array variable passing
[Ankit]

--v7
-Pass no of vdsc instances to get_pps_reg [Ankit]

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vdsc.c | 306 +++++-----------------
 1 file changed, 64 insertions(+), 242 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index aa93228ca7af..22bb22678fee 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -387,6 +387,27 @@ static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int
 	}
 }
 
+static int intel_dsc_write_pps_reg(const struct intel_crtc_state *crtc_state,
+				   int pps, u32 pps_val)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+	i915_reg_t *dsc_reg;
+	int i, no_vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
+
+	dsc_reg = kcalloc(no_vdsc_per_pipe, sizeof(dsc_reg), GFP_KERNEL);
+	if (!dsc_reg)
+		return -ENOMEM;
+
+	intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, no_vdsc_per_pipe);
+
+	for (i = 0; i < no_vdsc_per_pipe; i++)
+		intel_de_write(i915, dsc_reg[i], pps_val);
+
+	kfree(dsc_reg);
+	return 0;
+}
+
 static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -400,6 +421,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 	int i = 0;
 	int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
 	int no_vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
+	int ret;
 
 	/* Populate PICTURE_PARAMETER_SET_0 registers */
 	pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
@@ -422,149 +444,53 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 	if (vdsc_cfg->vbr_enable)
 		pps_val |= DSC_VBR_ENABLE;
 	drm_dbg_kms(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val);
-	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
-		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_0,
-			       pps_val);
-		/*
-		 * If 2 VDSC instances are needed, configure PPS for second
-		 * VDSC
-		 */
-		if (no_vdsc_instances_per_pipe > 1)
-			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_0,
-				       pps_val);
-	} else {
-		intel_de_write(dev_priv,
-			       ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe),
-			       pps_val);
-		if (no_vdsc_instances_per_pipe > 1)
-			intel_de_write(dev_priv,
-				       ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe),
-				       pps_val);
-	}
+	ret = intel_dsc_write_pps_reg(crtc_state, 0, pps_val);
+	if (ret)
+		drm_dbg_kms(&dev_priv->drm, "PPS0 not written err:%d\n", ret);
 
 	/* Populate PICTURE_PARAMETER_SET_1 registers */
 	pps_val = 0;
 	pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);
 	drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val);
-	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
-		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_1,
-			       pps_val);
-		/*
-		 * If 2 VDSC instances are needed, configure PPS for second
-		 * VDSC
-		 */
-		if (no_vdsc_instances_per_pipe > 1)
-			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_1,
-				       pps_val);
-	} else {
-		intel_de_write(dev_priv,
-			       ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe),
-			       pps_val);
-		if (no_vdsc_instances_per_pipe > 1)
-			intel_de_write(dev_priv,
-				       ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe),
-				       pps_val);
-	}
+	ret = intel_dsc_write_pps_reg(crtc_state, 1, pps_val);
+	if (ret)
+		drm_dbg_kms(&dev_priv->drm, "PPS1 not written err:%d\n", ret);
 
 	/* Populate PICTURE_PARAMETER_SET_2 registers */
 	pps_val = 0;
 	pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
 		DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
 	drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val);
-	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
-		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_2,
-			       pps_val);
-		/*
-		 * If 2 VDSC instances are needed, configure PPS for second
-		 * VDSC
-		 */
-		if (no_vdsc_instances_per_pipe > 1)
-			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_2,
-				       pps_val);
-	} else {
-		intel_de_write(dev_priv,
-			       ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe),
-			       pps_val);
-		if (no_vdsc_instances_per_pipe > 1)
-			intel_de_write(dev_priv,
-				       ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe),
-				       pps_val);
-	}
+	ret = intel_dsc_write_pps_reg(crtc_state, 2, pps_val);
+	if (ret)
+		drm_dbg_kms(&dev_priv->drm, "PPS2 not written err:%d\n", ret);
 
 	/* Populate PICTURE_PARAMETER_SET_3 registers */
 	pps_val = 0;
 	pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
 		DSC_SLICE_WIDTH(vdsc_cfg->slice_width);
 	drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val);
-	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
-		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_3,
-			       pps_val);
-		/*
-		 * If 2 VDSC instances are needed, configure PPS for second
-		 * VDSC
-		 */
-		if (no_vdsc_instances_per_pipe > 1)
-			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_3,
-				       pps_val);
-	} else {
-		intel_de_write(dev_priv,
-			       ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe),
-			       pps_val);
-		if (no_vdsc_instances_per_pipe > 1)
-			intel_de_write(dev_priv,
-				       ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe),
-				       pps_val);
-	}
+	intel_dsc_write_pps_reg(crtc_state, 3, pps_val);
+	if (ret)
+		drm_dbg_kms(&dev_priv->drm, "PPS3 not written err:%d\n", ret);
 
 	/* Populate PICTURE_PARAMETER_SET_4 registers */
 	pps_val = 0;
 	pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
 		DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
 	drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val);
-	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
-		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_4,
-			       pps_val);
-		/*
-		 * If 2 VDSC instances are needed, configure PPS for second
-		 * VDSC
-		 */
-		if (no_vdsc_instances_per_pipe > 1)
-			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_4,
-				       pps_val);
-	} else {
-		intel_de_write(dev_priv,
-			       ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe),
-			       pps_val);
-		if (no_vdsc_instances_per_pipe > 1)
-			intel_de_write(dev_priv,
-				       ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe),
-				       pps_val);
-	}
+	ret = intel_dsc_write_pps_reg(crtc_state, 4, pps_val);
+	if (ret)
+		drm_dbg_kms(&dev_priv->drm, "PPS4 not written err:%d\n", ret);
 
 	/* Populate PICTURE_PARAMETER_SET_5 registers */
 	pps_val = 0;
 	pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
 		DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
 	drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val);
-	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
-		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_5,
-			       pps_val);
-		/*
-		 * If 2 VDSC instances are needed, configure PPS for second
-		 * VDSC
-		 */
-		if (no_vdsc_instances_per_pipe > 1)
-			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_5,
-				       pps_val);
-	} else {
-		intel_de_write(dev_priv,
-			       ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe),
-			       pps_val);
-		if (no_vdsc_instances_per_pipe > 1)
-			intel_de_write(dev_priv,
-				       ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe),
-				       pps_val);
-	}
+	ret = intel_dsc_write_pps_reg(crtc_state, 5, pps_val);
+	if (ret)
+		drm_dbg_kms(&dev_priv->drm, "PPS5 not written err:%d\n", ret);
 
 	/* Populate PICTURE_PARAMETER_SET_6 registers */
 	pps_val = 0;
@@ -573,100 +499,36 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 		DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
 		DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
 	drm_dbg_kms(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val);
-	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
-		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_6,
-			       pps_val);
-		/*
-		 * If 2 VDSC instances are needed, configure PPS for second
-		 * VDSC
-		 */
-		if (no_vdsc_instances_per_pipe > 1)
-			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_6,
-				       pps_val);
-	} else {
-		intel_de_write(dev_priv,
-			       ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe),
-			       pps_val);
-		if (no_vdsc_instances_per_pipe > 1)
-			intel_de_write(dev_priv,
-				       ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe),
-				       pps_val);
-	}
+	ret = intel_dsc_write_pps_reg(crtc_state, 6, pps_val);
+	if (ret)
+		drm_dbg_kms(&dev_priv->drm, "PPS6 not written err:%d\n", ret);
 
 	/* Populate PICTURE_PARAMETER_SET_7 registers */
 	pps_val = 0;
 	pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
 		DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
 	drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val);
-	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
-		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_7,
-			       pps_val);
-		/*
-		 * If 2 VDSC instances are needed, configure PPS for second
-		 * VDSC
-		 */
-		if (no_vdsc_instances_per_pipe > 1)
-			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_7,
-				       pps_val);
-	} else {
-		intel_de_write(dev_priv,
-			       ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe),
-			       pps_val);
-		if (no_vdsc_instances_per_pipe > 1)
-			intel_de_write(dev_priv,
-				       ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe),
-				       pps_val);
-	}
+	ret = intel_dsc_write_pps_reg(crtc_state, 7, pps_val);
+	if (ret)
+		drm_dbg_kms(&dev_priv->drm, "PPS7 not written err:%d\n", ret);
 
 	/* Populate PICTURE_PARAMETER_SET_8 registers */
 	pps_val = 0;
 	pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |
 		DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);
 	drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val);
-	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
-		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_8,
-			       pps_val);
-		/*
-		 * If 2 VDSC instances are needed, configure PPS for second
-		 * VDSC
-		 */
-		if (no_vdsc_instances_per_pipe > 1)
-			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_8,
-				       pps_val);
-	} else {
-		intel_de_write(dev_priv,
-			       ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe),
-			       pps_val);
-		if (no_vdsc_instances_per_pipe > 1)
-			intel_de_write(dev_priv,
-				       ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe),
-				       pps_val);
-	}
+	ret = intel_dsc_write_pps_reg(crtc_state, 8, pps_val);
+	if (ret)
+		drm_dbg_kms(&dev_priv->drm, "PPS8 not written err:%d\n", ret);
 
 	/* Populate PICTURE_PARAMETER_SET_9 registers */
 	pps_val = 0;
 	pps_val |= DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |
 		DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
 	drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val);
-	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
-		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_9,
-			       pps_val);
-		/*
-		 * If 2 VDSC instances are needed, configure PPS for second
-		 * VDSC
-		 */
-		if (no_vdsc_instances_per_pipe > 1)
-			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_9,
-				       pps_val);
-	} else {
-		intel_de_write(dev_priv,
-			       ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe),
-			       pps_val);
-		if (no_vdsc_instances_per_pipe > 1)
-			intel_de_write(dev_priv,
-				       ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe),
-				       pps_val);
-	}
+	ret = intel_dsc_write_pps_reg(crtc_state, 9, pps_val);
+	if (ret)
+		drm_dbg_kms(&dev_priv->drm, "PPS9 not written err:%d\n", ret);
 
 	/* Populate PICTURE_PARAMETER_SET_10 registers */
 	pps_val = 0;
@@ -675,25 +537,9 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 		DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |
 		DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
 	drm_dbg_kms(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val);
-	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
-		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_10,
-			       pps_val);
-		/*
-		 * If 2 VDSC instances are needed, configure PPS for second
-		 * VDSC
-		 */
-		if (no_vdsc_instances_per_pipe > 1)
-			intel_de_write(dev_priv,
-				       DSCC_PICTURE_PARAMETER_SET_10, pps_val);
-	} else {
-		intel_de_write(dev_priv,
-			       ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe),
-			       pps_val);
-		if (no_vdsc_instances_per_pipe > 1)
-			intel_de_write(dev_priv,
-				       ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe),
-				       pps_val);
-	}
+	ret = intel_dsc_write_pps_reg(crtc_state, 10, pps_val);
+	if (ret)
+		drm_dbg_kms(&dev_priv->drm, "PPS10 not written err:%d\n", ret);
 
 	/* Populate Picture parameter set 16 */
 	pps_val = 0;
@@ -703,51 +549,27 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 		DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
 					vdsc_cfg->slice_height);
 	drm_dbg_kms(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val);
-	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
-		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_16,
-			       pps_val);
-		/*
-		 * If 2 VDSC instances are needed, configure PPS for second
-		 * VDSC
-		 */
-		if (no_vdsc_instances_per_pipe > 1)
-			intel_de_write(dev_priv,
-				       DSCC_PICTURE_PARAMETER_SET_16, pps_val);
-	} else {
-		intel_de_write(dev_priv,
-			       ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe),
-			       pps_val);
-		if (no_vdsc_instances_per_pipe > 1)
-			intel_de_write(dev_priv,
-				       ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe),
-				       pps_val);
-	}
+	ret = intel_dsc_write_pps_reg(crtc_state, 16, pps_val);
+	if (ret)
+		drm_dbg_kms(&dev_priv->drm, "PPS16 not written err:%d\n", ret);
 
 	if (DISPLAY_VER(dev_priv) >= 14) {
 		/* Populate PICTURE_PARAMETER_SET_17 registers */
 		pps_val = 0;
 		pps_val |= DSC_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset);
 		drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val);
-		intel_de_write(dev_priv,
-			       MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe),
-			       pps_val);
-		if (no_vdsc_instances_per_pipe > 1)
-			intel_de_write(dev_priv,
-				       MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe),
-				       pps_val);
+		ret = intel_dsc_write_pps_reg(crtc_state, 17, pps_val);
+		if (ret)
+			drm_dbg_kms(&dev_priv->drm, "PPS17 not written err:%d\n", ret);
 
 		/* Populate PICTURE_PARAMETER_SET_18 registers */
 		pps_val = 0;
 		pps_val |= DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) |
 			   DSC_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj);
 		drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val);
-		intel_de_write(dev_priv,
-			       MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe),
-			       pps_val);
-		if (no_vdsc_instances_per_pipe > 1)
-			intel_de_write(dev_priv,
-				       MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe),
-				       pps_val);
+		ret = intel_dsc_write_pps_reg(crtc_state, 18, pps_val);
+		if (ret)
+			drm_dbg_kms(&dev_priv->drm, "PPS18 not written err:%d\n", ret);
 	}
 
 	/* Populate the RC_BUF_THRESH registers */
-- 
2.25.1

[Intel-gfx] [PATCH v7 6/8] drm/i915/vdsc: Remove unused dsc registers

[Suraj Kandpal]

Now that we have macros that can fetch dsc register values based
on pipe and pps parameters we can go ahead and remove all the
unused register.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 .../gpu/drm/i915/display/intel_vdsc_regs.h    | 259 ++----------------
 1 file changed, 24 insertions(+), 235 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
index 862dc708c5fc..7afc487223fb 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
@@ -46,38 +46,7 @@
 							   _ICL_PIPE_DSS_CTL2_PB, \
 							   _ICL_PIPE_DSS_CTL2_PC)
 
-/* MTL Display Stream Compression registers */
-#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB	0x782B4
-#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB	0x783B4
-#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC	0x784B4
-#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC	0x785B4
-#define MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							   _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB, \
-							   _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC)
-#define MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							   _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB, \
-							   _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC)
-#define DSC_SL_BPG_OFFSET_MASK			REG_GENMASK(31, 27)
-#define DSC_SL_BPG_OFFSET(offset)		REG_FIELD_PREP(DSC_SL_BPG_OFFSET_MASK, offset)
-
-#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB	0x782B8
-#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB	0x783B8
-#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC	0x784B8
-#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC	0x785B8
-#define MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							   _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB, \
-							   _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC)
-#define MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							   _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB, \
-							   _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC)
-#define DSC_NSL_BPG_OFFSET_MASK			REG_GENMASK(31, 16)
-#define DSC_SL_OFFSET_ADJ_MASK			REG_GENMASK(15, 0)
-#define DSC_NSL_BPG_OFFSET(offset)		REG_FIELD_PREP(DSC_NSL_BPG_OFFSET_MASK, offset)
-#define DSC_SL_OFFSET_ADJ(offset)		REG_FIELD_PREP(DSC_SL_OFFSET_ADJ_MASK, offset)
-
 /* Icelake Display Stream Compression Registers */
-#define DSCA_PICTURE_PARAMETER_SET_0		_MMIO(0x6B200)
-#define DSCC_PICTURE_PARAMETER_SET_0		_MMIO(0x6BA00)
 #define DSCA_PPS_0				0x6B200
 #define DSCC_PPS_0				0x6BA00
 #define DSCA_PPS_REG(pps)			_MMIO(DSCA_PPS_0 + (pps) * 4)
@@ -86,12 +55,6 @@
 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB	0x78370
 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC	0x78470
 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC	0x78570
-#define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							   _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
-							   _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
-#define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							   _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
-							   _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
 #define ICL_DSC0_PPS_0(pipe)			_PICK_EVEN((pipe) - PIPE_B, \
 							   _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
 							   _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
@@ -100,6 +63,8 @@
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
 #define  ICL_DSC0_PPS_REG(pipe, pps)		_MMIO(ICL_DSC0_PPS_0(pipe) + ((pps) * 4))
 #define  ICL_DSC1_PPS_REG(pipe, pps)		_MMIO(ICL_DSC1_PPS_0(pipe) + ((pps) * 4))
+
+/* PPS0 */
 #define  DSC_NATIVE_422_ENABLE		BIT(23)
 #define  DSC_NATIVE_420_ENABLE		BIT(22)
 #define  DSC_ALT_ICH_SEL		(1 << 20)
@@ -112,66 +77,22 @@
 #define  DSC_VER_MIN_SHIFT		4
 #define  DSC_VER_MAJ			(0x1 << 0)
 
-#define DSCA_PICTURE_PARAMETER_SET_1		_MMIO(0x6B204)
-#define DSCC_PICTURE_PARAMETER_SET_1		_MMIO(0x6BA04)
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB	0x78274
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB	0x78374
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC	0x78474
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC	0x78574
-#define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							   _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \
-							   _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC)
-#define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							   _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \
-							   _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC)
+/* PPS1 */
 #define  DSC_BPP(bpp)				((bpp) << 0)
 
-#define DSCA_PICTURE_PARAMETER_SET_2		_MMIO(0x6B208)
-#define DSCC_PICTURE_PARAMETER_SET_2		_MMIO(0x6BA08)
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB	0x78278
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB	0x78378
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC	0x78478
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC	0x78578
-#define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							   _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \
-							   _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC)
-#define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-					    _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \
-					    _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC)
+/* PPS2 */
 #define  DSC_PIC_WIDTH_MASK		REG_GENMASK(31, 16)
 #define  DSC_PIC_HEIGHT_MASK		REG_GENMASK(15, 0)
 #define  DSC_PIC_WIDTH(pic_width)	REG_FIELD_PREP(DSC_PIC_WIDTH_MASK, pic_width)
 #define  DSC_PIC_HEIGHT(pic_height)	REG_FIELD_PREP(DSC_PIC_HEIGHT_MASK, pic_height)
 
-#define DSCA_PICTURE_PARAMETER_SET_3		_MMIO(0x6B20C)
-#define DSCC_PICTURE_PARAMETER_SET_3		_MMIO(0x6BA0C)
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB	0x7827C
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB	0x7837C
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC	0x7847C
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC	0x7857C
-#define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							   _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \
-							   _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC)
-#define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							   _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \
-							   _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC)
+/* PPS3 */
 #define  DSC_SLICE_WIDTH_MASK			REG_GENMASK(31, 16)
 #define  DSC_SLICE_HEIGHT_MASK			REG_GENMASK(15, 0)
 #define  DSC_SLICE_WIDTH(slice_width)		REG_FIELD_PREP(DSC_SLICE_WIDTH_MASK, slice_width)
 #define  DSC_SLICE_HEIGHT(slice_height)		REG_FIELD_PREP(DSC_SLICE_HEIGHT_MASK, slice_height)
 
-#define DSCA_PICTURE_PARAMETER_SET_4		_MMIO(0x6B210)
-#define DSCC_PICTURE_PARAMETER_SET_4		_MMIO(0x6BA10)
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB	0x78280
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB	0x78380
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC	0x78480
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC	0x78580
-#define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							   _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
-							   _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC)
-#define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							   _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \
-							   _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)
+/* PPS4 */
 #define  DSC_INITIAL_DEC_DELAY_MASK		REG_GENMASK(31, 16)
 #define  DSC_INITIAL_XMIT_DELAY_MASK		REG_GENMASK(9, 0)
 #define  DSC_INITIAL_DEC_DELAY(dec_delay)       REG_FIELD_PREP(DSC_INITIAL_DEC_DELAY_MASK, \
@@ -179,35 +100,13 @@
 #define  DSC_INITIAL_XMIT_DELAY(xmit_delay)     REG_FIELD_PREP(DSC_INITIAL_XMIT_DELAY_MASK, \
 							       xmit_delay)
 
-#define DSCA_PICTURE_PARAMETER_SET_5		_MMIO(0x6B214)
-#define DSCC_PICTURE_PARAMETER_SET_5		_MMIO(0x6BA14)
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB	0x78284
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB	0x78384
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC	0x78484
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC	0x78584
-#define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							   _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \
-							   _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC)
-#define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							   _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \
-							   _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
+/* PPS5 */
 #define  DSC_SCALE_DEC_INT_MASK			REG_GENMASK(27, 16)
 #define  DSC_SCALE_INC_INT_MASK			REG_GENMASK(15, 0)
 #define  DSC_SCALE_DEC_INT(scale_dec)		REG_FIELD_PREP(DSC_SCALE_DEC_INT_MASK, scale_dec)
 #define  DSC_SCALE_INC_INT(scale_inc)		REG_FIELD_PREP(DSC_SCALE_INC_INT_MASK, scale_inc)
 
-#define DSCA_PICTURE_PARAMETER_SET_6		_MMIO(0x6B218)
-#define DSCC_PICTURE_PARAMETER_SET_6		_MMIO(0x6BA18)
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB	0x78288
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB	0x78388
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC	0x78488
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC	0x78588
-#define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							   _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \
-							   _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC)
-#define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							   _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \
-							   _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC)
+/* PPS6 */
 #define  DSC_FLATNESS_MAX_QP_MASK		REG_GENMASK(28, 24)
 #define  DSC_FLATNESS_MIN_QP_MASK		REG_GENMASK(20, 16)
 #define  DSC_FIRST_LINE_BPG_OFFSET_MASK		REG_GENMASK(12, 8)
@@ -219,36 +118,13 @@
 #define  DSC_INITIAL_SCALE_VALUE(value)		REG_FIELD_PREP(DSC_INITIAL_SCALE_VALUE_MASK, \
 							       value)
 
-#define DSCA_PICTURE_PARAMETER_SET_7		_MMIO(0x6B21C)
-#define DSCC_PICTURE_PARAMETER_SET_7		_MMIO(0x6BA1C)
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB	0x7828C
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB	0x7838C
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC	0x7848C
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC	0x7858C
-#define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							    _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \
-							    _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC)
-#define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							    _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \
-							    _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC)
+/* PPS7 */
 #define  DSC_NFL_BPG_OFFSET_MASK		REG_GENMASK(31, 16)
 #define  DSC_SLICE_BPG_OFFSET_MASK		REG_GENMASK(15, 0)
 #define  DSC_NFL_BPG_OFFSET(bpg_offset)		REG_FIELD_PREP(DSC_NFL_BPG_OFFSET_MASK, bpg_offset)
 #define  DSC_SLICE_BPG_OFFSET(bpg_offset)	REG_FIELD_PREP(DSC_SLICE_BPG_OFFSET_MASK, \
 							       bpg_offset)
-
-#define DSCA_PICTURE_PARAMETER_SET_8		_MMIO(0x6B220)
-#define DSCC_PICTURE_PARAMETER_SET_8		_MMIO(0x6BA20)
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB	0x78290
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB	0x78390
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC	0x78490
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC	0x78590
-#define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							   _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \
-							   _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC)
-#define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							   _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \
-							   _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC)
+/* PPS8 */
 #define  DSC_INITIAL_OFFSET_MASK		REG_GENMASK(31, 16)
 #define  DSC_FINAL_OFFSET_MASK			REG_GENMASK(15, 0)
 #define  DSC_INITIAL_OFFSET(initial_offset)	REG_FIELD_PREP(DSC_INITIAL_OFFSET_MASK, \
@@ -256,18 +132,7 @@
 #define  DSC_FINAL_OFFSET(final_offset)		REG_FIELD_PREP(DSC_FINAL_OFFSET_MASK, \
 							       final_offset)
 
-#define DSCA_PICTURE_PARAMETER_SET_9		_MMIO(0x6B224)
-#define DSCC_PICTURE_PARAMETER_SET_9		_MMIO(0x6BA24)
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB	0x78294
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB	0x78394
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC	0x78494
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC	0x78594
-#define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							   _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \
-							   _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC)
-#define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							   _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \
-							   _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC)
+/* PPS9 */
 #define  DSC_RC_EDGE_FACTOR_MASK		REG_GENMASK(19, 16)
 #define  DSC_RC_MODEL_SIZE_MASK			REG_GENMASK(15, 0)
 #define  DSC_RC_EDGE_FACTOR(rc_edge_fact)	REG_FIELD_PREP(DSC_RC_EDGE_FACTOR_MASK, \
@@ -275,18 +140,7 @@
 #define  DSC_RC_MODEL_SIZE(rc_model_size)	REG_FIELD_PREP(DSC_RC_MODEL_SIZE_MASK, \
 							       rc_model_size)
 
-#define DSCA_PICTURE_PARAMETER_SET_10		_MMIO(0x6B228)
-#define DSCC_PICTURE_PARAMETER_SET_10		_MMIO(0x6BA28)
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB	0x78298
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB	0x78398
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC	0x78498
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC	0x78598
-#define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							   _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \
-							   _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC)
-#define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							   _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \
-							   _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC)
+/* PPS10 */
 #define  DSC_RC_TGT_OFF_LOW_MASK			REG_GENMASK(23, 20)
 #define  DSC_RC_TGT_OFF_HIGH_MASK			REG_GENMASK(19, 16)
 #define  DSC_RC_QUANT_INC_LIMIT1_MASK			REG_GENMASK(12, 8)
@@ -298,83 +152,7 @@
 #define  DSC_RC_QUANT_INC_LIMIT1(lim)		REG_FIELD_PREP(DSC_RC_QUANT_INC_LIMIT1_MASK, lim)
 #define  DSC_RC_QUANT_INC_LIMIT0(lim)		REG_FIELD_PREP(DSC_RC_QUANT_INC_LIMIT0_MASK, lim)
 
-#define DSCA_PICTURE_PARAMETER_SET_11		_MMIO(0x6B22C)
-#define DSCC_PICTURE_PARAMETER_SET_11		_MMIO(0x6BA2C)
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB	0x7829C
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB	0x7839C
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC	0x7849C
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC	0x7859C
-#define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							   _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \
-							   _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC)
-#define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							   _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \
-							   _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC)
-
-#define DSCA_PICTURE_PARAMETER_SET_12		_MMIO(0x6B260)
-#define DSCC_PICTURE_PARAMETER_SET_12		_MMIO(0x6BA60)
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB	0x782A0
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB	0x783A0
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC	0x784A0
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC	0x785A0
-#define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							   _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \
-							   _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC)
-#define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							   _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \
-							   _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC)
-
-#define DSCA_PICTURE_PARAMETER_SET_13		_MMIO(0x6B264)
-#define DSCC_PICTURE_PARAMETER_SET_13		_MMIO(0x6BA64)
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB	0x782A4
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB	0x783A4
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC	0x784A4
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC	0x785A4
-#define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							   _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \
-							   _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC)
-#define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							   _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \
-							   _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC)
-
-#define DSCA_PICTURE_PARAMETER_SET_14		_MMIO(0x6B268)
-#define DSCC_PICTURE_PARAMETER_SET_14		_MMIO(0x6BA68)
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB	0x782A8
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB	0x783A8
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC	0x784A8
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC	0x785A8
-#define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							   _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \
-							   _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC)
-#define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							   _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \
-							   _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC)
-
-#define DSCA_PICTURE_PARAMETER_SET_15		_MMIO(0x6B26C)
-#define DSCC_PICTURE_PARAMETER_SET_15		_MMIO(0x6BA6C)
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB	0x782AC
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB	0x783AC
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC	0x784AC
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC	0x785AC
-#define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							   _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \
-							   _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC)
-#define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							   _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \
-							   _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC)
-
-#define DSCA_PICTURE_PARAMETER_SET_16		_MMIO(0x6B270)
-#define DSCC_PICTURE_PARAMETER_SET_16		_MMIO(0x6BA70)
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB	0x782B0
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB	0x783B0
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC	0x784B0
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC	0x785B0
-#define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							   _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \
-							   _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC)
-#define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							   _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
-							   _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
+/* PPS16 */
 #define  DSC_SLICE_ROW_PR_FRME_MASK			REG_GENMASK(31, 20)
 #define  DSC_SLICE_PER_LINE_MASK			REG_GENMASK(18, 16)
 #define  DSC_SLICE_CHUNK_SIZE_MASK			REG_GENMASK(15, 0)
@@ -385,6 +163,17 @@
 #define  DSC_SLICE_CHUNK_SIZE(slice_chunk_size)		REG_FIELD_PREP(DSC_SLICE_CHUNK_SIZE_MASK, \
 								       slice_chunk_size)
 
+/* MTL Display Stream Compression registers */
+/* PPS17 */
+#define DSC_SL_BPG_OFFSET_MASK			REG_GENMASK(31, 27)
+#define DSC_SL_BPG_OFFSET(offset)		REG_FIELD_PREP(DSC_SL_BPG_OFFSET_MASK, offset)
+
+/* PPS18 */
+#define DSC_NSL_BPG_OFFSET_MASK			REG_GENMASK(31, 16)
+#define DSC_SL_OFFSET_ADJ_MASK			REG_GENMASK(15, 0)
+#define DSC_NSL_BPG_OFFSET(offset)		REG_FIELD_PREP(DSC_NSL_BPG_OFFSET_MASK, offset)
+#define DSC_SL_OFFSET_ADJ(offset)		REG_FIELD_PREP(DSC_SL_OFFSET_ADJ_MASK, offset)
+
 /* Icelake Rate Control Buffer Threshold Registers */
 #define DSCA_RC_BUF_THRESH_0			_MMIO(0x6B230)
 #define DSCA_RC_BUF_THRESH_0_UDW		_MMIO(0x6B230 + 4)
-- 
2.25.1

[Intel-gfx] [PATCH v7 7/8] drm/i915/vdsc: Fill the intel_dsc_get_pps_config function

[Suraj Kandpal]

We have setup both the read and write functions so we can
move ahead and fill in all the readout state from PPS register
into the crtc_state so we can send it for comparision.

--v2
-Shorten comment to just PPSX rather than having the whole
"Readout PPSX register" [Jani]
-Remove pps_temp reinitialization as its being initialized in
the read function [Jani]
-Use REG_FIELD_GET to readout certain fields of dsc registers
[Jani]

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 99 +++++++++++++++++--
 .../gpu/drm/i915/display/intel_vdsc_regs.h    |  3 +
 2 files changed, 95 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 22bb22678fee..67ed8e8cef35 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -891,20 +891,105 @@ static void intel_dsc_read_and_verify_pps_reg(struct intel_crtc_state *crtc_stat
 static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
 {
 	struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
-	u32 pps_temp1, pps_temp2;
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+	u32 pps_temp;
 
-	/* FIXME: add more state readout as needed */
+	/* PPS_0 */
+	intel_dsc_read_and_verify_pps_reg(crtc_state, 0, &pps_temp);
 
-	/* Readout PPS_0 and PPS_1 registers */
-	intel_dsc_read_and_verify_pps_reg(crtc_state, 0, &pps_temp1);
-	intel_dsc_read_and_verify_pps_reg(crtc_state, 1, &pps_temp2);
+	vdsc_cfg->bits_per_component = (pps_temp & DSC_BPC_MASK) >> DSC_BPC_SHIFT;
+	vdsc_cfg->line_buf_depth =
+		(pps_temp & DSC_LINE_BUF_DEPTH_MASK) >> DSC_LINE_BUF_DEPTH_SHIFT;
+	vdsc_cfg->block_pred_enable = pps_temp & DSC_BLOCK_PREDICTION;
+	vdsc_cfg->convert_rgb = pps_temp & DSC_COLOR_SPACE_CONVERSION;
+	vdsc_cfg->simple_422 = pps_temp & DSC_422_ENABLE;
+	vdsc_cfg->native_422 = pps_temp & DSC_NATIVE_422_ENABLE;
+	vdsc_cfg->native_420 = pps_temp & DSC_NATIVE_420_ENABLE;
+	vdsc_cfg->vbr_enable = pps_temp & DSC_VBR_ENABLE;
 
-	vdsc_cfg->bits_per_pixel = pps_temp2;
+	/* PPS_1 */
+	intel_dsc_read_and_verify_pps_reg(crtc_state, 1, &pps_temp);
 
-	if (pps_temp1 & DSC_NATIVE_420_ENABLE)
+	vdsc_cfg->bits_per_pixel = pps_temp;
+
+	if (vdsc_cfg->native_420)
 		vdsc_cfg->bits_per_pixel >>= 1;
 
 	crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
+
+	/* PPS_2 */
+	intel_dsc_read_and_verify_pps_reg(crtc_state, 2, &pps_temp);
+
+	vdsc_cfg->pic_width = REG_FIELD_GET(DSC_PIC_WIDTH_MASK, pps_temp);
+	vdsc_cfg->pic_height = REG_FIELD_GET(DSC_PIC_HEIGHT_MASK, pps_temp);
+
+	/* PPS_3 */
+	intel_dsc_read_and_verify_pps_reg(crtc_state, 3, &pps_temp);
+
+	vdsc_cfg->slice_width = REG_FIELD_GET(DSC_SLICE_WIDTH_MASK, pps_temp);
+	vdsc_cfg->slice_height = REG_FIELD_GET(DSC_SLICE_HEIGHT_MASK, pps_temp);
+
+	/* PPS_4 */
+	intel_dsc_read_and_verify_pps_reg(crtc_state, 4, &pps_temp);
+
+	vdsc_cfg->initial_dec_delay = REG_FIELD_GET(DSC_INITIAL_DEC_DELAY_MASK, pps_temp);
+	vdsc_cfg->initial_xmit_delay = REG_FIELD_GET(DSC_INITIAL_XMIT_DELAY_MASK, pps_temp);
+
+	/* PPS_5 */
+	intel_dsc_read_and_verify_pps_reg(crtc_state, 5, &pps_temp);
+
+	vdsc_cfg->scale_decrement_interval = REG_FIELD_GET(DSC_SCALE_DEC_INT_MASK, pps_temp);
+	vdsc_cfg->scale_increment_interval = REG_FIELD_GET(DSC_SCALE_INC_INT_MASK, pps_temp);
+
+	/* PPS_6 */
+	intel_dsc_read_and_verify_pps_reg(crtc_state, 6, &pps_temp);
+
+	vdsc_cfg->initial_scale_value = REG_FIELD_GET(DSC_INITIAL_SCALE_VALUE_MASK, pps_temp);
+	vdsc_cfg->first_line_bpg_offset = REG_FIELD_GET(DSC_FIRST_LINE_BPG_OFFSET_MASK, pps_temp);
+	vdsc_cfg->flatness_min_qp = REG_FIELD_GET(DSC_FLATNESS_MIN_QP_MASK, pps_temp);
+	vdsc_cfg->flatness_max_qp = REG_FIELD_GET(DSC_FLATNESS_MAX_QP_MASK, pps_temp);
+
+	/* PPS_7 */
+	intel_dsc_read_and_verify_pps_reg(crtc_state, 7, &pps_temp);
+
+	vdsc_cfg->nfl_bpg_offset = REG_FIELD_GET(DSC_NFL_BPG_OFFSET_MASK, pps_temp);
+	vdsc_cfg->slice_bpg_offset = REG_FIELD_GET(DSC_SLICE_BPG_OFFSET_MASK, pps_temp);
+
+	/* PPS_8 */
+	intel_dsc_read_and_verify_pps_reg(crtc_state, 8, &pps_temp);
+
+	vdsc_cfg->initial_offset = REG_FIELD_GET(DSC_INITIAL_OFFSET_MASK, pps_temp);
+	vdsc_cfg->final_offset = REG_FIELD_GET(DSC_FINAL_OFFSET_MASK, pps_temp);
+
+	/* PPS_9 */
+	intel_dsc_read_and_verify_pps_reg(crtc_state, 9, &pps_temp);
+
+	vdsc_cfg->rc_model_size = REG_FIELD_GET(DSC_RC_MODEL_SIZE_MASK, pps_temp);
+
+	/* PPS_10 */
+	intel_dsc_read_and_verify_pps_reg(crtc_state, 10, &pps_temp);
+
+	vdsc_cfg->rc_quant_incr_limit0 = REG_FIELD_GET(DSC_RC_QUANT_INC_LIMIT0_MASK, pps_temp);
+	vdsc_cfg->rc_quant_incr_limit1 = REG_FIELD_GET(DSC_RC_QUANT_INC_LIMIT1_MASK, pps_temp);
+
+	/* PPS_16 */
+	intel_dsc_read_and_verify_pps_reg(crtc_state, 16, &pps_temp);
+
+	vdsc_cfg->slice_chunk_size = REG_FIELD_GET(DSC_SLICE_CHUNK_SIZE_MASK, pps_temp);
+
+	if (DISPLAY_VER(i915) >= 14) {
+		/* PPS_17 */
+		intel_dsc_read_and_verify_pps_reg(crtc_state, 17, &pps_temp);
+
+		vdsc_cfg->second_line_bpg_offset = REG_FIELD_GET(DSC_SL_BPG_OFFSET_MASK, pps_temp);
+
+		/* PPS_18 */
+		intel_dsc_read_and_verify_pps_reg(crtc_state, 18, &pps_temp);
+
+		vdsc_cfg->nsl_bpg_offset = REG_FIELD_GET(DSC_NSL_BPG_OFFSET_MASK, pps_temp);
+		vdsc_cfg->second_line_offset_adj = REG_FIELD_GET(DSC_SL_OFFSET_ADJ_MASK, pps_temp);
+	}
 }
 
 void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
index 7afc487223fb..8d4fcacd1229 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
@@ -76,6 +76,9 @@
 #define  DSC_BPC_SHIFT			8
 #define  DSC_VER_MIN_SHIFT		4
 #define  DSC_VER_MAJ			(0x1 << 0)
+#define  DSC_LINE_BUF_DEPTH_MASK	REG_GENMASK(15, 12)
+#define  DSC_BPC_MASK			REG_GENMASK(11, 8)
+
 
 /* PPS1 */
 #define  DSC_BPP(bpp)				((bpp) << 0)
-- 
2.25.1

[Intel-gfx] [PATCH v7 8/8] drm/i915/display: Compare the readout dsc pps params

[Suraj Kandpal]

With the dsc config being readout and filled in crtc_state add
macros and use them to compare current and previous PPS param in
DSC.

--v2
-Remove version check [Jani]
-Remove dupe macro for dsc pipe compare and use the existing ones
[Jani]

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 31 ++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 43cba98f7753..9c407ceb082e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5376,6 +5376,37 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	PIPE_CONF_CHECK_I(master_transcoder);
 	PIPE_CONF_CHECK_X(bigjoiner_pipes);
 
+	PIPE_CONF_CHECK_BOOL(dsc.config.block_pred_enable);
+	PIPE_CONF_CHECK_BOOL(dsc.config.convert_rgb);
+	PIPE_CONF_CHECK_BOOL(dsc.config.simple_422);
+	PIPE_CONF_CHECK_BOOL(dsc.config.native_422);
+	PIPE_CONF_CHECK_BOOL(dsc.config.native_420);
+	PIPE_CONF_CHECK_BOOL(dsc.config.vbr_enable);
+	PIPE_CONF_CHECK_I(dsc.config.line_buf_depth);
+	PIPE_CONF_CHECK_I(dsc.config.bits_per_component);
+	PIPE_CONF_CHECK_I(dsc.config.pic_width);
+	PIPE_CONF_CHECK_I(dsc.config.pic_height);
+	PIPE_CONF_CHECK_I(dsc.config.slice_width);
+	PIPE_CONF_CHECK_I(dsc.config.slice_height);
+	PIPE_CONF_CHECK_I(dsc.config.initial_dec_delay);
+	PIPE_CONF_CHECK_I(dsc.config.initial_xmit_delay);
+	PIPE_CONF_CHECK_I(dsc.config.scale_decrement_interval);
+	PIPE_CONF_CHECK_I(dsc.config.scale_increment_interval);
+	PIPE_CONF_CHECK_I(dsc.config.initial_scale_value);
+	PIPE_CONF_CHECK_I(dsc.config.first_line_bpg_offset);
+	PIPE_CONF_CHECK_I(dsc.config.flatness_min_qp);
+	PIPE_CONF_CHECK_I(dsc.config.flatness_max_qp);
+	PIPE_CONF_CHECK_I(dsc.config.slice_bpg_offset);
+	PIPE_CONF_CHECK_I(dsc.config.nfl_bpg_offset);
+	PIPE_CONF_CHECK_I(dsc.config.initial_offset);
+	PIPE_CONF_CHECK_I(dsc.config.final_offset);
+	PIPE_CONF_CHECK_I(dsc.config.rc_model_size);
+	PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit0);
+	PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit1);
+	PIPE_CONF_CHECK_I(dsc.config.slice_chunk_size);
+	PIPE_CONF_CHECK_I(dsc.config.second_line_bpg_offset);
+	PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset);
+
 	PIPE_CONF_CHECK_I(dsc.compression_enable);
 	PIPE_CONF_CHECK_I(dsc.dsc_split);
 	PIPE_CONF_CHECK_I(dsc.compressed_bpp);
-- 
2.25.1

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DSC PPS readout (rev7)

[Patchwork]

== Series Details ==

Series: Add DSC PPS readout (rev7)
URL   : https://patchwork.freedesktop.org/series/120456/
State : warning

== Summary ==

Error: dim checkpatch failed
/home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add DSC PPS readout (rev7)

[Patchwork]

== Series Details ==

Series: Add DSC PPS readout (rev7)
URL   : https://patchwork.freedesktop.org/series/120456/
State : warning

== Summary ==

Error: dim sparse failed
/home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory

[Intel-gfx] ✓ Fi.CI.BAT: success for Add DSC PPS readout (rev7)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 8313 bytes --]

== Series Details ==

Series: Add DSC PPS readout (rev7)
URL   : https://patchwork.freedesktop.org/series/120456/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13489 -> Patchwork_120456v7
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/index.html

Participating hosts (43 -> 40)
------------------------------

  Missing    (3): fi-kbl-soraka fi-tgl-1115g4 fi-snb-2520m 

Known issues
------------

  Here are the changes found in Patchwork_120456v7 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s3@smem:
    - bat-dg2-11:         [PASS][1] -> [INCOMPLETE][2] ([i915#6311])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/bat-dg2-11/igt@gem_exec_suspend@basic-s3@smem.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/bat-dg2-11/igt@gem_exec_suspend@basic-s3@smem.html

  * igt@i915_pm_rpm@basic-rte:
    - fi-cfl-8109u:       [PASS][3] -> [FAIL][4] ([i915#7940])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/fi-cfl-8109u/igt@i915_pm_rpm@basic-rte.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/fi-cfl-8109u/igt@i915_pm_rpm@basic-rte.html

  * igt@i915_pm_rpm@module-reload:
    - fi-apl-guc:         [PASS][5] -> [DMESG-FAIL][6] ([i915#8585])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/fi-apl-guc/igt@i915_pm_rpm@module-reload.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/fi-apl-guc/igt@i915_pm_rpm@module-reload.html
    - fi-rkl-11600:       [PASS][7] -> [FAIL][8] ([i915#7940])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/fi-rkl-11600/igt@i915_pm_rpm@module-reload.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/fi-rkl-11600/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live@gt_mocs:
    - bat-mtlp-8:         [PASS][9] -> [DMESG-FAIL][10] ([i915#7059])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html

  * igt@i915_selftest@live@requests:
    - bat-mtlp-8:         [PASS][11] -> [DMESG-FAIL][12] ([i915#8497])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/bat-mtlp-8/igt@i915_selftest@live@requests.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/bat-mtlp-8/igt@i915_selftest@live@requests.html

  * igt@i915_selftest@live@reset:
    - fi-apl-guc:         [PASS][13] -> [DMESG-WARN][14] ([i915#7634]) +31 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/fi-apl-guc/igt@i915_selftest@live@reset.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/fi-apl-guc/igt@i915_selftest@live@reset.html

  * igt@i915_selftest@live@slpc:
    - bat-mtlp-8:         [PASS][15] -> [DMESG-WARN][16] ([i915#6367])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/bat-mtlp-8/igt@i915_selftest@live@slpc.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/bat-mtlp-8/igt@i915_selftest@live@slpc.html

  * igt@i915_suspend@basic-s2idle-without-i915:
    - fi-apl-guc:         [PASS][17] -> [DMESG-WARN][18] ([i915#180] / [i915#7634] / [i915#8585])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/fi-apl-guc/igt@i915_suspend@basic-s2idle-without-i915.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/fi-apl-guc/igt@i915_suspend@basic-s2idle-without-i915.html

  * igt@kms_chamelium_hpd@common-hpd-after-suspend:
    - bat-rpls-2:         NOTRUN -> [SKIP][19] ([i915#7828])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/bat-rpls-2/igt@kms_chamelium_hpd@common-hpd-after-suspend.html

  * igt@kms_pipe_crc_basic@read-crc:
    - bat-dg2-11:         NOTRUN -> [SKIP][20] ([i915#1845] / [i915#5354]) +1 similar issue
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/bat-dg2-11/igt@kms_pipe_crc_basic@read-crc.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
    - bat-rpls-2:         NOTRUN -> [SKIP][21] ([i915#1845])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/bat-rpls-2/igt@kms_pipe_crc_basic@suspend-read-crc.html

  
#### Possible fixes ####

  * igt@i915_pm_rpm@basic-rte:
    - fi-kbl-x1275:       [FAIL][22] ([i915#8843]) -> [PASS][23]
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/fi-kbl-x1275/igt@i915_pm_rpm@basic-rte.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/fi-kbl-x1275/igt@i915_pm_rpm@basic-rte.html

  * igt@i915_selftest@live@migrate:
    - bat-dg2-11:         [DMESG-WARN][24] ([i915#7699]) -> [PASS][25]
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/bat-dg2-11/igt@i915_selftest@live@migrate.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/bat-dg2-11/igt@i915_selftest@live@migrate.html

  * igt@i915_selftest@live@slpc:
    - bat-mtlp-6:         [DMESG-WARN][26] ([i915#6367]) -> [PASS][27]
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/bat-mtlp-6/igt@i915_selftest@live@slpc.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/bat-mtlp-6/igt@i915_selftest@live@slpc.html

  * igt@i915_suspend@basic-s3-without-i915:
    - bat-rpls-2:         [ABORT][28] ([i915#6687] / [i915#7978] / [i915#8668]) -> [PASS][29]
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/bat-rpls-2/igt@i915_suspend@basic-s3-without-i915.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/bat-rpls-2/igt@i915_suspend@basic-s3-without-i915.html

  
#### Warnings ####

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - bat-adlp-9:         [FAIL][30] ([i915#7691]) -> [FAIL][31] ([i915#7940])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/bat-adlp-9/igt@i915_pm_rpm@basic-pci-d3-state.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/bat-adlp-9/igt@i915_pm_rpm@basic-pci-d3-state.html

  
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#6311]: https://gitlab.freedesktop.org/drm/intel/issues/6311
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
  [i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059
  [i915#7634]: https://gitlab.freedesktop.org/drm/intel/issues/7634
  [i915#7691]: https://gitlab.freedesktop.org/drm/intel/issues/7691
  [i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#7940]: https://gitlab.freedesktop.org/drm/intel/issues/7940
  [i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
  [i915#8497]: https://gitlab.freedesktop.org/drm/intel/issues/8497
  [i915#8585]: https://gitlab.freedesktop.org/drm/intel/issues/8585
  [i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
  [i915#8843]: https://gitlab.freedesktop.org/drm/intel/issues/8843


Build changes
-------------

  * Linux: CI_DRM_13489 -> Patchwork_120456v7

  CI-20190529: 20190529
  CI_DRM_13489: ba0acfd5bae2ff82ebfd23d50d4e80020fa9c4c1 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7420: 7420
  Patchwork_120456v7: ba0acfd5bae2ff82ebfd23d50d4e80020fa9c4c1 @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

9895feb293e5 drm/i915/display: Compare the readout dsc pps params
7f92b298240b drm/i915/vdsc: Fill the intel_dsc_get_pps_config function
543b4d3bbac0 drm/i915/vdsc: Remove unused dsc registers
2c4dc0cf21f0 drm/i915/vdsc: Add function to write in PPS register
241baea0eb0e drm/i915/vdsc: Add function to read any PPS register
1c0da6b76035 drm/i915/vdsc: Add func to get no. of vdsc instances per pipe
b2e3976d3b68 drm/i915/vdsc: Add a check for dsc split cases
c614d0aa0c10 drm/i915/vdsc: Refactor dsc register field macro

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/index.html

[-- Attachment #2: Type: text/html, Size: 9764 bytes --]

[Intel-gfx] ✗ Fi.CI.IGT: failure for Add DSC PPS readout (rev7)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 55525 bytes --]

== Series Details ==

Series: Add DSC PPS readout (rev7)
URL   : https://patchwork.freedesktop.org/series/120456/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13489_full -> Patchwork_120456v7_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_120456v7_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_120456v7_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (11 -> 10)
------------------------------

  Missing    (1): shard-rkl0 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_120456v7_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_exec_whisper@basic-queues-forked:
    - shard-dg1:          [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-dg1-16/igt@gem_exec_whisper@basic-queues-forked.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-dg1-13/igt@gem_exec_whisper@basic-queues-forked.html

  
Known issues
------------

  Here are the changes found in Patchwork_120456v7_full that come from known issues:

### CI changes ###

#### Possible fixes ####

  * boot:
    - shard-rkl:          ([PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [FAIL][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26]) ([i915#8293]) -> ([PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-rkl-1/boot.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-rkl-1/boot.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-rkl-1/boot.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-rkl-2/boot.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-rkl-2/boot.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-rkl-2/boot.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-rkl-2/boot.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-rkl-2/boot.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-rkl-4/boot.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-rkl-4/boot.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-rkl-4/boot.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-rkl-4/boot.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-rkl-4/boot.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-rkl-6/boot.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-rkl-6/boot.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-rkl-6/boot.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-rkl-6/boot.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-rkl-6/boot.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-rkl-6/boot.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-rkl-7/boot.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-rkl-7/boot.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-rkl-7/boot.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-rkl-7/boot.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-rkl-7/boot.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-1/boot.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-1/boot.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-1/boot.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-1/boot.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-2/boot.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-2/boot.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-2/boot.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-2/boot.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-2/boot.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-2/boot.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-4/boot.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-4/boot.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-4/boot.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-4/boot.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-4/boot.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-4/boot.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-6/boot.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-6/boot.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-6/boot.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-6/boot.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-6/boot.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-7/boot.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-7/boot.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-7/boot.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-7/boot.html

  

### IGT changes ###

#### Issues hit ####

  * igt@drm_mm@drm_mm_test:
    - shard-snb:          NOTRUN -> [SKIP][52] ([fdo#109271] / [i915#8661])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-snb4/igt@drm_mm@drm_mm_test.html

  * igt@feature_discovery@display-2x:
    - shard-rkl:          NOTRUN -> [SKIP][53] ([i915#1839])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-4/igt@feature_discovery@display-2x.html

  * igt@gem_busy@semaphore:
    - shard-mtlp:         NOTRUN -> [SKIP][54] ([i915#3936])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-1/igt@gem_busy@semaphore.html

  * igt@gem_ctx_persistence@hostile:
    - shard-snb:          NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#1099]) +1 similar issue
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-snb2/igt@gem_ctx_persistence@hostile.html

  * igt@gem_eio@hibernate:
    - shard-tglu:         [PASS][56] -> [ABORT][57] ([i915#7975] / [i915#8213] / [i915#8398])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-tglu-5/igt@gem_eio@hibernate.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-tglu-10/igt@gem_eio@hibernate.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-rkl:          NOTRUN -> [FAIL][58] ([i915#2842])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-4/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_exec_reloc@basic-cpu-wc-noreloc:
    - shard-mtlp:         NOTRUN -> [SKIP][59] ([i915#3281])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-8/igt@gem_exec_reloc@basic-cpu-wc-noreloc.html

  * igt@gem_exec_reloc@basic-gtt-cpu:
    - shard-rkl:          NOTRUN -> [SKIP][60] ([i915#3281]) +2 similar issues
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-7/igt@gem_exec_reloc@basic-gtt-cpu.html

  * igt@gem_exec_schedule@semaphore-power:
    - shard-mtlp:         NOTRUN -> [SKIP][61] ([i915#4812])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-8/igt@gem_exec_schedule@semaphore-power.html

  * igt@gem_exec_suspend@basic-s4-devices@smem:
    - shard-rkl:          NOTRUN -> [ABORT][62] ([i915#7975] / [i915#8213])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-7/igt@gem_exec_suspend@basic-s4-devices@smem.html

  * igt@gem_lmem_swapping@heavy-verify-multi-ccs:
    - shard-mtlp:         NOTRUN -> [SKIP][63] ([i915#4613]) +1 similar issue
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-8/igt@gem_lmem_swapping@heavy-verify-multi-ccs.html

  * igt@gem_lmem_swapping@massive-random:
    - shard-rkl:          NOTRUN -> [SKIP][64] ([i915#4613])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-7/igt@gem_lmem_swapping@massive-random.html

  * igt@gem_mmap_wc@write-wc-read-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][65] ([i915#4083])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-8/igt@gem_mmap_wc@write-wc-read-gtt.html

  * igt@gem_pread@bench:
    - shard-mtlp:         NOTRUN -> [SKIP][66] ([i915#3282])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-1/igt@gem_pread@bench.html

  * igt@gem_pread@snoop:
    - shard-rkl:          NOTRUN -> [SKIP][67] ([i915#3282]) +2 similar issues
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-7/igt@gem_pread@snoop.html

  * igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted:
    - shard-mtlp:         NOTRUN -> [SKIP][68] ([i915#4270])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-8/igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted.html

  * igt@gem_pxp@protected-raw-src-copy-not-readible:
    - shard-rkl:          NOTRUN -> [SKIP][69] ([i915#4270]) +1 similar issue
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-7/igt@gem_pxp@protected-raw-src-copy-not-readible.html

  * igt@gem_set_tiling_vs_blt@untiled-to-tiled:
    - shard-mtlp:         NOTRUN -> [SKIP][70] ([i915#4079])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-8/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html

  * igt@gem_softpin@evict-snoop:
    - shard-rkl:          NOTRUN -> [SKIP][71] ([fdo#109312])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-7/igt@gem_softpin@evict-snoop.html

  * igt@gen7_exec_parse@cmd-crossing-page:
    - shard-rkl:          NOTRUN -> [SKIP][72] ([fdo#109289])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-7/igt@gen7_exec_parse@cmd-crossing-page.html

  * igt@gen9_exec_parse@batch-without-end:
    - shard-rkl:          NOTRUN -> [SKIP][73] ([i915#2527])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-4/igt@gen9_exec_parse@batch-without-end.html

  * igt@gen9_exec_parse@bb-chained:
    - shard-mtlp:         NOTRUN -> [SKIP][74] ([i915#2856])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-8/igt@gen9_exec_parse@bb-chained.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-mtlp:         [PASS][75] -> [ABORT][76] ([i915#8489] / [i915#8668])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-mtlp-1/igt@i915_module_load@reload-with-fault-injection.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-1/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_backlight@basic-brightness:
    - shard-rkl:          NOTRUN -> [SKIP][77] ([i915#7561])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-4/igt@i915_pm_backlight@basic-brightness.html

  * igt@i915_pm_rc6_residency@rc6-idle@rcs0:
    - shard-dg1:          [PASS][78] -> [FAIL][79] ([i915#3591]) +1 similar issue
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-dg1-19/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html

  * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-dg2:          [PASS][80] -> [SKIP][81] ([i915#1397]) +1 similar issue
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-dg2-8/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-dg2-10/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@i915_pm_rpm@dpms-non-lpsp:
    - shard-rkl:          [PASS][82] -> [SKIP][83] ([i915#1397])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-rkl-1/igt@i915_pm_rpm@dpms-non-lpsp.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-7/igt@i915_pm_rpm@dpms-non-lpsp.html

  * igt@i915_pm_rpm@drm-resources-equal:
    - shard-rkl:          [PASS][84] -> [FAIL][85] ([i915#7940])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-rkl-2/igt@i915_pm_rpm@drm-resources-equal.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-4/igt@i915_pm_rpm@drm-resources-equal.html

  * igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
    - shard-dg1:          [PASS][86] -> [SKIP][87] ([i915#1397])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-dg1-12/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-dg1-19/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html

  * igt@i915_pm_rpm@system-suspend:
    - shard-dg2:          [PASS][88] -> [FAIL][89] ([fdo#103375]) +3 similar issues
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-dg2-11/igt@i915_pm_rpm@system-suspend.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-dg2-5/igt@i915_pm_rpm@system-suspend.html

  * igt@i915_selftest@live@slpc:
    - shard-mtlp:         [PASS][90] -> [DMESG-WARN][91] ([i915#6367])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-mtlp-7/igt@i915_selftest@live@slpc.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-7/igt@i915_selftest@live@slpc.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-dp-4-4-mc_ccs:
    - shard-dg2:          NOTRUN -> [SKIP][92] ([i915#8709]) +11 similar issues
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-dg2-11/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-dp-4-4-mc_ccs.html

  * igt@kms_async_flips@crc@pipe-a-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [FAIL][93] ([i915#8247]) +3 similar issues
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-dg2-8/igt@kms_async_flips@crc@pipe-a-hdmi-a-3.html

  * igt@kms_async_flips@crc@pipe-b-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [FAIL][94] ([i915#8247]) +1 similar issue
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-7/igt@kms_async_flips@crc@pipe-b-hdmi-a-1.html

  * igt@kms_async_flips@crc@pipe-b-vga-1:
    - shard-snb:          NOTRUN -> [FAIL][95] ([i915#8247]) +1 similar issue
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-snb7/igt@kms_async_flips@crc@pipe-b-vga-1.html

  * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
    - shard-mtlp:         NOTRUN -> [SKIP][96] ([i915#404])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-8/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
    - shard-snb:          NOTRUN -> [SKIP][97] ([fdo#109271] / [i915#1769])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-snb4/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-0:
    - shard-rkl:          NOTRUN -> [SKIP][98] ([i915#5286]) +3 similar issues
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-4/igt@kms_big_fb@4-tiled-32bpp-rotate-0.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0:
    - shard-mtlp:         [PASS][99] -> [FAIL][100] ([i915#5138])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-mtlp-8/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-90:
    - shard-rkl:          NOTRUN -> [SKIP][101] ([fdo#111614] / [i915#3638])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-4/igt@kms_big_fb@x-tiled-32bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
    - shard-mtlp:         [PASS][102] -> [FAIL][103] ([i915#3743])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-mtlp-4/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-2/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - shard-mtlp:         NOTRUN -> [FAIL][104] ([i915#3743])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-8/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
    - shard-mtlp:         NOTRUN -> [SKIP][105] ([i915#6187])
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-8/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@yf-tiled-8bpp-rotate-270:
    - shard-mtlp:         NOTRUN -> [SKIP][106] ([fdo#111615])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-8/igt@kms_big_fb@yf-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
    - shard-rkl:          NOTRUN -> [SKIP][107] ([fdo#110723])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-4/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_big_joiner@2x-modeset:
    - shard-rkl:          NOTRUN -> [SKIP][108] ([i915#2705])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-4/igt@kms_big_joiner@2x-modeset.html

  * igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_ccs:
    - shard-rkl:          NOTRUN -> [SKIP][109] ([i915#3734] / [i915#5354] / [i915#6095]) +3 similar issues
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-4/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_ccs.html

  * igt@kms_ccs@pipe-b-crc-primary-rotation-180-4_tiled_dg2_rc_ccs_cc:
    - shard-rkl:          NOTRUN -> [SKIP][110] ([i915#5354] / [i915#6095]) +3 similar issues
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-4/igt@kms_ccs@pipe-b-crc-primary-rotation-180-4_tiled_dg2_rc_ccs_cc.html

  * igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
    - shard-mtlp:         NOTRUN -> [SKIP][111] ([i915#3886] / [i915#6095]) +1 similar issue
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-8/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-d-crc-primary-rotation-180-4_tiled_dg2_mc_ccs:
    - shard-mtlp:         NOTRUN -> [SKIP][112] ([i915#6095]) +7 similar issues
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-1/igt@kms_ccs@pipe-d-crc-primary-rotation-180-4_tiled_dg2_mc_ccs.html

  * igt@kms_ccs@pipe-d-crc-sprite-planes-basic-4_tiled_dg2_mc_ccs:
    - shard-rkl:          NOTRUN -> [SKIP][113] ([i915#5354]) +10 similar issues
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-4/igt@kms_ccs@pipe-d-crc-sprite-planes-basic-4_tiled_dg2_mc_ccs.html

  * igt@kms_chamelium_color@ctm-negative:
    - shard-rkl:          NOTRUN -> [SKIP][114] ([fdo#111827])
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-4/igt@kms_chamelium_color@ctm-negative.html

  * igt@kms_chamelium_hpd@hdmi-hpd-fast:
    - shard-rkl:          NOTRUN -> [SKIP][115] ([i915#7828]) +1 similar issue
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-4/igt@kms_chamelium_hpd@hdmi-hpd-fast.html

  * igt@kms_chamelium_hpd@hdmi-hpd-storm:
    - shard-mtlp:         NOTRUN -> [SKIP][116] ([i915#7828])
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-8/igt@kms_chamelium_hpd@hdmi-hpd-storm.html

  * igt@kms_color@deep-color:
    - shard-rkl:          NOTRUN -> [SKIP][117] ([i915#3555])
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-6/igt@kms_color@deep-color.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-dg2:          NOTRUN -> [SKIP][118] ([i915#7118])
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-dg2-5/igt@kms_content_protection@atomic-dpms.html
    - shard-rkl:          NOTRUN -> [SKIP][119] ([i915#7118]) +1 similar issue
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-4/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@srm@pipe-a-dp-4:
    - shard-dg2:          NOTRUN -> [TIMEOUT][120] ([i915#7173])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-dg2-11/igt@kms_content_protection@srm@pipe-a-dp-4.html

  * igt@kms_cursor_crc@cursor-random-max-size:
    - shard-mtlp:         NOTRUN -> [SKIP][121] ([i915#8814])
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-8/igt@kms_cursor_crc@cursor-random-max-size.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x170:
    - shard-rkl:          NOTRUN -> [SKIP][122] ([i915#3359])
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-7/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html

  * igt@kms_cursor_crc@cursor-sliding-512x170:
    - shard-mtlp:         NOTRUN -> [SKIP][123] ([i915#3359])
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-8/igt@kms_cursor_crc@cursor-sliding-512x170.html

  * igt@kms_cursor_crc@cursor-suspend@pipe-d-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [FAIL][124] ([fdo#103375])
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-dg2-5/igt@kms_cursor_crc@cursor-suspend@pipe-d-hdmi-a-3.html

  * igt@kms_cursor_legacy@cursor-vs-flip-toggle:
    - shard-mtlp:         [PASS][125] -> [FAIL][126] ([i915#8248])
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-mtlp-7/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-2/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size:
    - shard-mtlp:         NOTRUN -> [SKIP][127] ([i915#3546])
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-8/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-glk:          [PASS][128] -> [FAIL][129] ([i915#2346]) +1 similar issue
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][130] ([i915#3804])
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-2/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2.html

  * igt@kms_flip@2x-flip-vs-rmfb:
    - shard-mtlp:         NOTRUN -> [SKIP][131] ([i915#3637])
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-8/igt@kms_flip@2x-flip-vs-rmfb.html

  * igt@kms_flip@2x-plain-flip-interruptible:
    - shard-rkl:          NOTRUN -> [SKIP][132] ([fdo#111825]) +1 similar issue
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-7/igt@kms_flip@2x-plain-flip-interruptible.html

  * igt@kms_flip@flip-vs-fences-interruptible:
    - shard-mtlp:         NOTRUN -> [SKIP][133] ([i915#8381])
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-8/igt@kms_flip@flip-vs-fences-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][134] ([i915#2672])
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][135] ([i915#8810])
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-8/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling@pipe-a-default-mode.html

  * igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][136] ([i915#8708])
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-8/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw:
    - shard-rkl:          NOTRUN -> [SKIP][137] ([i915#3023]) +10 similar issues
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-mtlp:         NOTRUN -> [SKIP][138] ([i915#1825]) +5 similar issues
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][139] ([fdo#111825] / [i915#1825]) +13 similar issues
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt.html

  * igt@kms_hdr@static-toggle-suspend:
    - shard-dg2:          NOTRUN -> [SKIP][140] ([i915#3555] / [i915#8228])
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-dg2-5/igt@kms_hdr@static-toggle-suspend.html
    - shard-rkl:          NOTRUN -> [SKIP][141] ([i915#3555] / [i915#8228])
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-4/igt@kms_hdr@static-toggle-suspend.html

  * igt@kms_invalid_mode@clock-too-high@edp-1-pipe-d:
    - shard-mtlp:         NOTRUN -> [SKIP][142] ([i915#6403]) +3 similar issues
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-8/igt@kms_invalid_mode@clock-too-high@edp-1-pipe-d.html

  * igt@kms_plane@pixel-format-source-clamping@pipe-b-planes:
    - shard-mtlp:         NOTRUN -> [FAIL][143] ([i915#1623])
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-8/igt@kms_plane@pixel-format-source-clamping@pipe-b-planes.html

  * igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [FAIL][144] ([i915#8292])
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-1/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2.html

  * igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [FAIL][145] ([i915#8292])
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-dg1-18/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-4.html

  * igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-b-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][146] ([i915#5176]) +3 similar issues
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-dg2-3/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-b-hdmi-a-3.html

  * igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-b-hdmi-a-1:
    - shard-dg1:          NOTRUN -> [SKIP][147] ([i915#5176]) +15 similar issues
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-dg1-19/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-b-hdmi-a-1.html

  * igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][148] ([i915#5176]) +1 similar issue
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-2/igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-a-hdmi-a-2.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][149] ([i915#5235]) +1 similar issue
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-7/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b-hdmi-a-1.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][150] ([i915#5235]) +7 similar issues
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-dg2-8/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-3.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling@pipe-a-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][151] ([i915#5235]) +3 similar issues
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-8/igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling@pipe-a-edp-1.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling@pipe-b-vga-1:
    - shard-snb:          NOTRUN -> [SKIP][152] ([fdo#109271]) +268 similar issues
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-snb4/igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling@pipe-b-vga-1.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-1:
    - shard-dg1:          NOTRUN -> [SKIP][153] ([i915#5235]) +11 similar issues
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-dg1-19/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-1.html

  * igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
    - shard-rkl:          NOTRUN -> [SKIP][154] ([i915#658])
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-4/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html

  * igt@kms_psr@primary_render:
    - shard-rkl:          NOTRUN -> [SKIP][155] ([i915#1072]) +1 similar issue
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-4/igt@kms_psr@primary_render.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
    - shard-rkl:          NOTRUN -> [SKIP][156] ([fdo#111615] / [i915#5289])
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-7/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html

  * igt@kms_selftest@drm_format:
    - shard-rkl:          NOTRUN -> [SKIP][157] ([i915#8661])
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-4/igt@kms_selftest@drm_format.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - shard-rkl:          NOTRUN -> [SKIP][158] ([i915#3555] / [i915#4098])
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-7/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@kms_setmode@invalid-clone-single-crtc:
    - shard-mtlp:         NOTRUN -> [SKIP][159] ([i915#8809])
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-1/igt@kms_setmode@invalid-clone-single-crtc.html

  * igt@kms_vblank@pipe-c-ts-continuation-suspend:
    - shard-rkl:          NOTRUN -> [SKIP][160] ([i915#4070] / [i915#6768])
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-7/igt@kms_vblank@pipe-c-ts-continuation-suspend.html

  * igt@kms_vblank@pipe-d-query-busy:
    - shard-rkl:          NOTRUN -> [SKIP][161] ([i915#4070] / [i915#533] / [i915#6768]) +2 similar issues
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-4/igt@kms_vblank@pipe-d-query-busy.html

  * igt@perf@enable-disable@0-rcs0:
    - shard-dg2:          [PASS][162] -> [FAIL][163] ([i915#8724])
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-dg2-6/igt@perf@enable-disable@0-rcs0.html
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-dg2-11/igt@perf@enable-disable@0-rcs0.html

  * igt@perf_pmu@busy-double-start@vecs1:
    - shard-dg2:          [PASS][164] -> [FAIL][165] ([i915#4349]) +3 similar issues
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-dg2-6/igt@perf_pmu@busy-double-start@vecs1.html
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-dg2-5/igt@perf_pmu@busy-double-start@vecs1.html

  * igt@perf_pmu@rc6-suspend:
    - shard-snb:          NOTRUN -> [DMESG-WARN][166] ([i915#8841]) +5 similar issues
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-snb1/igt@perf_pmu@rc6-suspend.html

  * igt@sysfs_heartbeat_interval@nopreempt@vcs0:
    - shard-mtlp:         [PASS][167] -> [FAIL][168] ([i915#6015]) +1 similar issue
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-mtlp-4/igt@sysfs_heartbeat_interval@nopreempt@vcs0.html
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-2/igt@sysfs_heartbeat_interval@nopreempt@vcs0.html

  * igt@v3d/v3d_perfmon@create-perfmon-0:
    - shard-rkl:          NOTRUN -> [SKIP][169] ([fdo#109315]) +4 similar issues
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-7/igt@v3d/v3d_perfmon@create-perfmon-0.html

  * igt@v3d/v3d_perfmon@get-values-valid-perfmon:
    - shard-mtlp:         NOTRUN -> [SKIP][170] ([i915#2575]) +4 similar issues
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-8/igt@v3d/v3d_perfmon@get-values-valid-perfmon.html

  * igt@vc4/vc4_tiling@set-get:
    - shard-rkl:          NOTRUN -> [SKIP][171] ([i915#7711]) +2 similar issues
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-4/igt@vc4/vc4_tiling@set-get.html

  * igt@vc4/vc4_wait_seqno@bad-seqno-1ns:
    - shard-mtlp:         NOTRUN -> [SKIP][172] ([i915#7711]) +2 similar issues
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-8/igt@vc4/vc4_wait_seqno@bad-seqno-1ns.html

  
#### Possible fixes ####

  * igt@gem_eio@in-flight-contexts-immediate:
    - shard-mtlp:         [ABORT][173] ([i915#8503]) -> [PASS][174]
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-mtlp-4/igt@gem_eio@in-flight-contexts-immediate.html
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-8/igt@gem_eio@in-flight-contexts-immediate.html

  * igt@gem_eio@reset-stress:
    - shard-dg1:          [FAIL][175] ([i915#5784]) -> [PASS][176]
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-dg1-18/igt@gem_eio@reset-stress.html
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-dg1-17/igt@gem_eio@reset-stress.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - shard-apl:          [FAIL][177] ([i915#2842]) -> [PASS][178]
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-apl6/igt@gem_exec_fair@basic-none-solo@rcs0.html
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-apl7/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@gem_exec_whisper@basic-contexts-forked-all:
    - shard-mtlp:         [ABORT][179] ([i915#7392] / [i915#8131]) -> [PASS][180]
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-mtlp-2/igt@gem_exec_whisper@basic-contexts-forked-all.html
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-8/igt@gem_exec_whisper@basic-contexts-forked-all.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-dg2:          [DMESG-WARN][181] ([i915#7061] / [i915#8617]) -> [PASS][182]
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-dg2-10/igt@i915_module_load@reload-with-fault-injection.html
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-dg2-8/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pipe_stress@stress-xrgb8888-untiled:
    - shard-mtlp:         [FAIL][183] ([i915#8691]) -> [PASS][184]
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-mtlp-8/igt@i915_pipe_stress@stress-xrgb8888-untiled.html
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-6/igt@i915_pipe_stress@stress-xrgb8888-untiled.html

  * igt@i915_pm_rc6_residency@rc6-idle@bcs0:
    - shard-dg1:          [FAIL][185] ([i915#3591]) -> [PASS][186]
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-dg1-19/igt@i915_pm_rc6_residency@rc6-idle@bcs0.html
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-idle@bcs0.html

  * igt@i915_pm_rpm@dpms-mode-unset-lpsp:
    - shard-tglu:         [FAIL][187] ([i915#7940]) -> [PASS][188]
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-tglu-2/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-tglu-2/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html

  * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-dg1:          [FAIL][189] ([i915#7940]) -> [PASS][190] +2 similar issues
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-dg1-16/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-dg1-13/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@i915_pm_rpm@modeset-lpsp-stress:
    - shard-dg1:          [SKIP][191] ([i915#1397]) -> [PASS][192]
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-dg1-18/igt@i915_pm_rpm@modeset-lpsp-stress.html
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-dg1-19/igt@i915_pm_rpm@modeset-lpsp-stress.html

  * igt@i915_pm_rpm@modeset-non-lpsp-stress:
    - shard-rkl:          [SKIP][193] ([i915#1397]) -> [PASS][194] +1 similar issue
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-rkl-7/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-1/igt@i915_pm_rpm@modeset-non-lpsp-stress.html

  * igt@i915_selftest@live@gt_mocs:
    - shard-mtlp:         [DMESG-FAIL][195] ([i915#7059]) -> [PASS][196]
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-mtlp-7/igt@i915_selftest@live@gt_mocs.html
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-7/igt@i915_selftest@live@gt_mocs.html

  * igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1:
    - shard-mtlp:         [FAIL][197] ([i915#2521]) -> [PASS][198]
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-mtlp-7/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1.html
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-2/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-mtlp:         [FAIL][199] ([i915#5138]) -> [PASS][200]
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-mtlp-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-8/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-apl:          [FAIL][201] ([i915#2346]) -> [PASS][202]
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-apl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-apl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt:
    - shard-dg2:          [FAIL][203] ([i915#6880]) -> [PASS][204]
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt.html
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt.html

  * igt@kms_plane@pixel-format@pipe-b-planes:
    - shard-mtlp:         [FAIL][205] ([i915#1623]) -> [PASS][206]
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-mtlp-6/igt@kms_plane@pixel-format@pipe-b-planes.html
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-4/igt@kms_plane@pixel-format@pipe-b-planes.html

  * igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
    - shard-dg2:          [FAIL][207] ([fdo#103375]) -> [PASS][208] +1 similar issue
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-dg2-11/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-dg2-2/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html

  * igt@sysfs_heartbeat_interval@nopreempt@vecs0:
    - shard-mtlp:         [FAIL][209] ([i915#6015]) -> [PASS][210]
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-mtlp-4/igt@sysfs_heartbeat_interval@nopreempt@vecs0.html
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-2/igt@sysfs_heartbeat_interval@nopreempt@vecs0.html

  
#### Warnings ####

  * igt@gem_lmem_swapping@smem-oom@lmem0:
    - shard-dg1:          [DMESG-WARN][211] ([i915#4936] / [i915#5493]) -> [TIMEOUT][212] ([i915#5493])
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-dg1-17/igt@gem_lmem_swapping@smem-oom@lmem0.html
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-dg1-18/igt@gem_lmem_swapping@smem-oom@lmem0.html

  * igt@gem_workarounds@suspend-resume-context:
    - shard-snb:          [DMESG-WARN][213] ([i915#8841]) -> [DMESG-FAIL][214] ([fdo#103375])
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-snb1/igt@gem_workarounds@suspend-resume-context.html
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-snb7/igt@gem_workarounds@suspend-resume-context.html

  * igt@i915_pm_rc6_residency@rc6-idle@rcs0:
    - shard-tglu:         [WARN][215] ([i915#2681]) -> [FAIL][216] ([i915#2681] / [i915#3591])
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-tglu-3/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-tglu-9/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html

  * igt@i915_pm_rc6_residency@rc6-idle@vecs0:
    - shard-tglu:         [FAIL][217] ([i915#2681] / [i915#3591]) -> [WARN][218] ([i915#2681])
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-tglu-3/igt@i915_pm_rc6_residency@rc6-idle@vecs0.html
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-tglu-9/igt@i915_pm_rc6_residency@rc6-idle@vecs0.html

  * igt@kms_content_protection@content_type_change:
    - shard-dg2:          [SKIP][219] ([i915#7118] / [i915#7162]) -> [SKIP][220] ([i915#7118])
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-dg2-11/igt@kms_content_protection@content_type_change.html
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-dg2-2/igt@kms_content_protection@content_type_change.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-mtlp:         [DMESG-FAIL][221] ([i915#2017] / [i915#5954]) -> [FAIL][222] ([i915#2346])
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-mtlp-2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-mtlp-8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_fbcon_fbt@psr:
    - shard-rkl:          [SKIP][223] ([i915#3955]) -> [SKIP][224] ([fdo#110189] / [i915#3955])
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-rkl-7/igt@kms_fbcon_fbt@psr.html
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-1/igt@kms_fbcon_fbt@psr.html

  * igt@kms_force_connector_basic@force-load-detect:
    - shard-rkl:          [SKIP][225] ([fdo#109285] / [i915#4098]) -> [SKIP][226] ([fdo#109285])
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-rkl-4/igt@kms_force_connector_basic@force-load-detect.html
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-6/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-rkl:          [SKIP][227] ([i915#4070] / [i915#4816]) -> [SKIP][228] ([i915#4816])
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-rkl-2/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-rkl-4/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_psr@sprite_plane_onoff:
    - shard-dg1:          [SKIP][229] ([i915#1072] / [i915#4078]) -> [SKIP][230] ([i915#1072])
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-dg1-18/igt@kms_psr@sprite_plane_onoff.html
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-dg1-17/igt@kms_psr@sprite_plane_onoff.html

  * igt@perf@non-zero-reason@0-rcs0:
    - shard-dg2:          [FAIL][231] ([i915#7484]) -> [FAIL][232] ([i915#3089])
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-dg2-11/igt@perf@non-zero-reason@0-rcs0.html
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-dg2-11/igt@perf@non-zero-reason@0-rcs0.html

  * igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem:
    - shard-dg2:          [INCOMPLETE][233] ([i915#5493]) -> [CRASH][234] ([i915#7331])
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13489/shard-dg2-1/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/shard-dg2-1/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html

  
  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#1623]: https://gitlab.freedesktop.org/drm/intel/issues/1623
  [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
  [i915#2017]: https://gitlab.freedesktop.org/drm/intel/issues/2017
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
  [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
  [i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
  [i915#3089]: https://gitlab.freedesktop.org/drm/intel/issues/3089
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
  [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
  [i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
  [i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936
  [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
  [i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
  [i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
  [i915#4936]: https://gitlab.freedesktop.org/drm/intel/issues/4936
  [i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
  [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
  [i915#5954]: https://gitlab.freedesktop.org/drm/intel/issues/5954
  [i915#6015]: https://gitlab.freedesktop.org/drm/intel/issues/6015
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6187]: https://gitlab.freedesktop.org/drm/intel/issues/6187
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6403]: https://gitlab.freedesktop.org/drm/intel/issues/6403
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
  [i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
  [i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059
  [i915#7061]: https://gitlab.freedesktop.org/drm/intel/issues/7061
  [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
  [i915#7162]: https://gitlab.freedesktop.org/drm/intel/issues/7162
  [i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173
  [i915#7331]: https://gitlab.freedesktop.org/drm/intel/issues/7331
  [i915#7392]: https://gitlab.freedesktop.org/drm/intel/issues/7392
  [i915#7484]: https://gitlab.freedesktop.org/drm/intel/issues/7484
  [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
  [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#7940]: https://gitlab.freedesktop.org/drm/intel/issues/7940
  [i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
  [i915#8131]: https://gitlab.freedesktop.org/drm/intel/issues/8131
  [i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
  [i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
  [i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
  [i915#8248]: https://gitlab.freedesktop.org/drm/intel/issues/8248
  [i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
  [i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
  [i915#8381]: https://gitlab.freedesktop.org/drm/intel/issues/8381
  [i915#8398]: https://gitlab.freedesktop.org/drm/intel/issues/8398
  [i915#8489]: https://gitlab.freedesktop.org/drm/intel/issues/8489
  [i915#8503]: https://gitlab.freedesktop.org/drm/intel/issues/8503
  [i915#8617]: https://gitlab.freedesktop.org/drm/intel/issues/8617
  [i915#8661]: https://gitlab.freedesktop.org/drm/intel/issues/8661
  [i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
  [i915#8691]: https://gitlab.freedesktop.org/drm/intel/issues/8691
  [i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
  [i915#8709]: https://gitlab.freedesktop.org/drm/intel/issues/8709
  [i915#8724]: https://gitlab.freedesktop.org/drm/intel/issues/8724
  [i915#8809]: https://gitlab.freedesktop.org/drm/intel/issues/8809
  [i915#8810]: https://gitlab.freedesktop.org/drm/intel/issues/8810
  [i915#8814]: https://gitlab.freedesktop.org/drm/intel/issues/8814
  [i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841


Build changes
-------------

  * Linux: CI_DRM_13489 -> Patchwork_120456v7

  CI-20190529: 20190529
  CI_DRM_13489: ba0acfd5bae2ff82ebfd23d50d4e80020fa9c4c1 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7420: 7420
  Patchwork_120456v7: ba0acfd5bae2ff82ebfd23d50d4e80020fa9c4c1 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v7/index.html

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