From: Thomas Gleixner <tglx@linutronix.de>
To: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>,
Dmitry Vyukov <dvyukov@google.com>
Cc: Peter Zijlstra <peterz@infradead.org>,
Dave Hansen <dave.hansen@linux.intel.com>,
Andy Lutomirski <luto@kernel.org>,
x86@kernel.org, Alexander Potapenko <glider@google.com>,
"H . J . Lu" <hjl.tools@gmail.com>,
Andi Kleen <ak@linux.intel.com>,
Rick Edgecombe <rick.p.edgecombe@intel.com>,
linux-mm@kvack.org, linux-kernel@vger.kernel.org
Subject: Re: [RFCv2 00/10] Linear Address Masking enabling
Date: Fri, 13 May 2022 01:21:37 +0200 [thread overview]
Message-ID: <87r14ytjzy.ffs@tglx> (raw)
In-Reply-To: <878rr6v985.ffs@tglx>
On Thu, May 12 2022 at 21:31, Thomas Gleixner wrote:
> On Thu, May 12 2022 at 19:56, Kirill A. Shutemov wrote:
>> On Thu, May 12, 2022 at 05:42:58PM +0200, Thomas Gleixner wrote:
>>> On Wed, May 11 2022 at 08:49, Peter Zijlstra wrote:
>>> > On Wed, May 11, 2022 at 05:27:40AM +0300, Kirill A. Shutemov wrote:
>>> > So aren't we creating a problem with LAM_U48 where programs relying on
>>> > it are of limited sustainability?
>>> >
>>> > Any such program simply *cannot* run on 5 level pagetables. Why do we
>>> > want to do this?
>>>
>>> More bits are better :)
>>>
>>> Seriously, I agree that restricting it to LAM57, which gives us 6 bits,
>>> makes a lot of sense _and_ makes the whole thing way simpler.
>>>
>>> So supporting both needs a truly good justification and a real world use
>>> case.
>>
>> I asked the question before[1]. Basically, more bits more better:
>>
>> For HWASAN #bits == detection probability.
>> For MarkUS #bits == exponential cost reduction
>
> What is MarkUS? It's not really helpful to provide acronyms which are
> not decodable.
>
>> I would really like to have only LAM_U57, but IIUC 6 bits is not always
>> enough.
>>
>> Dmitry, could you elaborate?
>>
>> [1] https://mobile.twitter.com/dvyukov/status/1342019823400837120
>
> I don't know whether he reacts on posting a link to his twitter
> account. I've CC'ed him now. Maybe that works better.
Duh. I should have looked at 'To:' and not only at 'Cc:'
Maybe someday I get used to this email thing.
Thanks,
tglx
next prev parent reply other threads:[~2022-05-12 23:21 UTC|newest]
Thread overview: 82+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-11 2:27 [RFCv2 00/10] Linear Address Masking enabling Kirill A. Shutemov
2022-05-11 2:27 ` [PATCH] x86: Implement Linear Address Masking support Kirill A. Shutemov
2022-05-12 13:01 ` David Laight
2022-05-12 14:07 ` Matthew Wilcox
2022-05-12 15:06 ` Thomas Gleixner
2022-05-12 15:33 ` David Laight
2022-05-12 14:35 ` Peter Zijlstra
2022-05-12 17:00 ` Kirill A. Shutemov
2022-05-11 2:27 ` [RFCv2 01/10] x86/mm: Fix CR3_ADDR_MASK Kirill A. Shutemov
2022-05-11 2:27 ` [RFCv2 02/10] x86: CPUID and CR3/CR4 flags for Linear Address Masking Kirill A. Shutemov
2022-05-11 2:27 ` [RFCv2 03/10] x86: Introduce userspace API to handle per-thread features Kirill A. Shutemov
2022-05-12 12:02 ` Thomas Gleixner
2022-05-12 12:04 ` [PATCH] x86/prctl: Remove pointless task argument Thomas Gleixner
2022-05-13 12:30 ` [tip: x86/cleanups] " tip-bot2 for Thomas Gleixner
2022-05-13 14:09 ` [RFCv2 03/10] x86: Introduce userspace API to handle per-thread features Alexander Potapenko
2022-05-13 17:34 ` Edgecombe, Rick P
2022-05-13 23:09 ` Kirill A. Shutemov
2022-05-13 23:50 ` Edgecombe, Rick P
2022-05-14 8:37 ` Thomas Gleixner
2022-05-14 23:06 ` Edgecombe, Rick P
2022-05-15 9:02 ` Thomas Gleixner
2022-05-15 18:24 ` Edgecombe, Rick P
2022-05-15 19:38 ` Thomas Gleixner
2022-05-15 22:01 ` Edgecombe, Rick P
2022-05-11 2:27 ` [RFCv2 04/10] x86/mm: Introduce X86_THREAD_LAM_U48 and X86_THREAD_LAM_U57 Kirill A. Shutemov
2022-05-11 7:02 ` Peter Zijlstra
2022-05-12 12:24 ` Thomas Gleixner
2022-05-12 14:37 ` Peter Zijlstra
2022-05-11 2:27 ` [RFCv2 05/10] x86/mm: Provide untagged_addr() helper Kirill A. Shutemov
2022-05-11 7:21 ` Peter Zijlstra
2022-05-11 7:45 ` Peter Zijlstra
2022-05-12 13:06 ` Thomas Gleixner
2022-05-12 14:23 ` Peter Zijlstra
2022-05-12 15:16 ` Thomas Gleixner
2022-05-12 23:14 ` Thomas Gleixner
2022-05-13 10:14 ` David Laight
2022-05-11 2:27 ` [RFCv2 06/10] x86/uaccess: Remove tags from the address before checking Kirill A. Shutemov
2022-05-12 13:02 ` David Laight
2022-05-11 2:27 ` [RFCv2 07/10] x86/mm: Handle tagged memory accesses from kernel threads Kirill A. Shutemov
2022-05-11 7:23 ` Peter Zijlstra
2022-05-12 13:30 ` Thomas Gleixner
2022-05-11 2:27 ` [RFCv2 08/10] x86/mm: Make LAM_U48 and mappings above 47-bits mutually exclusive Kirill A. Shutemov
2022-05-12 13:36 ` Thomas Gleixner
2022-05-13 23:22 ` Kirill A. Shutemov
2022-05-14 8:37 ` Thomas Gleixner
2022-05-18 8:43 ` Bharata B Rao
2022-05-18 17:08 ` Kirill A. Shutemov
2022-05-11 2:27 ` [RFCv2 09/10] x86/mm: Add userspace API to enable Linear Address Masking Kirill A. Shutemov
2022-05-11 7:26 ` Peter Zijlstra
2022-05-12 14:46 ` Thomas Gleixner
2022-05-11 14:15 ` H.J. Lu
2022-05-12 14:21 ` Thomas Gleixner
2022-05-11 2:27 ` [RFCv2 10/10] x86: Expose thread features status in /proc/$PID/arch_status Kirill A. Shutemov
2022-05-11 6:49 ` [RFCv2 00/10] Linear Address Masking enabling Peter Zijlstra
2022-05-12 15:42 ` Thomas Gleixner
2022-05-12 16:56 ` Kirill A. Shutemov
2022-05-12 19:31 ` Thomas Gleixner
2022-05-12 23:21 ` Thomas Gleixner [this message]
2022-05-12 17:22 ` Dave Hansen
2022-05-12 19:39 ` Thomas Gleixner
2022-05-12 21:24 ` Thomas Gleixner
2022-05-13 14:43 ` Matthew Wilcox
2022-05-13 22:59 ` Kirill A. Shutemov
2022-05-12 21:51 ` Dave Hansen
2022-05-12 22:10 ` H.J. Lu
2022-05-12 23:35 ` Thomas Gleixner
2022-05-13 0:08 ` H.J. Lu
2022-05-13 0:46 ` Dave Hansen
2022-05-13 1:27 ` Thomas Gleixner
2022-05-13 3:05 ` Dave Hansen
2022-05-13 8:28 ` Thomas Gleixner
2022-05-13 22:48 ` Kirill A. Shutemov
2022-05-13 9:14 ` Catalin Marinas
2022-05-13 9:26 ` Thomas Gleixner
2022-05-13 0:46 ` Thomas Gleixner
2022-05-13 11:07 ` Alexander Potapenko
2022-05-13 11:28 ` David Laight
2022-05-13 12:26 ` Alexander Potapenko
2022-05-13 14:26 ` David Laight
2022-05-13 15:28 ` Alexander Potapenko
2022-05-13 23:01 ` Kirill A. Shutemov
2022-05-14 10:00 ` Thomas Gleixner
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