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From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915/gt: Invalidate as we write the gen7 breadcrumb
Date: Wed, 13 Nov 2019 17:59:53 +0200	[thread overview]
Message-ID: <87r22b7ona.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <20191113151956.32242-1-chris@chris-wilson.co.uk>

Chris Wilson <chris@chris-wilson.co.uk> writes:

> Still the saga of the hsw live_blt incoherency continues. While it did
> seem that the invalidate before the breadcrumb had improved the mtbf,
> nevertheless live_blt still failed. Mika's next idea was to pull the
> invalidate-stall into the breadcrumb write itself.
>
> References: 860afa086841 ("drm/i915/gt: Flush gen7 even harder")
> References: https://bugs.freedesktop.org/show_bug.cgi?id=112147
> Testcase: igt/i915_selftest/live_blt
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_ring_submission.c | 9 +++------
>  1 file changed, 3 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index e8bee44add34..f25ceccb335e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -454,12 +454,8 @@ static u32 *gen7_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
>  	GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma);
>  	GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR);
>  
> -	*cs++ = (MI_FLUSH_DW | MI_INVALIDATE_TLB |
> -		 MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW);
> -	*cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
> -	*cs++ = 0;
> -
> -	*cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX;
> +	*cs++ = MI_FLUSH_DW | MI_INVALIDATE_TLB |
> +		MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX;
>  	*cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT;
>  	*cs++ = rq->fence.seqno;

In both would have been the shotgun approach. You favour sniper.

Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

>  
> @@ -474,6 +470,7 @@ static u32 *gen7_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
>  	*cs++ = 0;
>  
>  	*cs++ = MI_USER_INTERRUPT;
> +	*cs++ = MI_NOOP;
>  
>  	rq->tail = intel_ring_offset(rq, cs);
>  	assert_ring_tail_valid(rq->ring, rq->tail);
> -- 
> 2.24.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

WARNING: multiple messages have this Message-ID (diff)
From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915/gt: Invalidate as we write the gen7 breadcrumb
Date: Wed, 13 Nov 2019 17:59:53 +0200	[thread overview]
Message-ID: <87r22b7ona.fsf@gaia.fi.intel.com> (raw)
Message-ID: <20191113155953.xan4P4uU8emAIdMxaTbESPvCnDsTVsXASSQzkG_KYFM@z> (raw)
In-Reply-To: <20191113151956.32242-1-chris@chris-wilson.co.uk>

Chris Wilson <chris@chris-wilson.co.uk> writes:

> Still the saga of the hsw live_blt incoherency continues. While it did
> seem that the invalidate before the breadcrumb had improved the mtbf,
> nevertheless live_blt still failed. Mika's next idea was to pull the
> invalidate-stall into the breadcrumb write itself.
>
> References: 860afa086841 ("drm/i915/gt: Flush gen7 even harder")
> References: https://bugs.freedesktop.org/show_bug.cgi?id=112147
> Testcase: igt/i915_selftest/live_blt
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_ring_submission.c | 9 +++------
>  1 file changed, 3 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index e8bee44add34..f25ceccb335e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -454,12 +454,8 @@ static u32 *gen7_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
>  	GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma);
>  	GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR);
>  
> -	*cs++ = (MI_FLUSH_DW | MI_INVALIDATE_TLB |
> -		 MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW);
> -	*cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
> -	*cs++ = 0;
> -
> -	*cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX;
> +	*cs++ = MI_FLUSH_DW | MI_INVALIDATE_TLB |
> +		MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX;
>  	*cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT;
>  	*cs++ = rq->fence.seqno;

In both would have been the shotgun approach. You favour sniper.

Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

>  
> @@ -474,6 +470,7 @@ static u32 *gen7_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
>  	*cs++ = 0;
>  
>  	*cs++ = MI_USER_INTERRUPT;
> +	*cs++ = MI_NOOP;
>  
>  	rq->tail = intel_ring_offset(rq, cs);
>  	assert_ring_tail_valid(rq->ring, rq->tail);
> -- 
> 2.24.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2019-11-13 16:00 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-13 15:19 [PATCH] drm/i915/gt: Invalidate as we write the gen7 breadcrumb Chris Wilson
2019-11-13 15:19 ` [Intel-gfx] " Chris Wilson
2019-11-13 15:59 ` Mika Kuoppala [this message]
2019-11-13 15:59   ` Mika Kuoppala
2019-11-13 16:20   ` Chris Wilson
2019-11-13 16:20     ` [Intel-gfx] " Chris Wilson
2019-11-13 16:05 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2019-11-13 16:05   ` [Intel-gfx] " Patchwork
2019-11-13 16:31 ` ✓ Fi.CI.BAT: success " Patchwork
2019-11-13 16:31   ` [Intel-gfx] " Patchwork
2019-11-14  5:59 ` ✓ Fi.CI.IGT: " Patchwork
2019-11-14  5:59   ` [Intel-gfx] " Patchwork

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