* [PATCH] drm/i915: use the correct register when turning VDD off [not found] <bf13e81b904a37d94d83dd6c3b53a147719a3ead> @ 2013-10-31 14:44 ` Paulo Zanoni 2013-10-31 15:02 ` Jani Nikula 0 siblings, 1 reply; 2+ messages in thread From: Paulo Zanoni @ 2013-10-31 14:44 UTC (permalink / raw) To: intel-gfx; +Cc: Paulo Zanoni From: Paulo Zanoni <paulo.r.zanoni@intel.com> That explains why I was seeing 2 consecutive "Turning eDP VDD off" messages. Regression introduced by: commit bf13e81b904a37d94d83dd6c3b53a147719a3ead Author: Jani Nikula <jani.nikula@intel.com> Date: Fri Sep 6 07:40:05 2013 +0300 drm/i915: add support for per-pipe power sequencing on vlv Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 8db1fda..c8515bb 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1125,8 +1125,8 @@ static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp) pp = ironlake_get_pp_control(intel_dp); pp &= ~EDP_FORCE_VDD; - pp_stat_reg = _pp_ctrl_reg(intel_dp); - pp_ctrl_reg = _pp_stat_reg(intel_dp); + pp_ctrl_reg = _pp_ctrl_reg(intel_dp); + pp_stat_reg = _pp_stat_reg(intel_dp); I915_WRITE(pp_ctrl_reg, pp); POSTING_READ(pp_ctrl_reg); -- 1.8.3.1 ^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] drm/i915: use the correct register when turning VDD off 2013-10-31 14:44 ` [PATCH] drm/i915: use the correct register when turning VDD off Paulo Zanoni @ 2013-10-31 15:02 ` Jani Nikula 0 siblings, 0 replies; 2+ messages in thread From: Jani Nikula @ 2013-10-31 15:02 UTC (permalink / raw) To: Paulo Zanoni, intel-gfx; +Cc: Paulo Zanoni On Thu, 31 Oct 2013, Paulo Zanoni <przanoni@gmail.com> wrote: > From: Paulo Zanoni <paulo.r.zanoni@intel.com> > > That explains why I was seeing 2 consecutive "Turning eDP VDD off" > messages. > > Regression introduced by: > commit bf13e81b904a37d94d83dd6c3b53a147719a3ead > Author: Jani Nikula <jani.nikula@intel.com> > Date: Fri Sep 6 07:40:05 2013 +0300 > drm/i915: add support for per-pipe power sequencing on vlv > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Good catch, Reviewed-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/intel_dp.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 8db1fda..c8515bb 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -1125,8 +1125,8 @@ static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp) > pp = ironlake_get_pp_control(intel_dp); > pp &= ~EDP_FORCE_VDD; > > - pp_stat_reg = _pp_ctrl_reg(intel_dp); > - pp_ctrl_reg = _pp_stat_reg(intel_dp); > + pp_ctrl_reg = _pp_ctrl_reg(intel_dp); > + pp_stat_reg = _pp_stat_reg(intel_dp); > > I915_WRITE(pp_ctrl_reg, pp); > POSTING_READ(pp_ctrl_reg); > -- > 1.8.3.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Technology Center ^ permalink raw reply [flat|nested] 2+ messages in thread
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2013-10-31 14:44 ` [PATCH] drm/i915: use the correct register when turning VDD off Paulo Zanoni
2013-10-31 15:02 ` Jani Nikula
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