From: "Alex Bennée" <alex.bennee@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, qemu-stable@nongnu.org
Subject: Re: [PATCH 1/3] target/arm: SVE2 FMAXP, FMINP must honour AH=1
Date: Thu, 21 May 2026 15:45:01 +0100 [thread overview]
Message-ID: <87se7kom8i.fsf@draig.linaro.org> (raw)
In-Reply-To: <20260521122913.1565011-2-peter.maydell@linaro.org> (Peter Maydell's message of "Thu, 21 May 2026 13:29:11 +0100")
Peter Maydell <peter.maydell@linaro.org> writes:
> The behaviour of floating-point maximum and minimum insns has
> some odd special cases when FPCR.AH=1. We get this right in most
> places (for instance, the ASIMD FMAXP, FMINP) but forgot about
> it for the SVE2 versions of FMAXP and FMINP.
>
> Cc: qemu-stable@nongnu.org
> Fixes: 384433e70983 ("target/arm: Implement FPCR.AH semantics for FMINP and FMAXP")
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
next prev parent reply other threads:[~2026-05-21 14:45 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-21 12:29 [PATCH 0/3] target/arm: Fix some FEAT_AFP corner cases Peter Maydell
2026-05-21 12:29 ` [PATCH 1/3] target/arm: SVE2 FMAXP, FMINP must honour AH=1 Peter Maydell
2026-05-21 14:45 ` Alex Bennée [this message]
2026-05-21 12:29 ` [PATCH 2/3] target/arm: Use FPST_A64_F16 for SVE FCVTLT_hs Peter Maydell
2026-05-21 14:55 ` Alex Bennée
2026-05-21 15:21 ` Peter Maydell
2026-05-21 17:50 ` Alex Bennée
2026-05-22 21:52 ` Richard Henderson
2026-05-21 12:29 ` [PATCH 3/3] target/arm: Set correct fp flags for FLOGB when FPCR.AH = 1 Peter Maydell
2026-05-21 15:03 ` Alex Bennée
2026-05-22 21:54 ` Richard Henderson
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