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* [PATCHv2] drm/i915/dp: Guarantee a minimum HBlank time
@ 2024-10-01  7:43 Arun R Murthy
  2024-10-01  8:00 ` ✓ CI.Patch_applied: success for drm/i915/dp: Guarantee a minimum HBlank time (rev2) Patchwork
                   ` (11 more replies)
  0 siblings, 12 replies; 16+ messages in thread
From: Arun R Murthy @ 2024-10-01  7:43 UTC (permalink / raw)
  To: intel-xe, intel-gfx; +Cc: Arun R Murthy

Mandate a minimum Hblank symbol cycle count between BS and BE in 8b/10b
MST and 12b/132b mode.
Spec: DP2.1a

v2: Affine calculation/updation of min HBlank to dp_mst (Jani)

Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  2 ++
 drivers/gpu/drm/i915/display/intel_dp_mst.c   | 30 +++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h               |  4 +++
 3 files changed, 36 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 17fc21f6ae36..5f151ad9b878 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1770,6 +1770,8 @@ struct intel_dp {
 
 	u8 alpm_dpcd;
 
+	u32 min_hblank;
+
 	struct {
 		unsigned long mask;
 	} quirks;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 4765bda154c1..45c8be7cd7b3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -156,6 +156,30 @@ static int intel_dp_mst_calc_pbn(int pixel_clock, int bpp_x16, int bw_overhead)
 	return DIV_ROUND_UP(effective_data_rate * 64, 54 * 1000);
 }
 
+static void intel_dp_mst_compute_min_hblank(struct intel_crtc_state *crtc_state,
+					    struct intel_connector *intel_connector,
+					    int bpp_x16)
+{
+	struct intel_encoder *intel_encoder = intel_connector->encoder;
+	struct intel_dp_mst_encoder *intel_mst = enc_to_mst(intel_encoder);
+	struct intel_dp *intel_dp = &intel_mst->primary->dp;
+	struct intel_display *intel_display = to_intel_display(intel_encoder);
+	const struct drm_display_mode *adjusted_mode =
+					&crtc_state->hw.adjusted_mode;
+	u32 symbol_size = intel_dp_is_uhbr(crtc_state) ? 32 : 8;
+	u32 hblank;
+
+	if (DISPLAY_VER(intel_display) < 20)
+		return;
+
+	/* Calculate min Hblank Link Layer Symbol Cycle Count for 8b/10b MST & 128b/132b */
+	hblank = DIV_ROUND_UP((DIV_ROUND_UP(adjusted_mode->htotal - adjusted_mode->hdisplay, 4) * bpp_x16), symbol_size);
+	if (intel_dp_is_uhbr(crtc_state))
+		intel_dp->min_hblank = hblank > 5 ? hblank : 5;
+	else
+		intel_dp->min_hblank = hblank > 3 ? hblank : 3;
+}
+
 static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
 						struct intel_crtc_state *crtc_state,
 						int max_bpp,
@@ -228,6 +252,8 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
 					 link_bpp_x16,
 					 &crtc_state->dp_m_n);
 
+		intel_dp_mst_compute_min_hblank(crtc_state, connector, link_bpp_x16);
+
 		/*
 		 * The TU size programmed to the HW determines which slots in
 		 * an MTP frame are used for this stream, which needs to match
@@ -1274,6 +1300,10 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
 			       TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff));
 	}
 
+	if (DISPLAY_VER(dev_priv) >= 20)
+		intel_de_write(dev_priv, DP_MIN_HBLANK_CTL(dev_priv, trans),
+			       intel_dp->min_hblank);
+
 	enable_bs_jitter_was(pipe_config);
 
 	intel_ddi_enable_transcoder_func(encoder, pipe_config);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7396fc630e29..b321d136e1b0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1138,6 +1138,10 @@
 #define _TRANS_MULT_B		0x6102c
 #define TRANS_MULT(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A)
 
+#define _DP_MIN_HBLANK_CTL_A	0x600ac
+#define _DP_MIN_HBLANK_CTL_B	0x610ac
+#define DP_MIN_HBLANK_CTL(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _DP_MIN_HBLANK_CTL_A)
+
 /* VGA port control */
 #define ADPA			_MMIO(0x61100)
 #define PCH_ADPA                _MMIO(0xe1100)
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 16+ messages in thread
* Re: [PATCHv2] drm/i915/dp: Guarantee a minimum HBlank time
@ 2024-10-02  3:11 kernel test robot
  0 siblings, 0 replies; 16+ messages in thread
From: kernel test robot @ 2024-10-02  3:11 UTC (permalink / raw)
  To: oe-kbuild; +Cc: lkp, Julia Lawall

BCC: lkp@intel.com
CC: oe-kbuild-all@lists.linux.dev
In-Reply-To: <20241001074348.2193502-1-arun.r.murthy@intel.com>
References: <20241001074348.2193502-1-arun.r.murthy@intel.com>
TO: Arun R Murthy <arun.r.murthy@intel.com>
TO: intel-xe@lists.freedesktop.org
TO: intel-gfx@lists.freedesktop.org
CC: Arun R Murthy <arun.r.murthy@intel.com>

Hi Arun,

kernel test robot noticed the following build warnings:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on linus/master v6.12-rc1 next-20241001]
[cannot apply to drm-intel/for-linux-next-fixes drm-tip/drm-tip]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Arun-R-Murthy/drm-i915-dp-Guarantee-a-minimum-HBlank-time/20241001-155536
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
patch link:    https://lore.kernel.org/r/20241001074348.2193502-1-arun.r.murthy%40intel.com
patch subject: [PATCHv2] drm/i915/dp: Guarantee a minimum HBlank time
:::::: branch date: 19 hours ago
:::::: commit date: 19 hours ago
config: x86_64-randconfig-104-20241002 (https://download.01.org/0day-ci/archive/20241002/202410021032.BpJez1ja-lkp@intel.com/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Julia Lawall <julia.lawall@inria.fr>
| Closes: https://lore.kernel.org/r/202410021032.BpJez1ja-lkp@intel.com/

cocci warnings: (new ones prefixed by >>)
>> drivers/gpu/drm/i915/display/intel_dp_mst.c:178:32-33: WARNING opportunity for max()
   drivers/gpu/drm/i915/display/intel_dp_mst.c:180:32-33: WARNING opportunity for max()

vim +178 drivers/gpu/drm/i915/display/intel_dp_mst.c

9069b77545ca5a Imre Deak     2023-11-17  158  
9ffe2a8e0d3097 Arun R Murthy 2024-10-01  159  static void intel_dp_mst_compute_min_hblank(struct intel_crtc_state *crtc_state,
9ffe2a8e0d3097 Arun R Murthy 2024-10-01  160  					    struct intel_connector *intel_connector,
9ffe2a8e0d3097 Arun R Murthy 2024-10-01  161  					    int bpp_x16)
9ffe2a8e0d3097 Arun R Murthy 2024-10-01  162  {
9ffe2a8e0d3097 Arun R Murthy 2024-10-01  163  	struct intel_encoder *intel_encoder = intel_connector->encoder;
9ffe2a8e0d3097 Arun R Murthy 2024-10-01  164  	struct intel_dp_mst_encoder *intel_mst = enc_to_mst(intel_encoder);
9ffe2a8e0d3097 Arun R Murthy 2024-10-01  165  	struct intel_dp *intel_dp = &intel_mst->primary->dp;
9ffe2a8e0d3097 Arun R Murthy 2024-10-01  166  	struct intel_display *intel_display = to_intel_display(intel_encoder);
9ffe2a8e0d3097 Arun R Murthy 2024-10-01  167  	const struct drm_display_mode *adjusted_mode =
9ffe2a8e0d3097 Arun R Murthy 2024-10-01  168  					&crtc_state->hw.adjusted_mode;
9ffe2a8e0d3097 Arun R Murthy 2024-10-01  169  	u32 symbol_size = intel_dp_is_uhbr(crtc_state) ? 32 : 8;
9ffe2a8e0d3097 Arun R Murthy 2024-10-01  170  	u32 hblank;
9ffe2a8e0d3097 Arun R Murthy 2024-10-01  171  
9ffe2a8e0d3097 Arun R Murthy 2024-10-01  172  	if (DISPLAY_VER(intel_display) < 20)
9ffe2a8e0d3097 Arun R Murthy 2024-10-01  173  		return;
9ffe2a8e0d3097 Arun R Murthy 2024-10-01  174  
9ffe2a8e0d3097 Arun R Murthy 2024-10-01  175  	/* Calculate min Hblank Link Layer Symbol Cycle Count for 8b/10b MST & 128b/132b */
9ffe2a8e0d3097 Arun R Murthy 2024-10-01  176  	hblank = DIV_ROUND_UP((DIV_ROUND_UP(adjusted_mode->htotal - adjusted_mode->hdisplay, 4) * bpp_x16), symbol_size);
9ffe2a8e0d3097 Arun R Murthy 2024-10-01  177  	if (intel_dp_is_uhbr(crtc_state))
9ffe2a8e0d3097 Arun R Murthy 2024-10-01 @178  		intel_dp->min_hblank = hblank > 5 ? hblank : 5;
9ffe2a8e0d3097 Arun R Murthy 2024-10-01  179  	else
9ffe2a8e0d3097 Arun R Murthy 2024-10-01  180  		intel_dp->min_hblank = hblank > 3 ? hblank : 3;
9ffe2a8e0d3097 Arun R Murthy 2024-10-01  181  }
9ffe2a8e0d3097 Arun R Murthy 2024-10-01  182  

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

^ permalink raw reply	[flat|nested] 16+ messages in thread
end of thread, other threads:[~2024-10-22  8:13 UTC | newest]

Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-10-01  7:43 [PATCHv2] drm/i915/dp: Guarantee a minimum HBlank time Arun R Murthy
2024-10-01  8:00 ` ✓ CI.Patch_applied: success for drm/i915/dp: Guarantee a minimum HBlank time (rev2) Patchwork
2024-10-01  8:00 ` ✗ CI.checkpatch: warning " Patchwork
2024-10-01  8:01 ` ✓ CI.KUnit: success " Patchwork
2024-10-01  8:12 ` ✓ CI.Build: " Patchwork
2024-10-01  8:15 ` ✓ CI.Hooks: " Patchwork
2024-10-01  8:16 ` ✗ CI.checksparse: warning " Patchwork
2024-10-01  8:41 ` ✓ CI.BAT: success " Patchwork
2024-10-01 16:05 ` ✗ CI.FULL: failure " Patchwork
2024-10-01 23:31 ` ✗ Fi.CI.CHECKPATCH: warning " Patchwork
2024-10-01 23:40 ` ✓ Fi.CI.BAT: success " Patchwork
2024-10-02 23:01 ` ✗ Fi.CI.IGT: failure " Patchwork
2024-10-22  7:33 ` [PATCHv2] drm/i915/dp: Guarantee a minimum HBlank time Jani Nikula
2024-10-22  7:55   ` Murthy, Arun R
2024-10-22  8:12     ` Jani Nikula
  -- strict thread matches above, loose matches on Subject: below --
2024-10-02  3:11 kernel test robot

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