Re: [PATCH] drm/i915: Implement Dbuf overlap detection feature starting from LNL

[Jani Nikula <jani.nikula@linux.intel.com>]

On Mon, 05 Aug 2024, Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> wrote:
> From LNL onwards there is a new hardware feature, which
> allows to detect if the driver wrongly allocated DBuf
> entries and they happen to overlap. If enabled this will
> cause a specific interrupt to occur.
> We now handle it in the driver, by writing correspondent
> error message to kernel log.
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_device.c | 6 ++++++
>  drivers/gpu/drm/i915/display/intel_display_device.h | 2 ++
>  drivers/gpu/drm/i915/display/intel_display_irq.c    | 7 +++++++
>  drivers/gpu/drm/i915/i915_reg.h                     | 2 ++
>  4 files changed, 17 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
> index dd7dce4b0e7a..b4f979bc59cf 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -1457,6 +1457,12 @@ static void __intel_display_device_info_runtime_init(struct drm_i915_private *i9
>  		if (IS_DISPLAY_VER(i915, 10, 12) &&
>  		    (dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE))
>  			display_runtime->has_dsc = 0;
> +
> +		if (DISPLAY_VER(i915) >= 20 &&
> +		    !(dfsm & XE2LPD_DFSM_DBUF_OVERLAP_DISABLE))
> +			display_runtime->has_dbuf_overlap_detection = 1;
> +		else
> +			display_runtime->has_dbuf_overlap_detection = 0;

I'd initialize this to true in the __runtime_defaults init for LNL+, and
only set it to false when dfsm says so. Similar to has_dsc above.

And nitpick, please use true/false not 1/0 to initialize bool
values. (Even though a bunch of code does use 1/0...)

BR,
Jani.

>  	}
>  
>  	if (DISPLAY_VER(i915) >= 20) {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> index 13453ea4daea..6b94ccd381bc 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -122,6 +122,7 @@ enum intel_display_subplatform {
>  #define HAS_CDCLK_SQUASH(i915)		(DISPLAY_INFO(i915)->has_cdclk_squash)
>  #define HAS_CUR_FBC(i915)		(!HAS_GMCH(i915) && IS_DISPLAY_VER(i915, 7, 13))
>  #define HAS_D12_PLANE_MINIMIZATION(i915) (IS_ROCKETLAKE(i915) || IS_ALDERLAKE_S(i915))
> +#define HAS_DBUF_OVERLAP_DETECTION(__i915) (DISPLAY_RUNTIME_INFO(__i915)->has_dbuf_overlap_detection)
>  #define HAS_DDI(i915)			(DISPLAY_INFO(i915)->has_ddi)
>  #define HAS_DISPLAY(i915)		(DISPLAY_RUNTIME_INFO(i915)->pipe_mask != 0)
>  #define HAS_DMC(i915)			(DISPLAY_RUNTIME_INFO(i915)->has_dmc)
> @@ -216,6 +217,7 @@ struct intel_display_runtime_info {
>  	bool has_hdcp;
>  	bool has_dmc;
>  	bool has_dsc;
> +	bool has_dbuf_overlap_detection;
>  };
>  
>  struct intel_display_device_info {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index 5219ba295c74..e0f1b54d9175 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -896,6 +896,13 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
>  {
>  	bool found = false;
>  
> +	if (HAS_DBUF_OVERLAP_DETECTION(dev_priv)) {
> +		if (iir & XE2LPD_DBUF_OVERLAP_DETECTED) {
> +			drm_warn(&dev_priv->drm,  "DBuf overlap detected\n");
> +			found = true;
> +		}
> +	}
> +
>  	if (DISPLAY_VER(dev_priv) >= 14) {
>  		if (iir & (XELPDP_PMDEMAND_RSP |
>  			   XELPDP_PMDEMAND_RSPTOUT_ERR)) {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0e3d79227e3c..1e8b04d2f728 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2578,6 +2578,7 @@
>  #define  GEN8_DE_MISC_GSE		REG_BIT(27)
>  #define  GEN8_DE_EDP_PSR		REG_BIT(19)
>  #define  XELPDP_PMDEMAND_RSP		REG_BIT(3)
> +#define  XE2LPD_DBUF_OVERLAP_DETECTED	REG_BIT(1)
>  
>  #define GEN8_PCU_ISR _MMIO(0x444e0)
>  #define GEN8_PCU_IMR _MMIO(0x444e4)
> @@ -2863,6 +2864,7 @@
>  #define   SKL_DFSM_PIPE_C_DISABLE	(1 << 28)
>  #define   TGL_DFSM_PIPE_D_DISABLE	(1 << 22)
>  #define   GLK_DFSM_DISPLAY_DSC_DISABLE	(1 << 7)
> +#define   XE2LPD_DFSM_DBUF_OVERLAP_DISABLE	(1 << 3)
>  
>  #define XE2LPD_DE_CAP			_MMIO(0x41100)
>  #define   XE2LPD_DE_CAP_3DLUT_MASK	REG_GENMASK(31, 30)

-- 
Jani Nikula, Intel