From: "Dixit, Ashutosh" <ashutosh.dixit@intel.com>
To: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 2/4] drm/i915/mtl: Modify CAGF functions for MTL
Date: Wed, 19 Oct 2022 16:43:01 -0700 [thread overview]
Message-ID: <87sfjjidmi.wl-ashutosh.dixit@intel.com> (raw)
In-Reply-To: <Y1AQhT4n4lYUUh9z@intel.com>
On Wed, 19 Oct 2022 07:58:13 -0700, Rodrigo Vivi wrote:
>
> On Tue, Oct 18, 2022 at 10:20:41PM -0700, Ashutosh Dixit wrote:
> > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> > index df21258976d86..5a743ae4dd11e 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> > @@ -2093,7 +2093,9 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
> > struct drm_i915_private *i915 = rps_to_i915(rps);
> > u32 cagf;
> >
> > - if (GRAPHICS_VER(i915) >= 12)
> > + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
> > + cagf = rpstat & MTL_CAGF_MASK;
>
> I believe we should advocate more the use of the REG_FIELD_GET
>
> cagf = REG_FIELD_GET(MTL_CAGF_MASK, rpstat);
>
> > + else if (GRAPHICS_VER(i915) >= 12)
> > cagf = (rpstat & GEN12_CAGF_MASK) >> GEN12_CAGF_SHIFT;
>
> cagf = REG_FIELD_GET(GEN12_CAGF_MASK, rpstat);
> // witht the proper REG_GENAMSK usage on the gen12_cagf_mask...
>
> > else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> > cagf = (rpstat >> 8) & 0xff;
>
> #define RPE_MASK REG_GENMASK(15, 8)
> cagf = REG_FIELD_GET(RPE_MASK, rpstat)
All these are now converted to REG_FIELD_GET in series version v8.
> > @@ -2116,7 +2118,13 @@ static u32 read_cagf(struct intel_rps *rps)
> > struct intel_uncore *uncore = rps_to_uncore(rps);
> ^
>
> > u32 freq;
> >
> > - if (GRAPHICS_VER(i915) >= 12) {
> > + /*
> > + * For Gen12+ reading freq from HW does not need a forcewake and
> > + * registers will return 0 freq when GT is in RC6
> > + */
> > + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
> > + freq = intel_uncore_read(rps_to_gt(rps)->uncore, MTL_MIRROR_TARGET_WP1);
>
> here we should use directly the local uncore already declared above with
> the same helper... and consistent with the following elses...
Fixed.
>
> > + } else if (GRAPHICS_VER(i915) >= 12) {
> > freq = intel_uncore_read(uncore, GEN12_RPSTAT1);
> > } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
> > vlv_punit_get(i915);
> > --
> > 2.38.0
> >
Thanks.
--
Ashutosh
WARNING: multiple messages have this Message-ID (diff)
From: "Dixit, Ashutosh" <ashutosh.dixit@intel.com>
To: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Anshuman Gupta <anshuman.gupta@intel.com>,
intel-gfx@lists.freedesktop.org,
Badal Nilawar <badal.nilawar@intel.com>,
dri-devel@lists.freedesktop.org
Subject: Re: [PATCH 2/4] drm/i915/mtl: Modify CAGF functions for MTL
Date: Wed, 19 Oct 2022 16:43:01 -0700 [thread overview]
Message-ID: <87sfjjidmi.wl-ashutosh.dixit@intel.com> (raw)
In-Reply-To: <Y1AQhT4n4lYUUh9z@intel.com>
On Wed, 19 Oct 2022 07:58:13 -0700, Rodrigo Vivi wrote:
>
> On Tue, Oct 18, 2022 at 10:20:41PM -0700, Ashutosh Dixit wrote:
> > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> > index df21258976d86..5a743ae4dd11e 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> > @@ -2093,7 +2093,9 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
> > struct drm_i915_private *i915 = rps_to_i915(rps);
> > u32 cagf;
> >
> > - if (GRAPHICS_VER(i915) >= 12)
> > + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
> > + cagf = rpstat & MTL_CAGF_MASK;
>
> I believe we should advocate more the use of the REG_FIELD_GET
>
> cagf = REG_FIELD_GET(MTL_CAGF_MASK, rpstat);
>
> > + else if (GRAPHICS_VER(i915) >= 12)
> > cagf = (rpstat & GEN12_CAGF_MASK) >> GEN12_CAGF_SHIFT;
>
> cagf = REG_FIELD_GET(GEN12_CAGF_MASK, rpstat);
> // witht the proper REG_GENAMSK usage on the gen12_cagf_mask...
>
> > else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> > cagf = (rpstat >> 8) & 0xff;
>
> #define RPE_MASK REG_GENMASK(15, 8)
> cagf = REG_FIELD_GET(RPE_MASK, rpstat)
All these are now converted to REG_FIELD_GET in series version v8.
> > @@ -2116,7 +2118,13 @@ static u32 read_cagf(struct intel_rps *rps)
> > struct intel_uncore *uncore = rps_to_uncore(rps);
> ^
>
> > u32 freq;
> >
> > - if (GRAPHICS_VER(i915) >= 12) {
> > + /*
> > + * For Gen12+ reading freq from HW does not need a forcewake and
> > + * registers will return 0 freq when GT is in RC6
> > + */
> > + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
> > + freq = intel_uncore_read(rps_to_gt(rps)->uncore, MTL_MIRROR_TARGET_WP1);
>
> here we should use directly the local uncore already declared above with
> the same helper... and consistent with the following elses...
Fixed.
>
> > + } else if (GRAPHICS_VER(i915) >= 12) {
> > freq = intel_uncore_read(uncore, GEN12_RPSTAT1);
> > } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
> > vlv_punit_get(i915);
> > --
> > 2.38.0
> >
Thanks.
--
Ashutosh
next prev parent reply other threads:[~2022-10-19 23:43 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-19 5:20 [Intel-gfx] [PATCH 0/4] i915: CAGF and RC6 changes for MTL Ashutosh Dixit
2022-10-19 5:20 ` Ashutosh Dixit
2022-10-19 5:20 ` [Intel-gfx] [PATCH 1/4] drm/i915: Use GEN12_RPSTAT register for GT freq Ashutosh Dixit
2022-10-19 5:20 ` Ashutosh Dixit
2022-10-19 15:06 ` [Intel-gfx] " Rodrigo Vivi
2022-10-19 15:06 ` Rodrigo Vivi
2022-10-19 23:42 ` [Intel-gfx] " Dixit, Ashutosh
2022-10-19 23:42 ` Dixit, Ashutosh
2022-10-19 5:20 ` [Intel-gfx] [PATCH 2/4] drm/i915/mtl: Modify CAGF functions for MTL Ashutosh Dixit
2022-10-19 5:20 ` Ashutosh Dixit
2022-10-19 14:58 ` [Intel-gfx] " Rodrigo Vivi
2022-10-19 14:58 ` Rodrigo Vivi
2022-10-19 23:43 ` Dixit, Ashutosh [this message]
2022-10-19 23:43 ` Dixit, Ashutosh
2022-10-19 5:20 ` [Intel-gfx] [PATCH 3/4] drm/i915/gt: Use RC6 residency types as arguments to residency functions Ashutosh Dixit
2022-10-19 5:20 ` Ashutosh Dixit
2022-10-19 7:51 ` [Intel-gfx] " Jani Nikula
2022-10-19 7:51 ` Jani Nikula
2022-10-19 23:40 ` [Intel-gfx] " Dixit, Ashutosh
2022-10-19 23:40 ` Dixit, Ashutosh
2022-10-19 5:20 ` [Intel-gfx] [PATCH 4/4] drm/i915/mtl: C6 residency and C state type for MTL SAMedia Ashutosh Dixit
2022-10-19 5:20 ` Ashutosh Dixit
2022-10-19 5:52 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915: CAGF and RC6 changes for MTL (rev6) Patchwork
2022-10-19 6:08 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-10-19 12:11 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for i915: CAGF and RC6 changes for MTL (rev7) Patchwork
2022-10-19 13:43 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for i915: CAGF and RC6 changes for MTL (rev6) Patchwork
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