From: "Alex Bennée" <alex.bennee@linaro.org>
To: Idan Horowitz <idan.horowitz@gmail.com>
Cc: qemu-arm@nongnu.org
Subject: Re: DSB does not seem to wait for TLBI completion
Date: Wed, 01 Dec 2021 16:13:38 +0000 [thread overview]
Message-ID: <87sfvcxpvb.fsf@linaro.org> (raw)
In-Reply-To: <CA+4MfEKrrsACvQKBimpkQt6r0H2cbJ9EaYCSFgZcx1Bqr20=Sg@mail.gmail.com>
Idan Horowitz <idan.horowitz@gmail.com> writes:
> Idan Horowitz <idan.horowitz@gmail.com> wrote:
>>
>> I am actually running in icount mode (-icount shift=10 specifically),
>> and adding the translation block exit or just using ISB directly does
>> not seem to affect it unfortunately.
>>
>> Idan Horowitz
>
> After a lot of testing I had the thought of trying this without
> icount, and it seems to work fine without it, so the issue is somehow
> related to icount being enabled.
That's is weird because icount basically ensures round robin scheduling
of each vCPU in turn. I wonder if there is a pending flush when the vCPU
switches?
We really need a reliable reproducer for this to investigate further.
>
> Idan Horowitz
--
Alex Bennée
next prev parent reply other threads:[~2021-12-01 16:16 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-18 15:19 DSB does not seem to wait for TLBI completion Idan Horowitz
2021-11-18 17:01 ` Alex Bennée
2021-11-21 7:52 ` Idan Horowitz
2021-12-01 15:40 ` Idan Horowitz
2021-12-01 16:13 ` Alex Bennée [this message]
2021-12-29 13:23 ` Idan Horowitz
2021-11-18 17:32 ` Peter Maydell
2021-11-18 18:50 ` Alex Bennée
2021-11-21 7:57 ` Idan Horowitz
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