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From: "Aneesh Kumar K.V" <aneesh.kumar-23VcF4HTsmIX0ybBhKVfKdBPR1lH4CV8@public.gmane.org>
To: Benjamin Herrenschmidt
	<benh-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r@public.gmane.org>,
	Jason Gunthorpe
	<jgunthorpe-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
Cc: paulus-eUNUBHrolfbYtjvyW6yDsg@public.gmane.org,
	mpe-Gsx/Oe8HsFggBc27wqDAHg@public.gmane.org,
	linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org,
	Mike Marciniszyn
	<infinipath-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>,
	Doug Ledford <dledford-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>,
	Sean Hefty <sean.hefty-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>,
	Hal Rosenstock
	<hal.rosenstock-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
	linux-rdma-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH V2] powerpc/infiniband: Use cache inhibitted and guarded mapping on powerpc
Date: Sun, 24 Apr 2016 23:03:10 +0530	[thread overview]
Message-ID: <87shyanc89.fsf@skywalker.in.ibm.com> (raw)
In-Reply-To: <1461399949.3135.52.camel-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r@public.gmane.org>

Benjamin Herrenschmidt <benh-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r@public.gmane.org> writes:

> On Fri, 2016-04-22 at 10:09 -0600, Jason Gunthorpe wrote:
>> On Fri, Apr 22, 2016 at 08:47:56AM +1000, Benjamin Herrenschmidt
>> wrote:
>> > 
>> > On Wed, 2016-04-20 at 03:58 -0400, Aneesh Kumar K.V wrote:
>> > > 
>> > > The driver was requesting for a writethrough mapping. But with
>> > > thoses
>> > > flags we will end up with a SAO mapping because we now have
>> > > memory
>> > > conherence always enabled. ie, the existing mapping will end up
>> > > with
>> > > a WIMG value 0b1110 which is Strong Access Order.
>> > > 
>> > > Update this to use cache inhibitted guarded mapping
>> > Why guarded ? If it's performance sensitive (and the driver has
>> > appropriate barriers where needed), you will get write combining
>> > without guarded, you won't with it.
>> This driver uses uncached write combining on x86
>
> Right so if you want something similar on power, use the _wc variant,
> and make sure you have the appropriate barriers when you need to
> break combining.
>
> Cheers,
> Ben.

The code after change looks like below

#if defined(__powerpc__)
	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
#endif

	/*
	 * don't allow them to later change to readable with mprotect (for when
	 * not initially mapped readable, as is normally the case)
	 */
	vma->vm_flags &= ~VM_MAYREAD;
	vma->vm_flags |= VM_DONTCOPY | VM_DONTEXPAND;

	/* We used PAT if wc_cookie == 0 */
	if (!dd->wc_cookie)
		vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);

So it uses pgprot_noncached_wc if (!dd->wc_cookie). Hence I was thinking
it needs more stricter mapping otherwise.

-aneesh

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WARNING: multiple messages have this Message-ID (diff)
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
To: Benjamin Herrenschmidt <benh@kernel.crashing.org>,
	Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: paulus@samba.org, mpe@ellerman.id.au,
	linuxppc-dev@lists.ozlabs.org,
	Mike Marciniszyn <infinipath@intel.com>,
	Doug Ledford <dledford@redhat.com>,
	Sean Hefty <sean.hefty@intel.com>,
	Hal Rosenstock <hal.rosenstock@gmail.com>,
	linux-rdma@vger.kernel.org
Subject: Re: [PATCH V2] powerpc/infiniband: Use cache inhibitted and guarded mapping on powerpc
Date: Sun, 24 Apr 2016 23:03:10 +0530	[thread overview]
Message-ID: <87shyanc89.fsf@skywalker.in.ibm.com> (raw)
In-Reply-To: <1461399949.3135.52.camel@kernel.crashing.org>

Benjamin Herrenschmidt <benh@kernel.crashing.org> writes:

> On Fri, 2016-04-22 at 10:09 -0600, Jason Gunthorpe wrote:
>> On Fri, Apr 22, 2016 at 08:47:56AM +1000, Benjamin Herrenschmidt
>> wrote:
>> > 
>> > On Wed, 2016-04-20 at 03:58 -0400, Aneesh Kumar K.V wrote:
>> > > 
>> > > The driver was requesting for a writethrough mapping. But with
>> > > thoses
>> > > flags we will end up with a SAO mapping because we now have
>> > > memory
>> > > conherence always enabled. ie, the existing mapping will end up
>> > > with
>> > > a WIMG value 0b1110 which is Strong Access Order.
>> > > 
>> > > Update this to use cache inhibitted guarded mapping
>> > Why guarded ? If it's performance sensitive (and the driver has
>> > appropriate barriers where needed), you will get write combining
>> > without guarded, you won't with it.
>> This driver uses uncached write combining on x86
>
> Right so if you want something similar on power, use the _wc variant,
> and make sure you have the appropriate barriers when you need to
> break combining.
>
> Cheers,
> Ben.

The code after change looks like below

#if defined(__powerpc__)
	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
#endif

	/*
	 * don't allow them to later change to readable with mprotect (for when
	 * not initially mapped readable, as is normally the case)
	 */
	vma->vm_flags &= ~VM_MAYREAD;
	vma->vm_flags |= VM_DONTCOPY | VM_DONTEXPAND;

	/* We used PAT if wc_cookie == 0 */
	if (!dd->wc_cookie)
		vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);

So it uses pgprot_noncached_wc if (!dd->wc_cookie). Hence I was thinking
it needs more stricter mapping otherwise.

-aneesh

  parent reply	other threads:[~2016-04-24 17:33 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-04-20  7:58 [PATCH V2] powerpc/infiniband: Use cache inhibitted and guarded mapping on powerpc Aneesh Kumar K.V
2016-04-20  7:58 ` Aneesh Kumar K.V
2016-04-20 16:29 ` Marciniszyn, Mike
2016-04-20 16:29   ` Marciniszyn, Mike
     [not found]   ` <32E1700B9017364D9B60AED9960492BC25ACE29D-RjuIdWtd+YbTXloPLtfHfbfspsVTdybXVpNB7YpNyf8@public.gmane.org>
2016-04-26 11:03     ` Michael Ellerman
2016-04-26 11:03       ` Michael Ellerman
2016-04-21 22:47 ` Benjamin Herrenschmidt
2016-04-21 22:47   ` Benjamin Herrenschmidt
     [not found]   ` <1461278876.3135.18.camel-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r@public.gmane.org>
2016-04-22 16:09     ` Jason Gunthorpe
2016-04-22 16:09       ` Jason Gunthorpe
2016-04-23  8:25       ` Benjamin Herrenschmidt
2016-04-23  8:25         ` Benjamin Herrenschmidt
     [not found]         ` <1461399949.3135.52.camel-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r@public.gmane.org>
2016-04-24 17:33           ` Aneesh Kumar K.V [this message]
2016-04-24 17:33             ` Aneesh Kumar K.V

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