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From: Thomas Gleixner <tglx@kernel.org>
To: Ryan Chen <ryan_chen@aspeedtech.com>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>, Joel Stanley <joel@jms.id.au>,
	Andrew Jeffery <andrew@codeconstruct.com.au>,
	Paul Walmsley <pjw@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alex@ghiti.fr>
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-aspeed@lists.ozlabs.org, linux-riscv@lists.infradead.org,
	Ryan Chen <ryan_chen@aspeedtech.com>
Subject: Re: [PATCH v2 1/5] dt-bindings: interrupt-controller: aspeed: Add AST2700-A2 support
Date: Fri, 20 Mar 2026 09:24:55 +0100	[thread overview]
Message-ID: <87tsualxgo.ffs@tglx> (raw)
In-Reply-To: <20260306-irqchip-v2-1-f8512c09be63@aspeedtech.com>

On Fri, Mar 06 2026 at 16:07, Ryan Chen wrote:

> Introduce a new binding describing the AST2700 interrupt controller
> architecture implemented in the A2 production silicon.
>
> The AST2700 SoC has undergone multiple silicon revisions (A0, A1, A2)
> prior to mass production. The interrupt architecture was substantially
> reworked after the A0 revision for A1, and the A1 design is retained
> unchanged in the A2 production silicon.
>
> The existing AST2700 interrupt controller binding was written against
> the pre-production A0 design. That binding does not accurately describe
> the interrupt hierarchy and routing model present in A1/A2, where
> interrupts can be routed to multiple processor-local interrupt
> controllers (Primary Service Processor (PSP) GIC, Secondary Service
> Processor (SSP)/Tertiary Service Processor (TSP) NVICs, and BootMCU
> APLIC) depending on the execution context.
>
> Hardware connectivity between interrupt controllers is expressed using
> the aspeed,interrupt-ranges property.

Gentle reminder. Can the DT folks please have a look at this so we can
make progress here?

Thanks,

        tglx



WARNING: multiple messages have this Message-ID (diff)
From: Thomas Gleixner <tglx@kernel.org>
To: Ryan Chen <ryan_chen@aspeedtech.com>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>, Joel Stanley <joel@jms.id.au>,
	Andrew Jeffery <andrew@codeconstruct.com.au>,
	Paul Walmsley <pjw@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alex@ghiti.fr>
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-aspeed@lists.ozlabs.org, linux-riscv@lists.infradead.org,
	Ryan Chen <ryan_chen@aspeedtech.com>
Subject: Re: [PATCH v2 1/5] dt-bindings: interrupt-controller: aspeed: Add AST2700-A2 support
Date: Fri, 20 Mar 2026 09:24:55 +0100	[thread overview]
Message-ID: <87tsualxgo.ffs@tglx> (raw)
In-Reply-To: <20260306-irqchip-v2-1-f8512c09be63@aspeedtech.com>

On Fri, Mar 06 2026 at 16:07, Ryan Chen wrote:

> Introduce a new binding describing the AST2700 interrupt controller
> architecture implemented in the A2 production silicon.
>
> The AST2700 SoC has undergone multiple silicon revisions (A0, A1, A2)
> prior to mass production. The interrupt architecture was substantially
> reworked after the A0 revision for A1, and the A1 design is retained
> unchanged in the A2 production silicon.
>
> The existing AST2700 interrupt controller binding was written against
> the pre-production A0 design. That binding does not accurately describe
> the interrupt hierarchy and routing model present in A1/A2, where
> interrupts can be routed to multiple processor-local interrupt
> controllers (Primary Service Processor (PSP) GIC, Secondary Service
> Processor (SSP)/Tertiary Service Processor (TSP) NVICs, and BootMCU
> APLIC) depending on the execution context.
>
> Hardware connectivity between interrupt controllers is expressed using
> the aspeed,interrupt-ranges property.

Gentle reminder. Can the DT folks please have a look at this so we can
make progress here?

Thanks,

        tglx


_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2026-03-20  8:37 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-06  8:07 [PATCH v2 0/5] AST2700-A2 interrupt controller hierarchy and route support Ryan Chen
2026-03-06  8:07 ` Ryan Chen
2026-03-06  8:07 ` [PATCH v2 1/5] dt-bindings: interrupt-controller: aspeed: Add AST2700-A2 support Ryan Chen
2026-03-06  8:07   ` Ryan Chen
2026-03-20  8:24   ` Thomas Gleixner [this message]
2026-03-20  8:24     ` Thomas Gleixner
2026-03-23 19:07   ` Rob Herring
2026-03-23 19:07     ` Rob Herring
2026-03-24  2:24     ` Ryan Chen
2026-03-24  2:24       ` Ryan Chen
2026-03-06  8:07 ` [PATCH v2 2/5] irqchip/ast2700-intc: " Ryan Chen
2026-03-06  8:07   ` Ryan Chen
2026-03-06  8:07 ` [PATCH v2 3/5] irqchip/ast2700-intc: Add KUnit tests for route resolution Ryan Chen
2026-03-06  8:07   ` Ryan Chen
2026-03-06  8:07 ` [PATCH v2 4/5] irqchip/aspeed-intc: Remove AST2700-A0 support Ryan Chen
2026-03-06  8:07   ` Ryan Chen
2026-03-06  8:07 ` [PATCH v2 5/5] dt-bindings: interrupt-controller: aspeed: " Ryan Chen
2026-03-06  8:07   ` Ryan Chen

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