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From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Keguang Zhang via B4 Relay <devnull+keguang.zhang.gmail.com@kernel.org>
Cc: Richard Weinberger <richard@nod.at>,
	 Vignesh Raghavendra <vigneshr@ti.com>,
	 Rob Herring <robh@kernel.org>,
	 Krzysztof Kozlowski <krzk+dt@kernel.org>,
	 Conor Dooley <conor+dt@kernel.org>,
	keguang.zhang@gmail.com,  linux-mtd@lists.infradead.org,
	linux-kernel@vger.kernel.org,  devicetree@vger.kernel.org,
	linux-media@vger.kernel.org
Subject: Re: [PATCH v12 2/2] mtd: rawnand: Add Loongson-1 NAND Controller Driver
Date: Thu, 06 Feb 2025 18:17:15 +0100	[thread overview]
Message-ID: <87tt972dt0.fsf@bootlin.com> (raw)
In-Reply-To: <20250121-loongson1-nand-v12-2-53507999de39@gmail.com> (Keguang Zhang via's message of "Tue, 21 Jan 2025 18:27:34 +0800")

Hello,

> +static inline int ls1x_nand_check_op(struct nand_chip *chip, const
>  struct nand_operation *op)

No inline function in a c file.

> +{
> +	struct ls1x_nand_host *host = nand_get_controller_data(chip);
> +	const struct nand_op_instr *instr1 = NULL, *instr2 = NULL;
> +	int op_id;
> +
> +	for (op_id = 0; op_id < op->ninstrs; op_id++) {
> +		const struct nand_op_instr *instr = &op->instrs[op_id];
> +
> +		if (instr->type == NAND_OP_CMD_INSTR) {
> +			if (!instr1)
> +				instr1 = instr;
> +			else if (!instr2)
> +				instr2 = instr;
> +			else
> +				break;
> +		}
> +	}
> +
> +	if (!instr1 || !instr2)
> +		return 0;

Is this expected?

> +
> +	if (instr1->ctx.cmd.opcode == NAND_CMD_RNDOUT &&
> +	    instr2->ctx.cmd.opcode == NAND_CMD_RNDOUTSTART)
> +		return 0;
> +
> +	if (instr1->ctx.cmd.opcode == NAND_CMD_READ0 &&
> +	    instr2->ctx.cmd.opcode == NAND_CMD_READSTART)
> +		return 0;
> +
> +	if (instr1->ctx.cmd.opcode == NAND_CMD_ERASE1 &&
> +	    instr2->ctx.cmd.opcode == NAND_CMD_ERASE2)
> +		return 0;
> +
> +	if (instr1->ctx.cmd.opcode == NAND_CMD_SEQIN &&
> +	    instr2->ctx.cmd.opcode == NAND_CMD_PAGEPROG)
> +		return 0;
> +
> +	dev_err(host->dev, "unsupported opcode sequence: %x %x",
> +		instr1->ctx.cmd.opcode, instr2->ctx.cmd.opcode);
> +
> +	return -EOPNOTSUPP;
> +}
> +
> +static int ls1x_nand_exec_op(struct nand_chip *chip,
> +			     const struct nand_operation *op,
> +			     bool check_only)
> +{
> +	int ret;
> +

        if (check_only) ?

> +	ret = ls1x_nand_check_op(chip, op);
> +	if (ret)
> +		return ret;
> +
> +	return nand_op_parser_exec_op(chip, &ls1x_nand_op_parser, op, check_only);
> +}
> +
> +static const char * const nand_ecc_algos[] = {
> +	[NAND_ECC_ALGO_UNKNOWN] = "none",
> +	[NAND_ECC_ALGO_HAMMING] = "hamming",
> +	[NAND_ECC_ALGO_BCH] = "bch",
> +};

No way you need this in your driver :-)

Thanks,
Miquèl

______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

WARNING: multiple messages have this Message-ID (diff)
From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Keguang Zhang via B4 Relay <devnull+keguang.zhang.gmail.com@kernel.org>
Cc: Richard Weinberger <richard@nod.at>,
	 Vignesh Raghavendra <vigneshr@ti.com>,
	 Rob Herring <robh@kernel.org>,
	 Krzysztof Kozlowski <krzk+dt@kernel.org>,
	 Conor Dooley <conor+dt@kernel.org>,
	keguang.zhang@gmail.com,  linux-mtd@lists.infradead.org,
	linux-kernel@vger.kernel.org,  devicetree@vger.kernel.org,
	linux-media@vger.kernel.org
Subject: Re: [PATCH v12 2/2] mtd: rawnand: Add Loongson-1 NAND Controller Driver
Date: Thu, 06 Feb 2025 18:17:15 +0100	[thread overview]
Message-ID: <87tt972dt0.fsf@bootlin.com> (raw)
In-Reply-To: <20250121-loongson1-nand-v12-2-53507999de39@gmail.com> (Keguang Zhang via's message of "Tue, 21 Jan 2025 18:27:34 +0800")

Hello,

> +static inline int ls1x_nand_check_op(struct nand_chip *chip, const
>  struct nand_operation *op)

No inline function in a c file.

> +{
> +	struct ls1x_nand_host *host = nand_get_controller_data(chip);
> +	const struct nand_op_instr *instr1 = NULL, *instr2 = NULL;
> +	int op_id;
> +
> +	for (op_id = 0; op_id < op->ninstrs; op_id++) {
> +		const struct nand_op_instr *instr = &op->instrs[op_id];
> +
> +		if (instr->type == NAND_OP_CMD_INSTR) {
> +			if (!instr1)
> +				instr1 = instr;
> +			else if (!instr2)
> +				instr2 = instr;
> +			else
> +				break;
> +		}
> +	}
> +
> +	if (!instr1 || !instr2)
> +		return 0;

Is this expected?

> +
> +	if (instr1->ctx.cmd.opcode == NAND_CMD_RNDOUT &&
> +	    instr2->ctx.cmd.opcode == NAND_CMD_RNDOUTSTART)
> +		return 0;
> +
> +	if (instr1->ctx.cmd.opcode == NAND_CMD_READ0 &&
> +	    instr2->ctx.cmd.opcode == NAND_CMD_READSTART)
> +		return 0;
> +
> +	if (instr1->ctx.cmd.opcode == NAND_CMD_ERASE1 &&
> +	    instr2->ctx.cmd.opcode == NAND_CMD_ERASE2)
> +		return 0;
> +
> +	if (instr1->ctx.cmd.opcode == NAND_CMD_SEQIN &&
> +	    instr2->ctx.cmd.opcode == NAND_CMD_PAGEPROG)
> +		return 0;
> +
> +	dev_err(host->dev, "unsupported opcode sequence: %x %x",
> +		instr1->ctx.cmd.opcode, instr2->ctx.cmd.opcode);
> +
> +	return -EOPNOTSUPP;
> +}
> +
> +static int ls1x_nand_exec_op(struct nand_chip *chip,
> +			     const struct nand_operation *op,
> +			     bool check_only)
> +{
> +	int ret;
> +

        if (check_only) ?

> +	ret = ls1x_nand_check_op(chip, op);
> +	if (ret)
> +		return ret;
> +
> +	return nand_op_parser_exec_op(chip, &ls1x_nand_op_parser, op, check_only);
> +}
> +
> +static const char * const nand_ecc_algos[] = {
> +	[NAND_ECC_ALGO_UNKNOWN] = "none",
> +	[NAND_ECC_ALGO_HAMMING] = "hamming",
> +	[NAND_ECC_ALGO_BCH] = "bch",
> +};

No way you need this in your driver :-)

Thanks,
Miquèl

  reply	other threads:[~2025-02-06 17:17 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-21 10:27 [PATCH v12 0/2] Add support for Loongson-1 NAND Keguang Zhang
2025-01-21 10:27 ` Keguang Zhang via B4 Relay
2025-01-21 10:27 ` Keguang Zhang via B4 Relay
2025-01-21 10:27 ` [PATCH v12 1/2] dt-bindings: mtd: Add Loongson-1 NAND Controller Keguang Zhang
2025-01-21 10:27   ` Keguang Zhang via B4 Relay
2025-01-21 10:27   ` Keguang Zhang via B4 Relay
2025-01-21 10:27 ` [PATCH v12 2/2] mtd: rawnand: Add Loongson-1 NAND Controller Driver Keguang Zhang
2025-01-21 10:27   ` Keguang Zhang via B4 Relay
2025-01-21 10:27   ` Keguang Zhang via B4 Relay
2025-02-06 17:17   ` Miquel Raynal [this message]
2025-02-06 17:17     ` Miquel Raynal
2025-03-04 11:46     ` Keguang Zhang
2025-03-04 11:46       ` Keguang Zhang
2025-03-04 13:52       ` Miquel Raynal
2025-03-04 13:52         ` Miquel Raynal

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