* [PATCH v8 0/2] Support RISC-V CSR read/write in Qtest environment
@ 2024-12-25 12:37 Ivan Klokov
2024-12-25 12:37 ` [PATCH v8 1/2] target/riscv: Add RISC-V CSR qtest support Ivan Klokov
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Ivan Klokov @ 2024-12-25 12:37 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, palmer, alistair.francis, bmeng.cn, liwei1518,
dbarboza, zhiwei_liu, farosas, lvivier, pbonzini, Ivan Klokov
These patches add functionality for unit testing RISC-V-specific registers.
The first patch adds a Qtest backend, and the second implements a simple test.
---
v8:
- Delete RFC label.
v7:
- Fix build errors, add Reviewed-by, Acked-by.
---
Ivan Klokov (2):
target/riscv: Add RISC-V CSR qtest support
tests/qtest: QTest example for RISC-V CSR register
hw/riscv/riscv_hart.c | 56 ++++++++++++++++++++++++++++++++++++
tests/qtest/libqtest.c | 27 +++++++++++++++++
tests/qtest/libqtest.h | 14 +++++++++
tests/qtest/meson.build | 2 +-
tests/qtest/riscv-csr-test.c | 56 ++++++++++++++++++++++++++++++++++++
5 files changed, 154 insertions(+), 1 deletion(-)
create mode 100644 tests/qtest/riscv-csr-test.c
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v8 1/2] target/riscv: Add RISC-V CSR qtest support 2024-12-25 12:37 [PATCH v8 0/2] Support RISC-V CSR read/write in Qtest environment Ivan Klokov @ 2024-12-25 12:37 ` Ivan Klokov 2025-01-06 1:32 ` Alistair Francis 2024-12-25 12:37 ` [PATCH v8 2/2] tests/qtest: QTest example for RISC-V CSR register Ivan Klokov 2025-01-02 15:47 ` [PATCH v8 0/2] Support RISC-V CSR read/write in Qtest environment Fabiano Rosas 2 siblings, 1 reply; 6+ messages in thread From: Ivan Klokov @ 2024-12-25 12:37 UTC (permalink / raw) To: qemu-devel Cc: qemu-riscv, palmer, alistair.francis, bmeng.cn, liwei1518, dbarboza, zhiwei_liu, farosas, lvivier, pbonzini, Ivan Klokov The RISC-V architecture supports the creation of custom CSR-mapped devices. It would be convenient to test them in the same way as MMIO-mapped devices. To do this, a new call has been added to read/write CSR registers. Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com> Acked-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- hw/riscv/riscv_hart.c | 56 ++++++++++++++++++++++++++++++++++++++++++ tests/qtest/libqtest.c | 27 ++++++++++++++++++++ tests/qtest/libqtest.h | 14 +++++++++++ 3 files changed, 97 insertions(+) diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index bc9ffdd2d4..b8151682c0 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -22,6 +22,9 @@ #include "qapi/error.h" #include "qemu/module.h" #include "system/reset.h" +#include "qemu/cutils.h" +#include "sysemu/qtest.h" +#include "sysemu/reset.h" #include "hw/sysbus.h" #include "target/riscv/cpu.h" #include "hw/qdev-properties.h" @@ -41,6 +44,55 @@ static void riscv_harts_cpu_reset(void *opaque) cpu_reset(CPU(cpu)); } +#ifndef CONFIG_USER_ONLY +static void csr_call(char *cmd, uint64_t cpu_num, int csrno, uint64_t *val) +{ + RISCVCPU *cpu = RISCV_CPU(cpu_by_arch_id(cpu_num)); + CPURISCVState *env = &cpu->env; + + int ret = RISCV_EXCP_NONE; + if (strcmp(cmd, "get_csr") == 0) { + ret = riscv_csrr(env, csrno, (target_ulong *)val); + } else if (strcmp(cmd, "set_csr") == 0) { + ret = riscv_csrrw(env, csrno, NULL, *(target_ulong *)val, + MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); + } + + g_assert(ret == RISCV_EXCP_NONE); +} + +static bool csr_qtest_callback(CharBackend *chr, gchar **words) +{ + if (strcmp(words[0], "csr") == 0) { + + uint64_t cpu; + uint64_t val; + int rc, csr; + + rc = qemu_strtou64(words[2], NULL, 0, &cpu); + g_assert(rc == 0); + rc = qemu_strtoi(words[3], NULL, 0, &csr); + g_assert(rc == 0); + rc = qemu_strtou64(words[4], NULL, 0, &val); + g_assert(rc == 0); + csr_call(words[1], cpu, csr, &val); + + qtest_send_prefix(chr); + qtest_sendf(chr, "OK 0 "TARGET_FMT_lx"\n", (target_ulong)val); + + return true; + } + + return false; +} + +static void riscv_cpu_register_csr_qtest_callback(void) +{ + static GOnce once; + g_once(&once, (GThreadFunc)qtest_set_command_cb, csr_qtest_callback); +} +#endif + static bool riscv_hart_realize(RISCVHartArrayState *s, int idx, char *cpu_type, Error **errp) { @@ -58,6 +110,10 @@ static void riscv_harts_realize(DeviceState *dev, Error **errp) s->harts = g_new0(RISCVCPU, s->num_harts); +#ifndef CONFIG_USER_ONLY + riscv_cpu_register_csr_qtest_callback(); +#endif + for (n = 0; n < s->num_harts; n++) { if (!riscv_hart_realize(s, n, s->cpu_type, errp)) { return; diff --git a/tests/qtest/libqtest.c b/tests/qtest/libqtest.c index 8de5f1fde3..4bc9643aad 100644 --- a/tests/qtest/libqtest.c +++ b/tests/qtest/libqtest.c @@ -1218,6 +1218,33 @@ uint64_t qtest_rtas_call(QTestState *s, const char *name, return 0; } +static void qtest_rsp_csr(QTestState *s, uint64_t *val) +{ + gchar **args; + uint64_t ret; + int rc; + + args = qtest_rsp_args(s, 3); + + rc = qemu_strtou64(args[1], NULL, 16, &ret); + g_assert(rc == 0); + rc = qemu_strtou64(args[2], NULL, 16, val); + g_assert(rc == 0); + + g_strfreev(args); +} + +uint64_t qtest_csr_call(QTestState *s, const char *name, + uint64_t cpu, int csr, + uint64_t *val) +{ + qtest_sendf(s, "csr %s 0x%"PRIx64" %d 0x%"PRIx64"\n", + name, cpu, csr, *val); + + qtest_rsp_csr(s, val); + return 0; +} + void qtest_add_func(const char *str, void (*fn)(void)) { gchar *path = g_strdup_printf("/%s/%s", qtest_get_arch(), str); diff --git a/tests/qtest/libqtest.h b/tests/qtest/libqtest.h index f23d80e9e5..cd35e11d4c 100644 --- a/tests/qtest/libqtest.h +++ b/tests/qtest/libqtest.h @@ -600,6 +600,20 @@ uint64_t qtest_rtas_call(QTestState *s, const char *name, uint32_t nargs, uint64_t args, uint32_t nret, uint64_t ret); +/** + * qtest_csr_call: + * @s: #QTestState instance to operate on. + * @name: name of the command to call. + * @cpu: hart number. + * @csr: CSR number. + * @val: Value for reading/writing. + * + * Call an RISC-V CSR read/write function + */ +uint64_t qtest_csr_call(QTestState *s, const char *name, + uint64_t cpu, int csr, + unsigned long *val); + /** * qtest_bufread: * @s: #QTestState instance to operate on. -- 2.34.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v8 1/2] target/riscv: Add RISC-V CSR qtest support 2024-12-25 12:37 ` [PATCH v8 1/2] target/riscv: Add RISC-V CSR qtest support Ivan Klokov @ 2025-01-06 1:32 ` Alistair Francis 0 siblings, 0 replies; 6+ messages in thread From: Alistair Francis @ 2025-01-06 1:32 UTC (permalink / raw) To: Ivan Klokov Cc: qemu-devel, qemu-riscv, palmer, alistair.francis, bmeng.cn, liwei1518, dbarboza, zhiwei_liu, farosas, lvivier, pbonzini On Wed, Dec 25, 2024 at 10:38 PM Ivan Klokov <ivan.klokov@syntacore.com> wrote: > > The RISC-V architecture supports the creation of custom > CSR-mapped devices. It would be convenient to test them in the same way > as MMIO-mapped devices. To do this, a new call has been added > to read/write CSR registers. > > Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com> > Acked-by: Fabiano Rosas <farosas@suse.de> > Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > hw/riscv/riscv_hart.c | 56 ++++++++++++++++++++++++++++++++++++++++++ > tests/qtest/libqtest.c | 27 ++++++++++++++++++++ > tests/qtest/libqtest.h | 14 +++++++++++ > 3 files changed, 97 insertions(+) > > diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c > index bc9ffdd2d4..b8151682c0 100644 > --- a/hw/riscv/riscv_hart.c > +++ b/hw/riscv/riscv_hart.c > @@ -22,6 +22,9 @@ > #include "qapi/error.h" > #include "qemu/module.h" > #include "system/reset.h" > +#include "qemu/cutils.h" > +#include "sysemu/qtest.h" > +#include "sysemu/reset.h" > #include "hw/sysbus.h" > #include "target/riscv/cpu.h" > #include "hw/qdev-properties.h" > @@ -41,6 +44,55 @@ static void riscv_harts_cpu_reset(void *opaque) > cpu_reset(CPU(cpu)); > } > > +#ifndef CONFIG_USER_ONLY > +static void csr_call(char *cmd, uint64_t cpu_num, int csrno, uint64_t *val) > +{ > + RISCVCPU *cpu = RISCV_CPU(cpu_by_arch_id(cpu_num)); > + CPURISCVState *env = &cpu->env; > + > + int ret = RISCV_EXCP_NONE; > + if (strcmp(cmd, "get_csr") == 0) { > + ret = riscv_csrr(env, csrno, (target_ulong *)val); > + } else if (strcmp(cmd, "set_csr") == 0) { > + ret = riscv_csrrw(env, csrno, NULL, *(target_ulong *)val, > + MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); > + } > + > + g_assert(ret == RISCV_EXCP_NONE); > +} > + > +static bool csr_qtest_callback(CharBackend *chr, gchar **words) > +{ > + if (strcmp(words[0], "csr") == 0) { > + > + uint64_t cpu; > + uint64_t val; > + int rc, csr; > + > + rc = qemu_strtou64(words[2], NULL, 0, &cpu); > + g_assert(rc == 0); > + rc = qemu_strtoi(words[3], NULL, 0, &csr); > + g_assert(rc == 0); > + rc = qemu_strtou64(words[4], NULL, 0, &val); > + g_assert(rc == 0); > + csr_call(words[1], cpu, csr, &val); > + > + qtest_send_prefix(chr); > + qtest_sendf(chr, "OK 0 "TARGET_FMT_lx"\n", (target_ulong)val); > + > + return true; > + } > + > + return false; > +} > + > +static void riscv_cpu_register_csr_qtest_callback(void) > +{ > + static GOnce once; > + g_once(&once, (GThreadFunc)qtest_set_command_cb, csr_qtest_callback); > +} > +#endif > + > static bool riscv_hart_realize(RISCVHartArrayState *s, int idx, > char *cpu_type, Error **errp) > { > @@ -58,6 +110,10 @@ static void riscv_harts_realize(DeviceState *dev, Error **errp) > > s->harts = g_new0(RISCVCPU, s->num_harts); > > +#ifndef CONFIG_USER_ONLY > + riscv_cpu_register_csr_qtest_callback(); > +#endif > + > for (n = 0; n < s->num_harts; n++) { > if (!riscv_hart_realize(s, n, s->cpu_type, errp)) { > return; > diff --git a/tests/qtest/libqtest.c b/tests/qtest/libqtest.c > index 8de5f1fde3..4bc9643aad 100644 > --- a/tests/qtest/libqtest.c > +++ b/tests/qtest/libqtest.c > @@ -1218,6 +1218,33 @@ uint64_t qtest_rtas_call(QTestState *s, const char *name, > return 0; > } > > +static void qtest_rsp_csr(QTestState *s, uint64_t *val) > +{ > + gchar **args; > + uint64_t ret; > + int rc; > + > + args = qtest_rsp_args(s, 3); > + > + rc = qemu_strtou64(args[1], NULL, 16, &ret); > + g_assert(rc == 0); > + rc = qemu_strtou64(args[2], NULL, 16, val); > + g_assert(rc == 0); > + > + g_strfreev(args); > +} > + > +uint64_t qtest_csr_call(QTestState *s, const char *name, > + uint64_t cpu, int csr, > + uint64_t *val) > +{ > + qtest_sendf(s, "csr %s 0x%"PRIx64" %d 0x%"PRIx64"\n", > + name, cpu, csr, *val); > + > + qtest_rsp_csr(s, val); > + return 0; > +} > + > void qtest_add_func(const char *str, void (*fn)(void)) > { > gchar *path = g_strdup_printf("/%s/%s", qtest_get_arch(), str); > diff --git a/tests/qtest/libqtest.h b/tests/qtest/libqtest.h > index f23d80e9e5..cd35e11d4c 100644 > --- a/tests/qtest/libqtest.h > +++ b/tests/qtest/libqtest.h > @@ -600,6 +600,20 @@ uint64_t qtest_rtas_call(QTestState *s, const char *name, > uint32_t nargs, uint64_t args, > uint32_t nret, uint64_t ret); > > +/** > + * qtest_csr_call: > + * @s: #QTestState instance to operate on. > + * @name: name of the command to call. > + * @cpu: hart number. > + * @csr: CSR number. > + * @val: Value for reading/writing. > + * > + * Call an RISC-V CSR read/write function > + */ > +uint64_t qtest_csr_call(QTestState *s, const char *name, > + uint64_t cpu, int csr, > + unsigned long *val); > + > /** > * qtest_bufread: > * @s: #QTestState instance to operate on. > -- > 2.34.1 > > > ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v8 2/2] tests/qtest: QTest example for RISC-V CSR register 2024-12-25 12:37 [PATCH v8 0/2] Support RISC-V CSR read/write in Qtest environment Ivan Klokov 2024-12-25 12:37 ` [PATCH v8 1/2] target/riscv: Add RISC-V CSR qtest support Ivan Klokov @ 2024-12-25 12:37 ` Ivan Klokov 2025-01-06 1:34 ` Alistair Francis 2025-01-02 15:47 ` [PATCH v8 0/2] Support RISC-V CSR read/write in Qtest environment Fabiano Rosas 2 siblings, 1 reply; 6+ messages in thread From: Ivan Klokov @ 2024-12-25 12:37 UTC (permalink / raw) To: qemu-devel Cc: qemu-riscv, palmer, alistair.francis, bmeng.cn, liwei1518, dbarboza, zhiwei_liu, farosas, lvivier, pbonzini, Ivan Klokov Added demo for reading CSR register from qtest environment. Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- tests/qtest/meson.build | 2 +- tests/qtest/riscv-csr-test.c | 56 ++++++++++++++++++++++++++++++++++++ 2 files changed, 57 insertions(+), 1 deletion(-) create mode 100644 tests/qtest/riscv-csr-test.c diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index c5a70021c5..7eb1199d91 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -273,7 +273,7 @@ qtests_s390x = \ qtests_riscv32 = \ (config_all_devices.has_key('CONFIG_SIFIVE_E_AON') ? ['sifive-e-aon-watchdog-test'] : []) -qtests_riscv64 = \ +qtests_riscv64 = ['riscv-csr-test'] + \ (unpack_edk2_blobs ? ['bios-tables-test'] : []) qos_test_ss = ss.source_set() diff --git a/tests/qtest/riscv-csr-test.c b/tests/qtest/riscv-csr-test.c new file mode 100644 index 0000000000..ff5c29e6c6 --- /dev/null +++ b/tests/qtest/riscv-csr-test.c @@ -0,0 +1,56 @@ +/* + * QTest testcase for RISC-V CSRs + * + * Copyright (c) 2024 Syntacore. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" +#include "libqtest.h" + +#define CSR_MVENDORID 0xf11 +#define CSR_MISELECT 0x350 + +static void run_test_csr(void) +{ + uint64_t res; + uint64_t val = 0; + + QTestState *qts = qtest_init("-machine virt -cpu veyron-v1"); + + res = qtest_csr_call(qts, "get_csr", 0, CSR_MVENDORID, &val); + + g_assert_cmpint(res, ==, 0); + g_assert_cmpint(val, ==, 0x61f); + + val = 0xff; + res = qtest_csr_call(qts, "set_csr", 0, CSR_MISELECT, &val); + + g_assert_cmpint(res, ==, 0); + + val = 0; + res = qtest_csr_call(qts, "get_csr", 0, CSR_MISELECT, &val); + + g_assert_cmpint(res, ==, 0); + g_assert_cmpint(val, ==, 0xff); + + qtest_quit(qts); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + qtest_add_func("/cpu/csr", run_test_csr); + + return g_test_run(); +} -- 2.34.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v8 2/2] tests/qtest: QTest example for RISC-V CSR register 2024-12-25 12:37 ` [PATCH v8 2/2] tests/qtest: QTest example for RISC-V CSR register Ivan Klokov @ 2025-01-06 1:34 ` Alistair Francis 0 siblings, 0 replies; 6+ messages in thread From: Alistair Francis @ 2025-01-06 1:34 UTC (permalink / raw) To: Ivan Klokov Cc: qemu-devel, qemu-riscv, palmer, alistair.francis, bmeng.cn, liwei1518, dbarboza, zhiwei_liu, farosas, lvivier, pbonzini On Wed, Dec 25, 2024 at 10:39 PM Ivan Klokov <ivan.klokov@syntacore.com> wrote: > > Added demo for reading CSR register from qtest environment. > > Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com> > Reviewed-by: Fabiano Rosas <farosas@suse.de> > Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > tests/qtest/meson.build | 2 +- > tests/qtest/riscv-csr-test.c | 56 ++++++++++++++++++++++++++++++++++++ > 2 files changed, 57 insertions(+), 1 deletion(-) > create mode 100644 tests/qtest/riscv-csr-test.c > > diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build > index c5a70021c5..7eb1199d91 100644 > --- a/tests/qtest/meson.build > +++ b/tests/qtest/meson.build > @@ -273,7 +273,7 @@ qtests_s390x = \ > qtests_riscv32 = \ > (config_all_devices.has_key('CONFIG_SIFIVE_E_AON') ? ['sifive-e-aon-watchdog-test'] : []) > > -qtests_riscv64 = \ > +qtests_riscv64 = ['riscv-csr-test'] + \ > (unpack_edk2_blobs ? ['bios-tables-test'] : []) > > qos_test_ss = ss.source_set() > diff --git a/tests/qtest/riscv-csr-test.c b/tests/qtest/riscv-csr-test.c > new file mode 100644 > index 0000000000..ff5c29e6c6 > --- /dev/null > +++ b/tests/qtest/riscv-csr-test.c > @@ -0,0 +1,56 @@ > +/* > + * QTest testcase for RISC-V CSRs > + * > + * Copyright (c) 2024 Syntacore. > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License > + * for more details. > + */ > + > +#include "qemu/osdep.h" > +#include "libqtest.h" > + > +#define CSR_MVENDORID 0xf11 > +#define CSR_MISELECT 0x350 > + > +static void run_test_csr(void) > +{ > + uint64_t res; > + uint64_t val = 0; > + > + QTestState *qts = qtest_init("-machine virt -cpu veyron-v1"); > + > + res = qtest_csr_call(qts, "get_csr", 0, CSR_MVENDORID, &val); > + > + g_assert_cmpint(res, ==, 0); > + g_assert_cmpint(val, ==, 0x61f); > + > + val = 0xff; > + res = qtest_csr_call(qts, "set_csr", 0, CSR_MISELECT, &val); > + > + g_assert_cmpint(res, ==, 0); > + > + val = 0; > + res = qtest_csr_call(qts, "get_csr", 0, CSR_MISELECT, &val); > + > + g_assert_cmpint(res, ==, 0); > + g_assert_cmpint(val, ==, 0xff); > + > + qtest_quit(qts); > +} > + > +int main(int argc, char **argv) > +{ > + g_test_init(&argc, &argv, NULL); > + > + qtest_add_func("/cpu/csr", run_test_csr); > + > + return g_test_run(); > +} > -- > 2.34.1 > > > ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v8 0/2] Support RISC-V CSR read/write in Qtest environment 2024-12-25 12:37 [PATCH v8 0/2] Support RISC-V CSR read/write in Qtest environment Ivan Klokov 2024-12-25 12:37 ` [PATCH v8 1/2] target/riscv: Add RISC-V CSR qtest support Ivan Klokov 2024-12-25 12:37 ` [PATCH v8 2/2] tests/qtest: QTest example for RISC-V CSR register Ivan Klokov @ 2025-01-02 15:47 ` Fabiano Rosas 2 siblings, 0 replies; 6+ messages in thread From: Fabiano Rosas @ 2025-01-02 15:47 UTC (permalink / raw) To: Ivan Klokov, qemu-devel Cc: qemu-riscv, palmer, alistair.francis, bmeng.cn, liwei1518, dbarboza, zhiwei_liu, lvivier, pbonzini, Ivan Klokov Ivan Klokov <ivan.klokov@syntacore.com> writes: > These patches add functionality for unit testing RISC-V-specific registers. > The first patch adds a Qtest backend, and the second implements a simple test. > > --- > v8: > - Delete RFC label. > v7: > - Fix build errors, add Reviewed-by, Acked-by. > --- > > Ivan Klokov (2): > target/riscv: Add RISC-V CSR qtest support > tests/qtest: QTest example for RISC-V CSR register > > hw/riscv/riscv_hart.c | 56 ++++++++++++++++++++++++++++++++++++ > tests/qtest/libqtest.c | 27 +++++++++++++++++ > tests/qtest/libqtest.h | 14 +++++++++ > tests/qtest/meson.build | 2 +- > tests/qtest/riscv-csr-test.c | 56 ++++++++++++++++++++++++++++++++++++ > 5 files changed, 154 insertions(+), 1 deletion(-) > create mode 100644 tests/qtest/riscv-csr-test.c Hi, there are some CI jobs failing with this series, could you take a look? https://gitlab.com/farosas/qemu/-/pipelines/1609210965 ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2025-01-06 1:35 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-12-25 12:37 [PATCH v8 0/2] Support RISC-V CSR read/write in Qtest environment Ivan Klokov 2024-12-25 12:37 ` [PATCH v8 1/2] target/riscv: Add RISC-V CSR qtest support Ivan Klokov 2025-01-06 1:32 ` Alistair Francis 2024-12-25 12:37 ` [PATCH v8 2/2] tests/qtest: QTest example for RISC-V CSR register Ivan Klokov 2025-01-06 1:34 ` Alistair Francis 2025-01-02 15:47 ` [PATCH v8 0/2] Support RISC-V CSR read/write in Qtest environment Fabiano Rosas
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