[PATCH 1/6] drm/i915/selftests: Serialise nop reset with retirement

[PATCH 1/6] drm/i915/selftests: Serialise nop reset with retirement

[Chris Wilson]

In order for the reset count to be accurate across our selftest, we need
to prevent the background retire worker from modifying our expected
state.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index 3ceb397c8645..0e0b6c572ae9 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -398,6 +398,7 @@ static int igt_reset_nop(void *arg)
 	count = 0;
 	do {
 		mutex_lock(&i915->drm.struct_mutex);
+
 		for_each_engine(engine, i915, id) {
 			int i;
 
@@ -413,11 +414,12 @@ static int igt_reset_nop(void *arg)
 				i915_request_add(rq);
 			}
 		}
-		mutex_unlock(&i915->drm.struct_mutex);
 
 		igt_global_reset_lock(i915);
 		i915_reset(i915, ALL_ENGINES, NULL);
 		igt_global_reset_unlock(i915);
+
+		mutex_unlock(&i915->drm.struct_mutex);
 		if (i915_reset_failed(i915)) {
 			err = -EIO;
 			break;
@@ -511,9 +513,8 @@ static int igt_reset_nop_engine(void *arg)
 
 				i915_request_add(rq);
 			}
-			mutex_unlock(&i915->drm.struct_mutex);
-
 			err = i915_reset_engine(engine, NULL);
+			mutex_unlock(&i915->drm.struct_mutex);
 			if (err) {
 				pr_err("i915_reset_engine failed\n");
 				break;
-- 
2.20.1

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[PATCH 2/6] drm/i915/selftests: Drop manual request wakerefs around hangcheck

[Chris Wilson]

We no longer need to manually acquire a wakeref for request emission, so
drop the redundant wakerefs, letting us test our wakeref handling more
precisely.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 7 -------
 drivers/gpu/drm/i915/gt/selftest_reset.c     | 4 ++--
 2 files changed, 2 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index 0e0b6c572ae9..cf592a049a71 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -373,7 +373,6 @@ static int igt_reset_nop(void *arg)
 	struct i915_gem_context *ctx;
 	unsigned int reset_count, count;
 	enum intel_engine_id id;
-	intel_wakeref_t wakeref;
 	struct drm_file *file;
 	IGT_TIMEOUT(end_time);
 	int err = 0;
@@ -393,7 +392,6 @@ static int igt_reset_nop(void *arg)
 	}
 
 	i915_gem_context_clear_bannable(ctx);
-	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
 	reset_count = i915_reset_count(&i915->gpu_error);
 	count = 0;
 	do {
@@ -442,8 +440,6 @@ static int igt_reset_nop(void *arg)
 	err = igt_flush_test(i915, I915_WAIT_LOCKED);
 	mutex_unlock(&i915->drm.struct_mutex);
 
-	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
-
 out:
 	mock_file_free(i915, file);
 	if (i915_reset_failed(i915))
@@ -457,7 +453,6 @@ static int igt_reset_nop_engine(void *arg)
 	struct intel_engine_cs *engine;
 	struct i915_gem_context *ctx;
 	enum intel_engine_id id;
-	intel_wakeref_t wakeref;
 	struct drm_file *file;
 	int err = 0;
 
@@ -479,7 +474,6 @@ static int igt_reset_nop_engine(void *arg)
 	}
 
 	i915_gem_context_clear_bannable(ctx);
-	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
 	for_each_engine(engine, i915, id) {
 		unsigned int reset_count, reset_engine_count;
 		unsigned int count;
@@ -549,7 +543,6 @@ static int igt_reset_nop_engine(void *arg)
 	err = igt_flush_test(i915, I915_WAIT_LOCKED);
 	mutex_unlock(&i915->drm.struct_mutex);
 
-	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
 out:
 	mock_file_free(i915, file);
 	if (i915_reset_failed(i915))
diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c b/drivers/gpu/drm/i915/gt/selftest_reset.c
index 89da9e7cc1ba..64c2c8ab64ec 100644
--- a/drivers/gpu/drm/i915/gt/selftest_reset.c
+++ b/drivers/gpu/drm/i915/gt/selftest_reset.c
@@ -63,8 +63,8 @@ static int igt_atomic_reset(void *arg)
 
 	/* Check that the resets are usable from atomic context */
 
+	intel_gt_pm_get(&i915->gt);
 	igt_global_reset_lock(i915);
-	mutex_lock(&i915->drm.struct_mutex);
 
 	/* Flush any requests before we get started and check basics */
 	if (!igt_force_reset(i915))
@@ -89,8 +89,8 @@ static int igt_atomic_reset(void *arg)
 	igt_force_reset(i915);
 
 unlock:
-	mutex_unlock(&i915->drm.struct_mutex);
 	igt_global_reset_unlock(i915);
+	intel_gt_pm_put(&i915->gt);
 
 	return err;
 }
-- 
2.20.1

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Re: [PATCH 2/6] drm/i915/selftests: Drop manual request wakerefs around hangcheck

[Chris Wilson]

Quoting Chris Wilson (2019-06-26 07:52:59)
> We no longer need to manually acquire a wakeref for request emission, so
> drop the redundant wakerefs, letting us test our wakeref handling more
> precisely.

References: 79ffac8599c4 ("drm/i915: Invert the GEM wakeref hierarchy")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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Re: [PATCH 2/6] drm/i915/selftests: Drop manual request wakerefs around hangcheck

[Mika Kuoppala]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> We no longer need to manually acquire a wakeref for request emission, so
> drop the redundant wakerefs, letting us test our wakeref handling more
> precisely.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

Riding on the request's ref and getting more fine
grained sounds good.

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 7 -------
>  drivers/gpu/drm/i915/gt/selftest_reset.c     | 4 ++--
>  2 files changed, 2 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> index 0e0b6c572ae9..cf592a049a71 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> @@ -373,7 +373,6 @@ static int igt_reset_nop(void *arg)
>  	struct i915_gem_context *ctx;
>  	unsigned int reset_count, count;
>  	enum intel_engine_id id;
> -	intel_wakeref_t wakeref;
>  	struct drm_file *file;
>  	IGT_TIMEOUT(end_time);
>  	int err = 0;
> @@ -393,7 +392,6 @@ static int igt_reset_nop(void *arg)
>  	}
>  
>  	i915_gem_context_clear_bannable(ctx);
> -	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
>  	reset_count = i915_reset_count(&i915->gpu_error);
>  	count = 0;
>  	do {
> @@ -442,8 +440,6 @@ static int igt_reset_nop(void *arg)
>  	err = igt_flush_test(i915, I915_WAIT_LOCKED);
>  	mutex_unlock(&i915->drm.struct_mutex);
>  
> -	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
> -
>  out:
>  	mock_file_free(i915, file);
>  	if (i915_reset_failed(i915))
> @@ -457,7 +453,6 @@ static int igt_reset_nop_engine(void *arg)
>  	struct intel_engine_cs *engine;
>  	struct i915_gem_context *ctx;
>  	enum intel_engine_id id;
> -	intel_wakeref_t wakeref;
>  	struct drm_file *file;
>  	int err = 0;
>  
> @@ -479,7 +474,6 @@ static int igt_reset_nop_engine(void *arg)
>  	}
>  
>  	i915_gem_context_clear_bannable(ctx);
> -	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
>  	for_each_engine(engine, i915, id) {
>  		unsigned int reset_count, reset_engine_count;
>  		unsigned int count;
> @@ -549,7 +543,6 @@ static int igt_reset_nop_engine(void *arg)
>  	err = igt_flush_test(i915, I915_WAIT_LOCKED);
>  	mutex_unlock(&i915->drm.struct_mutex);
>  
> -	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
>  out:
>  	mock_file_free(i915, file);
>  	if (i915_reset_failed(i915))
> diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c b/drivers/gpu/drm/i915/gt/selftest_reset.c
> index 89da9e7cc1ba..64c2c8ab64ec 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_reset.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_reset.c
> @@ -63,8 +63,8 @@ static int igt_atomic_reset(void *arg)
>  
>  	/* Check that the resets are usable from atomic context */
>  
> +	intel_gt_pm_get(&i915->gt);
>  	igt_global_reset_lock(i915);
> -	mutex_lock(&i915->drm.struct_mutex);
>  
>  	/* Flush any requests before we get started and check basics */
>  	if (!igt_force_reset(i915))
> @@ -89,8 +89,8 @@ static int igt_atomic_reset(void *arg)
>  	igt_force_reset(i915);
>  
>  unlock:
> -	mutex_unlock(&i915->drm.struct_mutex);
>  	igt_global_reset_unlock(i915);
> +	intel_gt_pm_put(&i915->gt);
>  
>  	return err;
>  }
> -- 
> 2.20.1
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[PATCH 3/6] drm/i915/selftests: Fixup atomic reset checking

[Chris Wilson]

We require that the intel_gpu_reset() was atomic, not the whole of
i915_reset() which is guarded by a mutex. However, we do require that
i915_reset_engine() is atomic for use from within the submission tasklet.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/selftest_reset.c | 65 +++++++++++++++++++++++-
 1 file changed, 63 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c b/drivers/gpu/drm/i915/gt/selftest_reset.c
index 64c2c8ab64ec..641cf3aee8d5 100644
--- a/drivers/gpu/drm/i915/gt/selftest_reset.c
+++ b/drivers/gpu/drm/i915/gt/selftest_reset.c
@@ -73,11 +73,13 @@ static int igt_atomic_reset(void *arg)
 	for (p = igt_atomic_phases; p->name; p++) {
 		GEM_TRACE("intel_gpu_reset under %s\n", p->name);
 
-		p->critical_section_begin();
 		reset_prepare(i915);
+		p->critical_section_begin();
+
 		err = intel_gpu_reset(i915, ALL_ENGINES);
-		reset_finish(i915);
+
 		p->critical_section_end();
+		reset_finish(i915);
 
 		if (err) {
 			pr_err("intel_gpu_reset failed under %s\n", p->name);
@@ -95,12 +97,71 @@ static int igt_atomic_reset(void *arg)
 	return err;
 }
 
+static int igt_atomic_engine_reset(void *arg)
+{
+	struct drm_i915_private *i915 = arg;
+	const typeof(*igt_atomic_phases) *p;
+	struct intel_engine_cs *engine;
+	enum intel_engine_id id;
+	int err = 0;
+
+	/* Check that the resets are usable from atomic context */
+
+	if (!intel_has_reset_engine(i915))
+		return 0;
+
+	if (USES_GUC_SUBMISSION(i915))
+		return 0;
+
+	intel_gt_pm_get(&i915->gt);
+	igt_global_reset_lock(i915);
+
+	/* Flush any requests before we get started and check basics */
+	if (!igt_force_reset(i915))
+		goto out_unlock;
+
+	for_each_engine(engine, i915, id) {
+		tasklet_disable_nosync(&engine->execlists.tasklet);
+		intel_engine_pm_get(engine);
+
+		for (p = igt_atomic_phases; p->name; p++) {
+			GEM_TRACE("i915_reset_engine(%s) under %s\n",
+				  engine->name, p->name);
+
+			p->critical_section_begin();
+			err = i915_reset_engine(engine, NULL);
+			p->critical_section_end();
+
+			if (err) {
+				pr_err("i915_reset_engine(%s) failed under %s\n",
+				       engine->name, p->name);
+				break;
+			}
+		}
+
+		intel_engine_pm_put(engine);
+		tasklet_enable(&engine->execlists.tasklet);
+		if (err)
+			break;
+	}
+
+	/* As we poke around the guts, do a full reset before continuing. */
+	igt_force_reset(i915);
+
+out_unlock:
+	igt_global_reset_unlock(i915);
+	intel_gt_pm_put(&i915->gt);
+
+	return err;
+}
+
 int intel_reset_live_selftests(struct drm_i915_private *i915)
 {
 	static const struct i915_subtest tests[] = {
 		SUBTEST(igt_global_reset), /* attempt to recover GPU first */
 		SUBTEST(igt_wedged_reset),
 		SUBTEST(igt_atomic_reset),
+		SUBTEST(igt_atomic_engine_reset),
 	};
 	intel_wakeref_t wakeref;
 	int err = 0;
-- 
2.20.1

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Re: [PATCH 3/6] drm/i915/selftests: Fixup atomic reset checking

[Mika Kuoppala]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> We require that the intel_gpu_reset() was atomic, not the whole of
> i915_reset() which is guarded by a mutex. However, we do require that
> i915_reset_engine() is atomic for use from within the submission tasklet.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/gt/selftest_reset.c | 65 +++++++++++++++++++++++-
>  1 file changed, 63 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c b/drivers/gpu/drm/i915/gt/selftest_reset.c
> index 64c2c8ab64ec..641cf3aee8d5 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_reset.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_reset.c
> @@ -73,11 +73,13 @@ static int igt_atomic_reset(void *arg)
>  	for (p = igt_atomic_phases; p->name; p++) {
>  		GEM_TRACE("intel_gpu_reset under %s\n", p->name);
>  
> -		p->critical_section_begin();
>  		reset_prepare(i915);
> +		p->critical_section_begin();
> +
>  		err = intel_gpu_reset(i915, ALL_ENGINES);
> -		reset_finish(i915);
> +
>  		p->critical_section_end();
> +		reset_finish(i915);
>  
>  		if (err) {
>  			pr_err("intel_gpu_reset failed under %s\n", p->name);
> @@ -95,12 +97,71 @@ static int igt_atomic_reset(void *arg)
>  	return err;
>  }
>  
> +static int igt_atomic_engine_reset(void *arg)
> +{
> +	struct drm_i915_private *i915 = arg;
> +	const typeof(*igt_atomic_phases) *p;

I did admire the nastyness of this array.

> +	struct intel_engine_cs *engine;
> +	enum intel_engine_id id;
> +	int err = 0;
> +
> +	/* Check that the resets are usable from atomic context */
> +
> +	if (!intel_has_reset_engine(i915))
> +		return 0;
> +
> +	if (USES_GUC_SUBMISSION(i915))
> +		return 0;
> +
> +	intel_gt_pm_get(&i915->gt);
> +	igt_global_reset_lock(i915);
> +
> +	/* Flush any requests before we get started and check basics */
> +	if (!igt_force_reset(i915))
> +		goto out_unlock;

I would still go out with error if the prerequisites
are not met?

-Mika

> +
> +	for_each_engine(engine, i915, id) {
> +		tasklet_disable_nosync(&engine->execlists.tasklet);
> +		intel_engine_pm_get(engine);
> +
> +		for (p = igt_atomic_phases; p->name; p++) {
> +			GEM_TRACE("i915_reset_engine(%s) under %s\n",
> +				  engine->name, p->name);
> +
> +			p->critical_section_begin();
> +			err = i915_reset_engine(engine, NULL);
> +			p->critical_section_end();
> +
> +			if (err) {
> +				pr_err("i915_reset_engine(%s) failed under %s\n",
> +				       engine->name, p->name);
> +				break;
> +			}
> +		}
> +
> +		intel_engine_pm_put(engine);
> +		tasklet_enable(&engine->execlists.tasklet);
> +		if (err)
> +			break;
> +	}
> +
> +	/* As we poke around the guts, do a full reset before continuing. */
> +	igt_force_reset(i915);
> +
> +out_unlock:
> +	igt_global_reset_unlock(i915);
> +	intel_gt_pm_put(&i915->gt);
> +
> +	return err;
> +}
> +
>  int intel_reset_live_selftests(struct drm_i915_private *i915)
>  {
>  	static const struct i915_subtest tests[] = {
>  		SUBTEST(igt_global_reset), /* attempt to recover GPU first */
>  		SUBTEST(igt_wedged_reset),
>  		SUBTEST(igt_atomic_reset),
> +		SUBTEST(igt_atomic_engine_reset),
>  	};
>  	intel_wakeref_t wakeref;
>  	int err = 0;
> -- 
> 2.20.1
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Re: [PATCH 3/6] drm/i915/selftests: Fixup atomic reset checking

[Chris Wilson]

Quoting Mika Kuoppala (2019-06-26 14:35:01)
> Chris Wilson <chris@chris-wilson.co.uk> writes:
> 
> > We require that the intel_gpu_reset() was atomic, not the whole of
> > i915_reset() which is guarded by a mutex. However, we do require that
> > i915_reset_engine() is atomic for use from within the submission tasklet.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > ---
> >  drivers/gpu/drm/i915/gt/selftest_reset.c | 65 +++++++++++++++++++++++-
> >  1 file changed, 63 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c b/drivers/gpu/drm/i915/gt/selftest_reset.c
> > index 64c2c8ab64ec..641cf3aee8d5 100644
> > --- a/drivers/gpu/drm/i915/gt/selftest_reset.c
> > +++ b/drivers/gpu/drm/i915/gt/selftest_reset.c
> > @@ -73,11 +73,13 @@ static int igt_atomic_reset(void *arg)
> >       for (p = igt_atomic_phases; p->name; p++) {
> >               GEM_TRACE("intel_gpu_reset under %s\n", p->name);
> >  
> > -             p->critical_section_begin();
> >               reset_prepare(i915);
> > +             p->critical_section_begin();
> > +
> >               err = intel_gpu_reset(i915, ALL_ENGINES);
> > -             reset_finish(i915);
> > +
> >               p->critical_section_end();
> > +             reset_finish(i915);
> >  
> >               if (err) {
> >                       pr_err("intel_gpu_reset failed under %s\n", p->name);
> > @@ -95,12 +97,71 @@ static int igt_atomic_reset(void *arg)
> >       return err;
> >  }
> >  
> > +static int igt_atomic_engine_reset(void *arg)
> > +{
> > +     struct drm_i915_private *i915 = arg;
> > +     const typeof(*igt_atomic_phases) *p;
> 
> I did admire the nastyness of this array.
> 
> > +     struct intel_engine_cs *engine;
> > +     enum intel_engine_id id;
> > +     int err = 0;
> > +
> > +     /* Check that the resets are usable from atomic context */
> > +
> > +     if (!intel_has_reset_engine(i915))
> > +             return 0;
> > +
> > +     if (USES_GUC_SUBMISSION(i915))
> > +             return 0;
> > +
> > +     intel_gt_pm_get(&i915->gt);
> > +     igt_global_reset_lock(i915);
> > +
> > +     /* Flush any requests before we get started and check basics */
> > +     if (!igt_force_reset(i915))
> > +             goto out_unlock;
> 
> I would still go out with error if the prerequisites
> are not met?

It's just so that the selftests report green except for the 1 or 2 that
explicitly report as red if the machine is terminally wedged at boot.

It's just damage control.
-Chris
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Re: [PATCH 3/6] drm/i915/selftests: Fixup atomic reset checking

[Mika Kuoppala]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> Quoting Mika Kuoppala (2019-06-26 14:35:01)
>> Chris Wilson <chris@chris-wilson.co.uk> writes:
>> 
>> > We require that the intel_gpu_reset() was atomic, not the whole of
>> > i915_reset() which is guarded by a mutex. However, we do require that
>> > i915_reset_engine() is atomic for use from within the submission tasklet.
>> >
>> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>> > ---
>> >  drivers/gpu/drm/i915/gt/selftest_reset.c | 65 +++++++++++++++++++++++-
>> >  1 file changed, 63 insertions(+), 2 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c b/drivers/gpu/drm/i915/gt/selftest_reset.c
>> > index 64c2c8ab64ec..641cf3aee8d5 100644
>> > --- a/drivers/gpu/drm/i915/gt/selftest_reset.c
>> > +++ b/drivers/gpu/drm/i915/gt/selftest_reset.c
>> > @@ -73,11 +73,13 @@ static int igt_atomic_reset(void *arg)
>> >       for (p = igt_atomic_phases; p->name; p++) {
>> >               GEM_TRACE("intel_gpu_reset under %s\n", p->name);
>> >  
>> > -             p->critical_section_begin();
>> >               reset_prepare(i915);
>> > +             p->critical_section_begin();
>> > +
>> >               err = intel_gpu_reset(i915, ALL_ENGINES);
>> > -             reset_finish(i915);
>> > +
>> >               p->critical_section_end();
>> > +             reset_finish(i915);
>> >  
>> >               if (err) {
>> >                       pr_err("intel_gpu_reset failed under %s\n", p->name);
>> > @@ -95,12 +97,71 @@ static int igt_atomic_reset(void *arg)
>> >       return err;
>> >  }
>> >  
>> > +static int igt_atomic_engine_reset(void *arg)
>> > +{
>> > +     struct drm_i915_private *i915 = arg;
>> > +     const typeof(*igt_atomic_phases) *p;
>> 
>> I did admire the nastyness of this array.
>> 
>> > +     struct intel_engine_cs *engine;
>> > +     enum intel_engine_id id;
>> > +     int err = 0;
>> > +
>> > +     /* Check that the resets are usable from atomic context */
>> > +
>> > +     if (!intel_has_reset_engine(i915))
>> > +             return 0;
>> > +
>> > +     if (USES_GUC_SUBMISSION(i915))
>> > +             return 0;
>> > +
>> > +     intel_gt_pm_get(&i915->gt);
>> > +     igt_global_reset_lock(i915);
>> > +
>> > +     /* Flush any requests before we get started and check basics */
>> > +     if (!igt_force_reset(i915))
>> > +             goto out_unlock;
>> 
>> I would still go out with error if the prerequisites
>> are not met?
>
> It's just so that the selftests report green except for the 1 or 2 that
> explicitly report as red if the machine is terminally wedged at boot.
>
> It's just damage control.

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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[PATCH 4/6] drm/i915: Add a wakeref getter for iff the wakeref is already active

[Chris Wilson]

For use in the next patch, we want to acquire a wakeref without having
to wake the device up -- i.e. only acquire the engine wakeref if the
engine is already active.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/intel_engine_pm.h |  7 ++++++-
 drivers/gpu/drm/i915/intel_wakeref.h      | 15 +++++++++++++++
 2 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.h b/drivers/gpu/drm/i915/gt/intel_engine_pm.h
index f3f5b031b4a1..7d057cdcd919 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.h
@@ -11,7 +11,6 @@
 #include "intel_wakeref.h"
 
 struct drm_i915_private;
-struct intel_engine_cs;
 
 void intel_engine_pm_get(struct intel_engine_cs *engine);
 void intel_engine_pm_put(struct intel_engine_cs *engine);
@@ -22,6 +21,12 @@ intel_engine_pm_is_awake(const struct intel_engine_cs *engine)
 	return intel_wakeref_is_active(&engine->wakeref);
 }
 
+static inline bool
+intel_engine_pm_get_if_awake(struct intel_engine_cs *engine)
+{
+	return intel_wakeref_get_if_active(&engine->wakeref);
+}
+
 void intel_engine_park(struct intel_engine_cs *engine);
 
 void intel_engine_init__pm(struct intel_engine_cs *engine);
diff --git a/drivers/gpu/drm/i915/intel_wakeref.h b/drivers/gpu/drm/i915/intel_wakeref.h
index f74272770a5c..1d6f5986e4e5 100644
--- a/drivers/gpu/drm/i915/intel_wakeref.h
+++ b/drivers/gpu/drm/i915/intel_wakeref.h
@@ -71,6 +71,21 @@ intel_wakeref_get(struct intel_runtime_pm *rpm,
 	return 0;
 }
 
+/**
+ * intel_wakeref_get_if_in_use: Acquire the wakeref
+ * @wf: the wakeref
+ *
+ * Acquire a hold on the wakeref, but only if the wakeref is already
+ * active.
+ *
+ * Returns: true if the wakeref was acquired, false otherwise.
+ */
+static inline bool
+intel_wakeref_get_if_active(struct intel_wakeref *wf)
+{
+	return atomic_inc_not_zero(&wf->count);
+}
+
 /**
  * intel_wakeref_put: Release the wakeref
  * @i915: the drm_i915_private device
-- 
2.20.1

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Re: [PATCH 4/6] drm/i915: Add a wakeref getter for iff the wakeref is already active

[Mika Kuoppala]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> For use in the next patch, we want to acquire a wakeref without having
> to wake the device up -- i.e. only acquire the engine wakeref if the
> engine is already active.
>

s/iff/if on the subject.

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/gt/intel_engine_pm.h |  7 ++++++-
>  drivers/gpu/drm/i915/intel_wakeref.h      | 15 +++++++++++++++
>  2 files changed, 21 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.h b/drivers/gpu/drm/i915/gt/intel_engine_pm.h
> index f3f5b031b4a1..7d057cdcd919 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_pm.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.h
> @@ -11,7 +11,6 @@
>  #include "intel_wakeref.h"
>  
>  struct drm_i915_private;
> -struct intel_engine_cs;
>  
>  void intel_engine_pm_get(struct intel_engine_cs *engine);
>  void intel_engine_pm_put(struct intel_engine_cs *engine);
> @@ -22,6 +21,12 @@ intel_engine_pm_is_awake(const struct intel_engine_cs *engine)
>  	return intel_wakeref_is_active(&engine->wakeref);
>  }
>  
> +static inline bool
> +intel_engine_pm_get_if_awake(struct intel_engine_cs *engine)
> +{
> +	return intel_wakeref_get_if_active(&engine->wakeref);
> +}
> +
>  void intel_engine_park(struct intel_engine_cs *engine);
>  
>  void intel_engine_init__pm(struct intel_engine_cs *engine);
> diff --git a/drivers/gpu/drm/i915/intel_wakeref.h b/drivers/gpu/drm/i915/intel_wakeref.h
> index f74272770a5c..1d6f5986e4e5 100644
> --- a/drivers/gpu/drm/i915/intel_wakeref.h
> +++ b/drivers/gpu/drm/i915/intel_wakeref.h
> @@ -71,6 +71,21 @@ intel_wakeref_get(struct intel_runtime_pm *rpm,
>  	return 0;
>  }
>  
> +/**
> + * intel_wakeref_get_if_in_use: Acquire the wakeref
> + * @wf: the wakeref
> + *
> + * Acquire a hold on the wakeref, but only if the wakeref is already
> + * active.
> + *
> + * Returns: true if the wakeref was acquired, false otherwise.
> + */
> +static inline bool
> +intel_wakeref_get_if_active(struct intel_wakeref *wf)
> +{
> +	return atomic_inc_not_zero(&wf->count);
> +}
> +
>  /**
>   * intel_wakeref_put: Release the wakeref
>   * @i915: the drm_i915_private device
> -- 
> 2.20.1
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Re: [PATCH 4/6] drm/i915: Add a wakeref getter for iff the wakeref is already active

[Chris Wilson]

Quoting Mika Kuoppala (2019-06-26 14:43:54)
> Chris Wilson <chris@chris-wilson.co.uk> writes:
> 
> > For use in the next patch, we want to acquire a wakeref without having
> > to wake the device up -- i.e. only acquire the engine wakeref if the
> > engine is already active.
> >
> 
> s/iff/if on the subject.

iff === if, and only if,
-Chris
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Re: [PATCH 4/6] drm/i915: Add a wakeref getter for iff the wakeref is already active

[Mika Kuoppala]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> Quoting Mika Kuoppala (2019-06-26 14:43:54)
>> Chris Wilson <chris@chris-wilson.co.uk> writes:
>> 
>> > For use in the next patch, we want to acquire a wakeref without having
>> > to wake the device up -- i.e. only acquire the engine wakeref if the
>> > engine is already active.
>> >
>> 
>> s/iff/if on the subject.
>
> iff === if, and only if,

til. I stand corrected, subject is fine and accurate.

-Mika

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[PATCH 5/6] drm/i915: Only recover active engines

[Chris Wilson]

If we issue a reset to a currently idle engine, leave it idle
afterwards. This is useful to excise a linkage between reset and the
shrinker. When waking the engine, we need to pin the default context
image which we use for overwriting a guilty context -- if the engine is
idle we do not need this pinned image! However, this pinning means that
waking the engine acquires the FS_RECLAIM, and so may trigger the
shrinker. The shrinker itself may need to wait upon the GPU to unbind
and object and so may require services of reset; ergo we should avoid
the engine wake up path.

The danger in skipping the recovery for idle engines is that we leave the
engine with no context defined, which may interfere with the operation of
the power context on some older platforms. In practice, we should only
be resetting an active GPU but it something to look out for on Ironlake
(if memory serves).

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/intel_reset.c    | 37 ++++++++++++++----------
 drivers/gpu/drm/i915/gt/selftest_reset.c |  6 ++--
 2 files changed, 26 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index 8ce92c51564e..e7cbd9cf85c1 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -678,7 +678,6 @@ static void reset_prepare_engine(struct intel_engine_cs *engine)
 	 * written to the powercontext is undefined and so we may lose
 	 * GPU state upon resume, i.e. fail to restart after a reset.
 	 */
-	intel_engine_pm_get(engine);
 	intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL);
 	engine->reset.prepare(engine);
 }
@@ -709,16 +708,21 @@ static void revoke_mmaps(struct drm_i915_private *i915)
 	}
 }
 
-static void reset_prepare(struct drm_i915_private *i915)
+static intel_engine_mask_t reset_prepare(struct drm_i915_private *i915)
 {
 	struct intel_engine_cs *engine;
+	intel_engine_mask_t awake = 0;
 	enum intel_engine_id id;
 
-	intel_gt_pm_get(&i915->gt);
-	for_each_engine(engine, i915, id)
+	for_each_engine(engine, i915, id) {
+		if (intel_engine_pm_get_if_awake(engine))
+			awake |= engine->mask;
 		reset_prepare_engine(engine);
+	}
 
 	intel_uc_reset_prepare(i915);
+
+	return awake;
 }
 
 static void gt_revoke(struct drm_i915_private *i915)
@@ -752,20 +756,22 @@ static int gt_reset(struct drm_i915_private *i915,
 static void reset_finish_engine(struct intel_engine_cs *engine)
 {
 	engine->reset.finish(engine);
-	intel_engine_pm_put(engine);
 	intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL);
+
+	intel_engine_signal_breadcrumbs(engine);
 }
 
-static void reset_finish(struct drm_i915_private *i915)
+static void reset_finish(struct drm_i915_private *i915,
+			 intel_engine_mask_t awake)
 {
 	struct intel_engine_cs *engine;
 	enum intel_engine_id id;
 
 	for_each_engine(engine, i915, id) {
 		reset_finish_engine(engine);
-		intel_engine_signal_breadcrumbs(engine);
+		if (awake & engine->mask)
+			intel_engine_pm_put(engine);
 	}
-	intel_gt_pm_put(&i915->gt);
 }
 
 static void nop_submit_request(struct i915_request *request)
@@ -789,6 +795,7 @@ static void __i915_gem_set_wedged(struct drm_i915_private *i915)
 {
 	struct i915_gpu_error *error = &i915->gpu_error;
 	struct intel_engine_cs *engine;
+	intel_engine_mask_t awake;
 	enum intel_engine_id id;
 
 	if (test_bit(I915_WEDGED, &error->flags))
@@ -808,7 +815,7 @@ static void __i915_gem_set_wedged(struct drm_i915_private *i915)
 	 * rolling the global seqno forward (since this would complete requests
 	 * for which we haven't set the fence error to EIO yet).
 	 */
-	reset_prepare(i915);
+	awake = reset_prepare(i915);
 
 	/* Even if the GPU reset fails, it should still stop the engines */
 	if (!INTEL_INFO(i915)->gpu_reset_clobbers_display)
@@ -832,7 +839,7 @@ static void __i915_gem_set_wedged(struct drm_i915_private *i915)
 	for_each_engine(engine, i915, id)
 		engine->cancel_requests(engine);
 
-	reset_finish(i915);
+	reset_finish(i915, awake);
 
 	GEM_TRACE("end\n");
 }
@@ -964,6 +971,7 @@ void i915_reset(struct drm_i915_private *i915,
 		const char *reason)
 {
 	struct i915_gpu_error *error = &i915->gpu_error;
+	intel_engine_mask_t awake;
 	int ret;
 
 	GEM_TRACE("flags=%lx\n", error->flags);
@@ -980,7 +988,7 @@ void i915_reset(struct drm_i915_private *i915,
 		dev_notice(i915->drm.dev, "Resetting chip for %s\n", reason);
 	error->reset_count++;
 
-	reset_prepare(i915);
+	awake = reset_prepare(i915);
 
 	if (!intel_has_gpu_reset(i915)) {
 		if (i915_modparams.reset)
@@ -1021,7 +1029,7 @@ void i915_reset(struct drm_i915_private *i915,
 	i915_queue_hangcheck(i915);
 
 finish:
-	reset_finish(i915);
+	reset_finish(i915, awake);
 unlock:
 	mutex_unlock(&error->wedge_mutex);
 	return;
@@ -1072,7 +1080,7 @@ int i915_reset_engine(struct intel_engine_cs *engine, const char *msg)
 	GEM_TRACE("%s flags=%lx\n", engine->name, error->flags);
 	GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));
 
-	if (!intel_engine_pm_is_awake(engine))
+	if (!intel_engine_pm_get_if_awake(engine))
 		return 0;
 
 	reset_prepare_engine(engine);
@@ -1107,12 +1115,11 @@ int i915_reset_engine(struct intel_engine_cs *engine, const char *msg)
 	 * process to program RING_MODE, HWSP and re-enable submission.
 	 */
 	ret = engine->resume(engine);
-	if (ret)
-		goto out;
 
 out:
 	intel_engine_cancel_stop_cs(engine);
 	reset_finish_engine(engine);
+	intel_engine_pm_put(engine);
 	return ret;
 }
 
diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c b/drivers/gpu/drm/i915/gt/selftest_reset.c
index 641cf3aee8d5..672e32e1ef95 100644
--- a/drivers/gpu/drm/i915/gt/selftest_reset.c
+++ b/drivers/gpu/drm/i915/gt/selftest_reset.c
@@ -71,15 +71,17 @@ static int igt_atomic_reset(void *arg)
 		goto unlock;
 
 	for (p = igt_atomic_phases; p->name; p++) {
+		intel_engine_mask_t awake;
+
 		GEM_TRACE("intel_gpu_reset under %s\n", p->name);
 
-		reset_prepare(i915);
+		awake = reset_prepare(i915);
 		p->critical_section_begin();
 
 		err = intel_gpu_reset(i915, ALL_ENGINES);
 
 		p->critical_section_end();
-		reset_finish(i915);
+		reset_finish(i915, awake);
 
 		if (err) {
 			pr_err("intel_gpu_reset failed under %s\n", p->name);
-- 
2.20.1

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Re: [PATCH 5/6] drm/i915: Only recover active engines

[Mika Kuoppala]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> If we issue a reset to a currently idle engine, leave it idle
> afterwards. This is useful to excise a linkage between reset and the
> shrinker. When waking the engine, we need to pin the default context

default context, kernel context, golden context...
if we ever revisit the naming, I will advocate for proto context.

> image which we use for overwriting a guilty context -- if the engine is
> idle we do not need this pinned image! However, this pinning means that
> waking the engine acquires the FS_RECLAIM, and so may trigger the
> shrinker. The shrinker itself may need to wait upon the GPU to unbind
> and object and so may require services of reset; ergo we should avoid
> the engine wake up path.
>
> The danger in skipping the recovery for idle engines is that we leave the
> engine with no context defined, which may interfere with the operation of
> the power context on some older platforms. In practice, we should only
> be resetting an active GPU but it something to look out for on Ironlake
> (if memory serves).
>

I will place my bet on bdw.

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/gt/intel_reset.c    | 37 ++++++++++++++----------
>  drivers/gpu/drm/i915/gt/selftest_reset.c |  6 ++--
>  2 files changed, 26 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
> index 8ce92c51564e..e7cbd9cf85c1 100644
> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> @@ -678,7 +678,6 @@ static void reset_prepare_engine(struct intel_engine_cs *engine)
>  	 * written to the powercontext is undefined and so we may lose
>  	 * GPU state upon resume, i.e. fail to restart after a reset.
>  	 */
> -	intel_engine_pm_get(engine);
>  	intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL);
>  	engine->reset.prepare(engine);
>  }
> @@ -709,16 +708,21 @@ static void revoke_mmaps(struct drm_i915_private *i915)
>  	}
>  }
>  
> -static void reset_prepare(struct drm_i915_private *i915)
> +static intel_engine_mask_t reset_prepare(struct drm_i915_private *i915)
>  {
>  	struct intel_engine_cs *engine;
> +	intel_engine_mask_t awake = 0;
>  	enum intel_engine_id id;
>  
> -	intel_gt_pm_get(&i915->gt);
> -	for_each_engine(engine, i915, id)
> +	for_each_engine(engine, i915, id) {
> +		if (intel_engine_pm_get_if_awake(engine))
> +			awake |= engine->mask;
>  		reset_prepare_engine(engine);
> +	}
>  
>  	intel_uc_reset_prepare(i915);
> +
> +	return awake;
>  }
>  
>  static void gt_revoke(struct drm_i915_private *i915)
> @@ -752,20 +756,22 @@ static int gt_reset(struct drm_i915_private *i915,
>  static void reset_finish_engine(struct intel_engine_cs *engine)
>  {
>  	engine->reset.finish(engine);
> -	intel_engine_pm_put(engine);
>  	intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL);
> +
> +	intel_engine_signal_breadcrumbs(engine);
>  }
>  
> -static void reset_finish(struct drm_i915_private *i915)
> +static void reset_finish(struct drm_i915_private *i915,
> +			 intel_engine_mask_t awake)
>  {
>  	struct intel_engine_cs *engine;
>  	enum intel_engine_id id;
>  
>  	for_each_engine(engine, i915, id) {
>  		reset_finish_engine(engine);
> -		intel_engine_signal_breadcrumbs(engine);
> +		if (awake & engine->mask)
> +			intel_engine_pm_put(engine);
>  	}
> -	intel_gt_pm_put(&i915->gt);
>  }
>  
>  static void nop_submit_request(struct i915_request *request)
> @@ -789,6 +795,7 @@ static void __i915_gem_set_wedged(struct drm_i915_private *i915)
>  {
>  	struct i915_gpu_error *error = &i915->gpu_error;
>  	struct intel_engine_cs *engine;
> +	intel_engine_mask_t awake;
>  	enum intel_engine_id id;
>  
>  	if (test_bit(I915_WEDGED, &error->flags))
> @@ -808,7 +815,7 @@ static void __i915_gem_set_wedged(struct drm_i915_private *i915)
>  	 * rolling the global seqno forward (since this would complete requests
>  	 * for which we haven't set the fence error to EIO yet).
>  	 */
> -	reset_prepare(i915);
> +	awake = reset_prepare(i915);
>  
>  	/* Even if the GPU reset fails, it should still stop the engines */
>  	if (!INTEL_INFO(i915)->gpu_reset_clobbers_display)
> @@ -832,7 +839,7 @@ static void __i915_gem_set_wedged(struct drm_i915_private *i915)
>  	for_each_engine(engine, i915, id)
>  		engine->cancel_requests(engine);
>  
> -	reset_finish(i915);
> +	reset_finish(i915, awake);
>  
>  	GEM_TRACE("end\n");
>  }
> @@ -964,6 +971,7 @@ void i915_reset(struct drm_i915_private *i915,
>  		const char *reason)
>  {
>  	struct i915_gpu_error *error = &i915->gpu_error;
> +	intel_engine_mask_t awake;
>  	int ret;
>  
>  	GEM_TRACE("flags=%lx\n", error->flags);
> @@ -980,7 +988,7 @@ void i915_reset(struct drm_i915_private *i915,
>  		dev_notice(i915->drm.dev, "Resetting chip for %s\n", reason);
>  	error->reset_count++;
>  
> -	reset_prepare(i915);
> +	awake = reset_prepare(i915);
>  
>  	if (!intel_has_gpu_reset(i915)) {
>  		if (i915_modparams.reset)
> @@ -1021,7 +1029,7 @@ void i915_reset(struct drm_i915_private *i915,
>  	i915_queue_hangcheck(i915);
>  
>  finish:
> -	reset_finish(i915);
> +	reset_finish(i915, awake);
>  unlock:
>  	mutex_unlock(&error->wedge_mutex);
>  	return;
> @@ -1072,7 +1080,7 @@ int i915_reset_engine(struct intel_engine_cs *engine, const char *msg)
>  	GEM_TRACE("%s flags=%lx\n", engine->name, error->flags);
>  	GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));
>  
> -	if (!intel_engine_pm_is_awake(engine))
> +	if (!intel_engine_pm_get_if_awake(engine))
>  		return 0;
>  
>  	reset_prepare_engine(engine);
> @@ -1107,12 +1115,11 @@ int i915_reset_engine(struct intel_engine_cs *engine, const char *msg)
>  	 * process to program RING_MODE, HWSP and re-enable submission.
>  	 */
>  	ret = engine->resume(engine);
> -	if (ret)
> -		goto out;
>  
>  out:
>  	intel_engine_cancel_stop_cs(engine);
>  	reset_finish_engine(engine);
> +	intel_engine_pm_put(engine);
>  	return ret;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c b/drivers/gpu/drm/i915/gt/selftest_reset.c
> index 641cf3aee8d5..672e32e1ef95 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_reset.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_reset.c
> @@ -71,15 +71,17 @@ static int igt_atomic_reset(void *arg)
>  		goto unlock;
>  
>  	for (p = igt_atomic_phases; p->name; p++) {
> +		intel_engine_mask_t awake;
> +
>  		GEM_TRACE("intel_gpu_reset under %s\n", p->name);
>  
> -		reset_prepare(i915);
> +		awake = reset_prepare(i915);
>  		p->critical_section_begin();
>  
>  		err = intel_gpu_reset(i915, ALL_ENGINES);
>  
>  		p->critical_section_end();
> -		reset_finish(i915);
> +		reset_finish(i915, awake);
>  
>  		if (err) {
>  			pr_err("intel_gpu_reset failed under %s\n", p->name);
> -- 
> 2.20.1
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Re: [PATCH 5/6] drm/i915: Only recover active engines

[Chris Wilson]

Quoting Mika Kuoppala (2019-06-26 15:44:56)
> Chris Wilson <chris@chris-wilson.co.uk> writes:
> 
> > If we issue a reset to a currently idle engine, leave it idle
> > afterwards. This is useful to excise a linkage between reset and the
> > shrinker. When waking the engine, we need to pin the default context
> 
> default context, kernel context, golden context...
> if we ever revisit the naming, I will advocate for proto context.

Not null_context or golden_context? :)

Or reset_context, or this_context_will_cause_gpu_hangs_in_mesa_context!
-Chris
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[PATCH 6/6] drm/i915: Lift intel_engines_resume() to callers

[Chris Wilson]

Since the reset path wants to recover the engines itself, it only wants
to reinitialise the hardware using i915_gem_init_hw(). Pull the call to
intel_engines_resume() to the module init/resume path so we can avoid it
during reset.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gem/i915_gem_pm.c    |   7 +-
 drivers/gpu/drm/i915/gt/intel_engine_pm.c |  24 ---
 drivers/gpu/drm/i915/gt/intel_engine_pm.h |   2 -
 drivers/gpu/drm/i915/gt/intel_gt_pm.c     |  21 ++-
 drivers/gpu/drm/i915/gt/intel_gt_pm.h     |   2 +-
 drivers/gpu/drm/i915/gt/intel_reset.c     |  21 ++-
 drivers/gpu/drm/i915/i915_gem.c           | 173 +++++++++-------------
 7 files changed, 116 insertions(+), 134 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
index 6b730bd4d72f..4d774376f5b8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
@@ -254,14 +254,15 @@ void i915_gem_resume(struct drm_i915_private *i915)
 	i915_gem_restore_gtt_mappings(i915);
 	i915_gem_restore_fences(i915);
 
+	if (i915_gem_init_hw(i915))
+		goto err_wedged;
+
 	/*
 	 * As we didn't flush the kernel context before suspend, we cannot
 	 * guarantee that the context image is complete. So let's just reset
 	 * it and start again.
 	 */
-	intel_gt_resume(&i915->gt);
-
-	if (i915_gem_init_hw(i915))
+	if (intel_gt_resume(&i915->gt))
 		goto err_wedged;
 
 	intel_uc_resume(i915);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index 5253c382034d..84e432abe8e0 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -142,27 +142,3 @@ void intel_engine_init__pm(struct intel_engine_cs *engine)
 {
 	intel_wakeref_init(&engine->wakeref);
 }
-
-int intel_engines_resume(struct drm_i915_private *i915)
-{
-	struct intel_engine_cs *engine;
-	enum intel_engine_id id;
-	int err = 0;
-
-	intel_gt_pm_get(&i915->gt);
-	for_each_engine(engine, i915, id) {
-		intel_engine_pm_get(engine);
-		engine->serial++; /* kernel context lost */
-		err = engine->resume(engine);
-		intel_engine_pm_put(engine);
-		if (err) {
-			dev_err(i915->drm.dev,
-				"Failed to restart %s (%d)\n",
-				engine->name, err);
-			break;
-		}
-	}
-	intel_gt_pm_put(&i915->gt);
-
-	return err;
-}
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.h b/drivers/gpu/drm/i915/gt/intel_engine_pm.h
index 7d057cdcd919..015ac72d7ad0 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.h
@@ -31,6 +31,4 @@ void intel_engine_park(struct intel_engine_cs *engine);
 
 void intel_engine_init__pm(struct intel_engine_cs *engine);
 
-int intel_engines_resume(struct drm_i915_private *i915);
-
 #endif /* INTEL_ENGINE_PM_H */
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index ec6b69d014b6..36ba80e6a0b7 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -5,6 +5,7 @@
  */
 
 #include "i915_drv.h"
+#include "intel_engine_pm.h"
 #include "intel_gt_pm.h"
 #include "intel_pm.h"
 #include "intel_wakeref.h"
@@ -122,10 +123,11 @@ void intel_gt_sanitize(struct intel_gt *gt, bool force)
 		intel_engine_reset(engine, false);
 }
 
-void intel_gt_resume(struct intel_gt *gt)
+int intel_gt_resume(struct intel_gt *gt)
 {
 	struct intel_engine_cs *engine;
 	enum intel_engine_id id;
+	int err = 0;
 
 	/*
 	 * After resume, we may need to poke into the pinned kernel
@@ -133,9 +135,12 @@ void intel_gt_resume(struct intel_gt *gt)
 	 * Only the kernel contexts should remain pinned over suspend,
 	 * allowing us to fixup the user contexts on their first pin.
 	 */
+	intel_gt_pm_get(gt);
 	for_each_engine(engine, gt->i915, id) {
 		struct intel_context *ce;
 
+		intel_engine_pm_get(engine);
+
 		ce = engine->kernel_context;
 		if (ce)
 			ce->ops->reset(ce);
@@ -143,5 +148,19 @@ void intel_gt_resume(struct intel_gt *gt)
 		ce = engine->preempt_context;
 		if (ce)
 			ce->ops->reset(ce);
+
+		engine->serial++; /* kernel context lost */
+		err = engine->resume(engine);
+
+		intel_engine_pm_put(engine);
+		if (err) {
+			dev_err(gt->i915->drm.dev,
+				"Failed to restart %s (%d)\n",
+				engine->name, err);
+			break;
+		}
 	}
+	intel_gt_pm_put(gt);
+
+	return err;
 }
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.h b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
index 4dbb92cf58d7..ba960e1fc209 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
@@ -22,6 +22,6 @@ void intel_gt_pm_put(struct intel_gt *gt);
 void intel_gt_pm_init_early(struct intel_gt *gt);
 
 void intel_gt_sanitize(struct intel_gt *gt, bool force);
-void intel_gt_resume(struct intel_gt *gt);
+int intel_gt_resume(struct intel_gt *gt);
 
 #endif /* INTEL_GT_PM_H */
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index e7cbd9cf85c1..adfdb908587f 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -949,6 +949,21 @@ static int do_reset(struct drm_i915_private *i915,
 	return gt_reset(i915, stalled_mask);
 }
 
+static int resume(struct drm_i915_private *i915)
+{
+	struct intel_engine_cs *engine;
+	enum intel_engine_id id;
+	int ret;
+
+	for_each_engine(engine, i915, id) {
+		ret = engine->resume(engine);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
 /**
  * i915_reset - reset chip after a hang
  * @i915: #drm_i915_private to reset
@@ -1023,9 +1038,13 @@ void i915_reset(struct drm_i915_private *i915,
 	if (ret) {
 		DRM_ERROR("Failed to initialise HW following reset (%d)\n",
 			  ret);
-		goto error;
+		goto taint;
 	}
 
+	ret = resume(i915);
+	if (ret)
+		goto taint;
+
 	i915_queue_hangcheck(i915);
 
 finish:
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index deecbe128e5b..5cc3a75d521a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -46,7 +46,6 @@
 #include "gem/i915_gem_ioctls.h"
 #include "gem/i915_gem_pm.h"
 #include "gem/i915_gemfs.h"
-#include "gt/intel_engine_pm.h"
 #include "gt/intel_gt.h"
 #include "gt/intel_gt_pm.h"
 #include "gt/intel_mocs.h"
@@ -1192,12 +1191,17 @@ static void init_unused_rings(struct intel_gt *gt)
 	}
 }
 
-static int init_hw(struct intel_gt *gt)
+int i915_gem_init_hw(struct drm_i915_private *i915)
 {
-	struct drm_i915_private *i915 = gt->i915;
-	struct intel_uncore *uncore = gt->uncore;
+	struct intel_uncore *uncore = &i915->uncore;
+	struct intel_gt *gt = &i915->gt;
 	int ret;
 
+	BUG_ON(!i915->kernel_context);
+	ret = i915_terminally_wedged(i915);
+	if (ret)
+		return ret;
+
 	gt->last_init_time = ktime_get();
 
 	/* Double layer security blanket, see i915_gem_init() */
@@ -1248,51 +1252,10 @@ static int init_hw(struct intel_gt *gt)
 
 	intel_mocs_init_l3cc_table(gt);
 
-	intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
-
-	return 0;
-
-out:
-	intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
-
-	return ret;
-}
-
-int i915_gem_init_hw(struct drm_i915_private *i915)
-{
-	struct intel_uncore *uncore = &i915->uncore;
-	int ret;
-
-	BUG_ON(!i915->kernel_context);
-	ret = i915_terminally_wedged(i915);
-	if (ret)
-		return ret;
-
-	/* Double layer security blanket, see i915_gem_init() */
-	intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
-
-	ret = init_hw(&i915->gt);
-	if (ret)
-		goto err_init;
-
-	/* Only when the HW is re-initialised, can we replay the requests */
-	ret = intel_engines_resume(i915);
-	if (ret)
-		goto err_engines;
-
-	intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
-
 	intel_engines_set_scheduler_caps(i915);
 
-	return 0;
-
-err_engines:
-	intel_uc_fini_hw(i915);
-err_init:
+out:
 	intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
-
-	intel_engines_set_scheduler_caps(i915);
-
 	return ret;
 }
 
@@ -1449,28 +1412,28 @@ static int intel_engines_verify_workarounds(struct drm_i915_private *i915)
 	return err;
 }
 
-int i915_gem_init(struct drm_i915_private *dev_priv)
+int i915_gem_init(struct drm_i915_private *i915)
 {
 	int ret;
 
 	/* We need to fallback to 4K pages if host doesn't support huge gtt. */
-	if (intel_vgpu_active(dev_priv) && !intel_vgpu_has_huge_gtt(dev_priv))
-		mkwrite_device_info(dev_priv)->page_sizes =
+	if (intel_vgpu_active(i915) && !intel_vgpu_has_huge_gtt(i915))
+		mkwrite_device_info(i915)->page_sizes =
 			I915_GTT_PAGE_SIZE_4K;
 
-	dev_priv->mm.unordered_timeline = dma_fence_context_alloc(1);
+	i915->mm.unordered_timeline = dma_fence_context_alloc(1);
 
-	intel_timelines_init(dev_priv);
+	intel_timelines_init(i915);
 
-	ret = i915_gem_init_userptr(dev_priv);
+	ret = i915_gem_init_userptr(i915);
 	if (ret)
 		return ret;
 
-	ret = intel_uc_init_misc(dev_priv);
+	ret = intel_uc_init_misc(i915);
 	if (ret)
 		return ret;
 
-	ret = intel_wopcm_init(&dev_priv->wopcm);
+	ret = intel_wopcm_init(&i915->wopcm);
 	if (ret)
 		goto err_uc_misc;
 
@@ -1480,50 +1443,55 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
 	 * we hold the forcewake during initialisation these problems
 	 * just magically go away.
 	 */
-	mutex_lock(&dev_priv->drm.struct_mutex);
-	intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
+	mutex_lock(&i915->drm.struct_mutex);
+	intel_uncore_forcewake_get(&i915->uncore, FORCEWAKE_ALL);
 
-	ret = i915_init_ggtt(dev_priv);
+	ret = i915_init_ggtt(i915);
 	if (ret) {
 		GEM_BUG_ON(ret == -EIO);
 		goto err_unlock;
 	}
 
-	ret = i915_gem_init_scratch(dev_priv,
-				    IS_GEN(dev_priv, 2) ? SZ_256K : PAGE_SIZE);
+	ret = i915_gem_init_scratch(i915,
+				    IS_GEN(i915, 2) ? SZ_256K : PAGE_SIZE);
 	if (ret) {
 		GEM_BUG_ON(ret == -EIO);
 		goto err_ggtt;
 	}
 
-	ret = intel_engines_setup(dev_priv);
+	ret = intel_engines_setup(i915);
 	if (ret) {
 		GEM_BUG_ON(ret == -EIO);
 		goto err_unlock;
 	}
 
-	ret = i915_gem_contexts_init(dev_priv);
+	ret = i915_gem_contexts_init(i915);
 	if (ret) {
 		GEM_BUG_ON(ret == -EIO);
 		goto err_scratch;
 	}
 
-	ret = intel_engines_init(dev_priv);
+	ret = intel_engines_init(i915);
 	if (ret) {
 		GEM_BUG_ON(ret == -EIO);
 		goto err_context;
 	}
 
-	intel_init_gt_powersave(dev_priv);
+	intel_init_gt_powersave(i915);
 
-	ret = intel_uc_init(dev_priv);
+	ret = intel_uc_init(i915);
 	if (ret)
 		goto err_pm;
 
-	ret = i915_gem_init_hw(dev_priv);
+	ret = i915_gem_init_hw(i915);
 	if (ret)
 		goto err_uc_init;
 
+	/* Only when the HW is re-initialised, can we replay the requests */
+	ret = intel_gt_resume(&i915->gt);
+	if (ret)
+		goto err_init_hw;
+
 	/*
 	 * Despite its name intel_init_clock_gating applies both display
 	 * clock gating workarounds; GT mmio workarounds and the occasional
@@ -1533,28 +1501,28 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
 	 *
 	 * FIXME: break up the workarounds and apply them at the right time!
 	 */
-	intel_init_clock_gating(dev_priv);
+	intel_init_clock_gating(i915);
 
-	ret = intel_engines_verify_workarounds(dev_priv);
+	ret = intel_engines_verify_workarounds(i915);
 	if (ret)
-		goto err_init_hw;
+		goto err_gt;
 
-	ret = __intel_engines_record_defaults(dev_priv);
+	ret = __intel_engines_record_defaults(i915);
 	if (ret)
-		goto err_init_hw;
+		goto err_gt;
 
 	if (i915_inject_load_failure()) {
 		ret = -ENODEV;
-		goto err_init_hw;
+		goto err_gt;
 	}
 
 	if (i915_inject_load_failure()) {
 		ret = -EIO;
-		goto err_init_hw;
+		goto err_gt;
 	}
 
-	intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
-	mutex_unlock(&dev_priv->drm.struct_mutex);
+	intel_uncore_forcewake_put(&i915->uncore, FORCEWAKE_ALL);
+	mutex_unlock(&i915->drm.struct_mutex);
 
 	return 0;
 
@@ -1564,66 +1532,67 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
 	 * HW as irrevisibly wedged, but keep enough state around that the
 	 * driver doesn't explode during runtime.
 	 */
-err_init_hw:
-	mutex_unlock(&dev_priv->drm.struct_mutex);
+err_gt:
+	mutex_unlock(&i915->drm.struct_mutex);
 
-	i915_gem_set_wedged(dev_priv);
-	i915_gem_suspend(dev_priv);
-	i915_gem_suspend_late(dev_priv);
+	i915_gem_set_wedged(i915);
+	i915_gem_suspend(i915);
+	i915_gem_suspend_late(i915);
 
-	i915_gem_drain_workqueue(dev_priv);
+	i915_gem_drain_workqueue(i915);
 
-	mutex_lock(&dev_priv->drm.struct_mutex);
-	intel_uc_fini_hw(dev_priv);
+	mutex_lock(&i915->drm.struct_mutex);
+err_init_hw:
+	intel_uc_fini_hw(i915);
 err_uc_init:
-	intel_uc_fini(dev_priv);
+	intel_uc_fini(i915);
 err_pm:
 	if (ret != -EIO) {
-		intel_cleanup_gt_powersave(dev_priv);
-		intel_engines_cleanup(dev_priv);
+		intel_cleanup_gt_powersave(i915);
+		intel_engines_cleanup(i915);
 	}
 err_context:
 	if (ret != -EIO)
-		i915_gem_contexts_fini(dev_priv);
+		i915_gem_contexts_fini(i915);
 err_scratch:
-	i915_gem_fini_scratch(dev_priv);
+	i915_gem_fini_scratch(i915);
 err_ggtt:
 err_unlock:
-	intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
-	mutex_unlock(&dev_priv->drm.struct_mutex);
+	intel_uncore_forcewake_put(&i915->uncore, FORCEWAKE_ALL);
+	mutex_unlock(&i915->drm.struct_mutex);
 
 err_uc_misc:
-	intel_uc_fini_misc(dev_priv);
+	intel_uc_fini_misc(i915);
 
 	if (ret != -EIO) {
-		i915_gem_cleanup_userptr(dev_priv);
-		intel_timelines_fini(dev_priv);
+		i915_gem_cleanup_userptr(i915);
+		intel_timelines_fini(i915);
 	}
 
 	if (ret == -EIO) {
-		mutex_lock(&dev_priv->drm.struct_mutex);
+		mutex_lock(&i915->drm.struct_mutex);
 
 		/*
 		 * Allow engine initialisation to fail by marking the GPU as
 		 * wedged. But we only want to do this where the GPU is angry,
 		 * for all other failure, such as an allocation failure, bail.
 		 */
-		if (!i915_reset_failed(dev_priv)) {
-			i915_load_error(dev_priv,
+		if (!i915_reset_failed(i915)) {
+			i915_load_error(i915,
 					"Failed to initialize GPU, declaring it wedged!\n");
-			i915_gem_set_wedged(dev_priv);
+			i915_gem_set_wedged(i915);
 		}
 
 		/* Minimal basic recovery for KMS */
-		ret = i915_ggtt_enable_hw(dev_priv);
-		i915_gem_restore_gtt_mappings(dev_priv);
-		i915_gem_restore_fences(dev_priv);
-		intel_init_clock_gating(dev_priv);
+		ret = i915_ggtt_enable_hw(i915);
+		i915_gem_restore_gtt_mappings(i915);
+		i915_gem_restore_fences(i915);
+		intel_init_clock_gating(i915);
 
-		mutex_unlock(&dev_priv->drm.struct_mutex);
+		mutex_unlock(&i915->drm.struct_mutex);
 	}
 
-	i915_gem_drain_freed_objects(dev_priv);
+	i915_gem_drain_freed_objects(i915);
 	return ret;
 }
 
-- 
2.20.1

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✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] drm/i915/selftests: Serialise nop reset with retirement

[Patchwork]

== Series Details ==

Series: series starting with [1/6] drm/i915/selftests: Serialise nop reset with retirement
URL   : https://patchwork.freedesktop.org/series/62756/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
679239f7e788 drm/i915/selftests: Serialise nop reset with retirement
4fed60f2c9df drm/i915/selftests: Drop manual request wakerefs around hangcheck
7e6ac9f43179 drm/i915/selftests: Fixup atomic reset checking
c846b259637d drm/i915: Add a wakeref getter for iff the wakeref is already active
5ca5fc0f3dc8 drm/i915: Only recover active engines
b6dd34a38751 drm/i915: Lift intel_engines_resume() to callers
-:215: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON()
#215: FILE: drivers/gpu/drm/i915/i915_gem.c:1200:
+	BUG_ON(!i915->kernel_context);

total: 0 errors, 1 warnings, 0 checks, 432 lines checked

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✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915/selftests: Serialise nop reset with retirement

[Patchwork]

== Series Details ==

Series: series starting with [1/6] drm/i915/selftests: Serialise nop reset with retirement
URL   : https://patchwork.freedesktop.org/series/62756/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6354 -> Patchwork_13434
====================================================

Summary
-------

  **WARNING**

  Minor unknown changes coming with Patchwork_13434 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_13434, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_13434:

### IGT changes ###

#### Warnings ####

  * igt@kms_chamelium@dp-crc-fast:
    - fi-kbl-7567u:       [FAIL][1] ([fdo#109635 ]) -> [TIMEOUT][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/fi-kbl-7567u/igt@kms_chamelium@dp-crc-fast.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/fi-kbl-7567u/igt@kms_chamelium@dp-crc-fast.html

  
Known issues
------------

  Here are the changes found in Patchwork_13434 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s4-devices:
    - fi-icl-u3:          [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/fi-icl-u3/igt@gem_exec_suspend@basic-s4-devices.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/fi-icl-u3/igt@gem_exec_suspend@basic-s4-devices.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size:
    - fi-kbl-7567u:       [PASS][5] -> [SKIP][6] ([fdo#109271]) +6 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/fi-kbl-7567u/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/fi-kbl-7567u/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html

  
#### Possible fixes ####

  * igt@i915_selftest@live_blt:
    - fi-icl-dsi:         [INCOMPLETE][7] ([fdo#107713]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/fi-icl-dsi/igt@i915_selftest@live_blt.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/fi-icl-dsi/igt@i915_selftest@live_blt.html

  * igt@kms_addfb_basic@small-bo:
    - fi-icl-u3:          [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/fi-icl-u3/igt@kms_addfb_basic@small-bo.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/fi-icl-u3/igt@kms_addfb_basic@small-bo.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-icl-u2:          [FAIL][11] ([fdo#103167]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html

  
#### Warnings ####

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-kbl-7567u:       [TIMEOUT][13] -> [FAIL][14] ([fdo#108767] / [fdo#109380])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/fi-kbl-7567u/igt@kms_chamelium@common-hpd-after-suspend.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/fi-kbl-7567u/igt@kms_chamelium@common-hpd-after-suspend.html

  
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#108767]: https://bugs.freedesktop.org/show_bug.cgi?id=108767
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109380]: https://bugs.freedesktop.org/show_bug.cgi?id=109380
  [fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635 


Participating hosts (54 -> 44)
------------------------------

  Missing    (10): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-hsw-peppy fi-byt-squawks fi-bsw-cyan fi-pnv-d510 fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_6354 -> Patchwork_13434

  CI_DRM_6354: e475c39caeca776a2645671bc184911107e3735c @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5068: 15ad664534413628f06c0f172aac11598bfdb895 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13434: b6dd34a38751e53cc3d049c4154ab07243bf75b0 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

b6dd34a38751 drm/i915: Lift intel_engines_resume() to callers
5ca5fc0f3dc8 drm/i915: Only recover active engines
c846b259637d drm/i915: Add a wakeref getter for iff the wakeref is already active
7e6ac9f43179 drm/i915/selftests: Fixup atomic reset checking
4fed60f2c9df drm/i915/selftests: Drop manual request wakerefs around hangcheck
679239f7e788 drm/i915/selftests: Serialise nop reset with retirement

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/
_______________________________________________
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Re: [PATCH 1/6] drm/i915/selftests: Serialise nop reset with retirement

[Mika Kuoppala]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> In order for the reset count to be accurate across our selftest, we need
> to prevent the background retire worker from modifying our expected
> state.
>

Ok, to summarize the irc discussion we had: The above holds true
for igt_reset_engine_nop only. As there is no race in
global reset path...currently.

But there is intent towards symmetry on both paths
so it makes sense to keep the tests aligned.

The commit msg could be enhanced on this regard.

Also while looking through this, we do increase
the reset_count rather early before the failpaths.
even with the resets disabled it gets incremented.
So now it is more of a attempted reset count.

But that is not a topic for this patch so,
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> index 3ceb397c8645..0e0b6c572ae9 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> @@ -398,6 +398,7 @@ static int igt_reset_nop(void *arg)
>  	count = 0;
>  	do {
>  		mutex_lock(&i915->drm.struct_mutex);
> +
>  		for_each_engine(engine, i915, id) {
>  			int i;
>  
> @@ -413,11 +414,12 @@ static int igt_reset_nop(void *arg)
>  				i915_request_add(rq);
>  			}
>  		}
> -		mutex_unlock(&i915->drm.struct_mutex);
>  
>  		igt_global_reset_lock(i915);
>  		i915_reset(i915, ALL_ENGINES, NULL);
>  		igt_global_reset_unlock(i915);
> +
> +		mutex_unlock(&i915->drm.struct_mutex);
>  		if (i915_reset_failed(i915)) {
>  			err = -EIO;
>  			break;
> @@ -511,9 +513,8 @@ static int igt_reset_nop_engine(void *arg)
>  
>  				i915_request_add(rq);
>  			}
> -			mutex_unlock(&i915->drm.struct_mutex);
> -
>  			err = i915_reset_engine(engine, NULL);
> +			mutex_unlock(&i915->drm.struct_mutex);
>  			if (err) {
>  				pr_err("i915_reset_engine failed\n");
>  				break;
> -- 
> 2.20.1
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Re: [PATCH 1/6] drm/i915/selftests: Serialise nop reset with retirement

[Chris Wilson]

Quoting Mika Kuoppala (2019-06-26 14:11:49)
> Chris Wilson <chris@chris-wilson.co.uk> writes:
> 
> > In order for the reset count to be accurate across our selftest, we need
> > to prevent the background retire worker from modifying our expected
> > state.
> >
> 
> Ok, to summarize the irc discussion we had: The above holds true
> for igt_reset_engine_nop only. As there is no race in
> global reset path...currently.
> 
> But there is intent towards symmetry on both paths
> so it makes sense to keep the tests aligned.
> 
> The commit msg could be enhanced on this regard.
> 
> Also while looking through this, we do increase
> the reset_count rather early before the failpaths.
> even with the resets disabled it gets incremented.
> So now it is more of a attempted reset count.

We don't expect it to fail, and if it does we wedge and report -EIO not
just a boring -EINVAL (or in theory we do -- that's generally the
approach we take elsewhere, treating the GPU going south as a more
severe failure than the test itself failing to fulfil its contract).
-Chris
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✓ Fi.CI.IGT: success for series starting with [1/6] drm/i915/selftests: Serialise nop reset with retirement

[Patchwork]

== Series Details ==

Series: series starting with [1/6] drm/i915/selftests: Serialise nop reset with retirement
URL   : https://patchwork.freedesktop.org/series/62756/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6354_full -> Patchwork_13434_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_13434_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_isolation@bcs0-s3:
    - shard-apl:          [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +5 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/shard-apl7/igt@gem_ctx_isolation@bcs0-s3.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/shard-apl5/igt@gem_ctx_isolation@bcs0-s3.html

  * igt@gem_exec_balancer@smoke:
    - shard-iclb:         [PASS][3] -> [SKIP][4] ([fdo#110854])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/shard-iclb4/igt@gem_exec_balancer@smoke.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/shard-iclb5/igt@gem_exec_balancer@smoke.html

  * igt@i915_selftest@mock_fence:
    - shard-iclb:         [PASS][5] -> [INCOMPLETE][6] ([fdo#107713])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/shard-iclb3/igt@i915_selftest@mock_fence.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/shard-iclb7/igt@i915_selftest@mock_fence.html

  * igt@i915_selftest@mock_requests:
    - shard-skl:          [PASS][7] -> [INCOMPLETE][8] ([fdo#110550])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/shard-skl5/igt@i915_selftest@mock_requests.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/shard-skl3/igt@i915_selftest@mock_requests.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-toggle:
    - shard-hsw:          [PASS][9] -> [SKIP][10] ([fdo#109271]) +11 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/shard-hsw8/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/shard-hsw1/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-skl:          [PASS][11] -> [INCOMPLETE][12] ([fdo#109507])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/shard-skl3/igt@kms_flip@flip-vs-suspend.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/shard-skl2/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite:
    - shard-iclb:         [PASS][13] -> [FAIL][14] ([fdo#103167]) +4 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-suspend:
    - shard-skl:          [PASS][15] -> [INCOMPLETE][16] ([fdo#104108] / [fdo#106978])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/shard-skl10/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/shard-skl2/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          [PASS][17] -> [FAIL][18] ([fdo#108145])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@kms_plane_lowres@pipe-a-tiling-y:
    - shard-iclb:         [PASS][19] -> [FAIL][20] ([fdo#103166])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/shard-iclb1/igt@kms_plane_lowres@pipe-a-tiling-y.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/shard-iclb4/igt@kms_plane_lowres@pipe-a-tiling-y.html

  * igt@kms_psr2_su@page_flip:
    - shard-iclb:         [PASS][21] -> [SKIP][22] ([fdo#109642])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/shard-iclb2/igt@kms_psr2_su@page_flip.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/shard-iclb6/igt@kms_psr2_su@page_flip.html

  * igt@kms_psr@no_drrs:
    - shard-iclb:         [PASS][23] -> [FAIL][24] ([fdo#108341])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/shard-iclb7/igt@kms_psr@no_drrs.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/shard-iclb1/igt@kms_psr@no_drrs.html

  * igt@kms_psr@psr2_sprite_blt:
    - shard-iclb:         [PASS][25] -> [SKIP][26] ([fdo#109441]) +1 similar issue
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/shard-iclb3/igt@kms_psr@psr2_sprite_blt.html

  * igt@kms_setmode@basic:
    - shard-kbl:          [PASS][27] -> [FAIL][28] ([fdo#99912])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/shard-kbl6/igt@kms_setmode@basic.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/shard-kbl3/igt@kms_setmode@basic.html

  
#### Possible fixes ####

  * igt@gem_eio@banned:
    - shard-skl:          [DMESG-WARN][29] ([fdo#110913 ]) -> [PASS][30] +1 similar issue
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/shard-skl1/igt@gem_eio@banned.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/shard-skl5/igt@gem_eio@banned.html

  * igt@gem_eio@execbuf:
    - shard-kbl:          [DMESG-WARN][31] ([fdo#110913 ]) -> [PASS][32] +5 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/shard-kbl6/igt@gem_eio@execbuf.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/shard-kbl6/igt@gem_eio@execbuf.html

  * igt@gem_partial_pwrite_pread@writes-after-reads-snoop:
    - shard-iclb:         [DMESG-WARN][33] ([fdo#110913 ]) -> [PASS][34] +10 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/shard-iclb8/igt@gem_partial_pwrite_pread@writes-after-reads-snoop.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/shard-iclb1/igt@gem_partial_pwrite_pread@writes-after-reads-snoop.html
    - shard-apl:          [DMESG-WARN][35] ([fdo#110913 ]) -> [PASS][36] +6 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/shard-apl8/igt@gem_partial_pwrite_pread@writes-after-reads-snoop.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/shard-apl1/igt@gem_partial_pwrite_pread@writes-after-reads-snoop.html

  * igt@gem_persistent_relocs@forked-faulting-reloc-thrash-inactive:
    - shard-glk:          [DMESG-WARN][37] ([fdo#110913 ]) -> [PASS][38] +7 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/shard-glk4/igt@gem_persistent_relocs@forked-faulting-reloc-thrash-inactive.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/shard-glk1/igt@gem_persistent_relocs@forked-faulting-reloc-thrash-inactive.html

  * igt@gem_softpin@noreloc-s3:
    - shard-apl:          [DMESG-WARN][39] ([fdo#108566]) -> [PASS][40] +2 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/shard-apl3/igt@gem_softpin@noreloc-s3.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/shard-apl2/igt@gem_softpin@noreloc-s3.html

  * igt@gem_tiled_swapping@non-threaded:
    - shard-glk:          [DMESG-WARN][41] ([fdo#108686]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/shard-glk6/igt@gem_tiled_swapping@non-threaded.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/shard-glk5/igt@gem_tiled_swapping@non-threaded.html
    - shard-hsw:          [FAIL][43] ([fdo#108686]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/shard-hsw4/igt@gem_tiled_swapping@non-threaded.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/shard-hsw6/igt@gem_tiled_swapping@non-threaded.html

  * igt@gem_userptr_blits@sync-unmap-cycles:
    - shard-snb:          [DMESG-WARN][45] ([fdo#110913 ]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/shard-snb4/igt@gem_userptr_blits@sync-unmap-cycles.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/shard-snb4/igt@gem_userptr_blits@sync-unmap-cycles.html
    - shard-hsw:          [DMESG-WARN][47] ([fdo#110913 ]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/shard-hsw5/igt@gem_userptr_blits@sync-unmap-cycles.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/shard-hsw5/igt@gem_userptr_blits@sync-unmap-cycles.html

  * igt@i915_pm_rc6_residency@rc6-accuracy:
    - shard-snb:          [SKIP][49] ([fdo#109271]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/shard-snb1/igt@i915_pm_rc6_residency@rc6-accuracy.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/shard-snb5/igt@i915_pm_rc6_residency@rc6-accuracy.html

  * igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic:
    - shard-skl:          [DMESG-WARN][51] ([fdo#105541]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/shard-skl9/igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/shard-skl6/igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic.html

  * igt@kms_flip@2x-plain-flip-ts-check-interruptible:
    - shard-hsw:          [SKIP][53] ([fdo#109271]) -> [PASS][54] +22 similar issues
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/shard-hsw1/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/shard-hsw7/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html

  * igt@kms_flip@modeset-vs-vblank-race:
    - shard-kbl:          [FAIL][55] ([fdo#103060]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/shard-kbl4/igt@kms_flip@modeset-vs-vblank-race.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/shard-kbl2/igt@kms_flip@modeset-vs-vblank-race.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack:
    - shard-iclb:         [FAIL][57] ([fdo#103167]) -> [PASS][58] +2 similar issues
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack.html

  * igt@kms_psr@psr2_cursor_blt:
    - shard-iclb:         [SKIP][59] ([fdo#109441]) -> [PASS][60] +1 similar issue
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/shard-iclb1/igt@kms_psr@psr2_cursor_blt.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html

  * igt@kms_sysfs_edid_timing:
    - shard-hsw:          [FAIL][61] ([fdo#100047]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/shard-hsw1/igt@kms_sysfs_edid_timing.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/shard-hsw7/igt@kms_sysfs_edid_timing.html

  * igt@kms_vblank@pipe-a-query-idle-hang:
    - shard-snb:          [DMESG-WARN][63] ([fdo#110789] / [fdo#110913 ]) -> [PASS][64] +4 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/shard-snb6/igt@kms_vblank@pipe-a-query-idle-hang.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/shard-snb2/igt@kms_vblank@pipe-a-query-idle-hang.html
    - shard-hsw:          [DMESG-WARN][65] ([fdo#110789] / [fdo#110913 ]) -> [PASS][66] +5 similar issues
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/shard-hsw8/igt@kms_vblank@pipe-a-query-idle-hang.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/shard-hsw1/igt@kms_vblank@pipe-a-query-idle-hang.html

  * igt@prime_busy@hang-default:
    - shard-glk:          [INCOMPLETE][67] ([fdo#103359] / [k.org#198133]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/shard-glk4/igt@prime_busy@hang-default.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/shard-glk3/igt@prime_busy@hang-default.html

  
#### Warnings ####

  * igt@gem_eio@in-flight-suspend:
    - shard-apl:          [DMESG-WARN][69] ([fdo#110913 ]) -> [DMESG-WARN][70] ([fdo#108566])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/shard-apl3/igt@gem_eio@in-flight-suspend.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/shard-apl2/igt@gem_eio@in-flight-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
    - shard-skl:          [FAIL][71] ([fdo#103167]) -> [FAIL][72] ([fdo#108040])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6354/shard-skl6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/shard-skl6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html

  
  [fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
  [fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#105541]: https://bugs.freedesktop.org/show_bug.cgi?id=105541
  [fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#110550]: https://bugs.freedesktop.org/show_bug.cgi?id=110550
  [fdo#110789]: https://bugs.freedesktop.org/show_bug.cgi?id=110789
  [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
  [fdo#110913 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110913 
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_6354 -> Patchwork_13434

  CI_DRM_6354: e475c39caeca776a2645671bc184911107e3735c @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5068: 15ad664534413628f06c0f172aac11598bfdb895 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13434: b6dd34a38751e53cc3d049c4154ab07243bf75b0 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13434/
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