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* [PATCH 1/3] drm/i915: Prepare for larger CSB status FIFO size
@ 2018-12-18 13:24 Mika Kuoppala
  2018-12-18 13:24 ` [PATCH 2/3] drm/i915/icl: Switch to using 12 deep CSB status FIFO Mika Kuoppala
                   ` (11 more replies)
  0 siblings, 12 replies; 21+ messages in thread
From: Mika Kuoppala @ 2018-12-18 13:24 UTC (permalink / raw)
  To: intel-gfx

Make csb entry count variable in preparation for larger
CSB status FIFO size found on gen11+ hardware.

v2: adapt to hwsp access only (Chris)
    non continuous mmio (Daniele)

Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_engine_cs.c  | 23 +++++++++++++----------
 drivers/gpu/drm/i915/intel_lrc.c        | 10 +++++++---
 drivers/gpu/drm/i915/intel_lrc.h        | 19 ++++++++++++-------
 drivers/gpu/drm/i915/intel_ringbuffer.h |  5 +++++
 4 files changed, 37 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 6f165f9ad2bf..f5960b3dc5d7 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1305,37 +1305,40 @@ static void intel_engine_print_registers(const struct intel_engine_cs *engine,
 	}
 
 	if (HAS_EXECLISTS(dev_priv)) {
-		const u32 *hws = &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
+		const u32 *hws = execlists->csb_status;
+		const u8 entries = execlists->csb_size;
 		unsigned int idx;
 		u8 read, write;
 
-		drm_printf(m, "\tExeclist status: 0x%08x %08x\n",
+		drm_printf(m, "\tExeclist status: 0x%08x %08x, entries %u\n",
 			   I915_READ(RING_EXECLIST_STATUS_LO(engine)),
-			   I915_READ(RING_EXECLIST_STATUS_HI(engine)));
+			   I915_READ(RING_EXECLIST_STATUS_HI(engine)),
+			   entries);
 
 		read = execlists->csb_head;
 		write = READ_ONCE(*execlists->csb_write);
 
 		drm_printf(m, "\tExeclist CSB read %d, write %d [mmio:%d], tasklet queued? %s (%s)\n",
 			   read, write,
-			   GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine))),
+			   I915_READ(RING_CONTEXT_STATUS_PTR(engine)) &
+			   GEN11_CSB_WRITE_PTR_MASK,
 			   yesno(test_bit(TASKLET_STATE_SCHED,
 					  &engine->execlists.tasklet.state)),
 			   enableddisabled(!atomic_read(&engine->execlists.tasklet.count)));
-		if (read >= GEN8_CSB_ENTRIES)
+		if (read >= entries)
 			read = 0;
-		if (write >= GEN8_CSB_ENTRIES)
+		if (write >= entries)
 			write = 0;
 		if (read > write)
-			write += GEN8_CSB_ENTRIES;
+			write += entries;
 		while (read < write) {
-			idx = ++read % GEN8_CSB_ENTRIES;
+			idx = ++read % entries;
 			drm_printf(m, "\tExeclist CSB[%d]: 0x%08x [mmio:0x%08x], context: %d [mmio:%d]\n",
 				   idx,
 				   hws[idx * 2],
-				   I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)),
+				   I915_READ(RING_CSB_LO(engine, idx)),
 				   hws[idx * 2 + 1],
-				   I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx)));
+				   I915_READ(RING_CSB_HI(engine, idx)));
 		}
 
 		rcu_read_lock();
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 1c9748f391fe..bd35ac3b7b77 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -760,7 +760,7 @@ invalidate_csb_entries(const u32 *first, const u32 *last)
 
 static void reset_csb_pointers(struct intel_engine_execlists *execlists)
 {
-	const unsigned int reset_value = GEN8_CSB_ENTRIES - 1;
+	const unsigned int reset_value = execlists->csb_size - 1;
 
 	/*
 	 * After a reset, the HW starts writing into CSB entry [0]. We
@@ -867,7 +867,7 @@ static void process_csb(struct intel_engine_cs *engine)
 	struct intel_engine_execlists * const execlists = &engine->execlists;
 	struct execlist_port *port = execlists->port;
 	const u32 * const buf = execlists->csb_status;
-	u8 head, tail;
+	u8 head, tail, entries;
 
 	/*
 	 * Note that csb_write, csb_status may be either in HWSP or mmio.
@@ -885,6 +885,8 @@ static void process_csb(struct intel_engine_cs *engine)
 	if (unlikely(head == tail))
 		return;
 
+	entries = execlists->csb_size;
+
 	/*
 	 * Hopefully paired with a wmb() in HW!
 	 *
@@ -900,7 +902,7 @@ static void process_csb(struct intel_engine_cs *engine)
 		unsigned int status;
 		unsigned int count;
 
-		if (++head == GEN8_CSB_ENTRIES)
+		if (++head == entries)
 			head = 0;
 
 		/*
@@ -2252,6 +2254,8 @@ static int logical_ring_init(struct intel_engine_cs *engine)
 	execlists->csb_write =
 		&engine->status_page.page_addr[intel_hws_csb_write_index(i915)];
 
+	execlists->csb_size = GEN8_CSB_ENTRIES;
+
 	reset_csb_pointers(execlists);
 
 	return 0;
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index f5a5502ecf70..206b0da6fbcc 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -36,9 +36,13 @@
 #define	  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT	(1 << 0)
 #define   CTX_CTRL_RS_CTX_ENABLE                (1 << 1)
 #define	  CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT	(1 << 2)
-#define RING_CONTEXT_STATUS_BUF_BASE(engine)	_MMIO((engine)->mmio_base + 0x370)
-#define RING_CONTEXT_STATUS_BUF_LO(engine, i)	_MMIO((engine)->mmio_base + 0x370 + (i) * 8)
-#define RING_CONTEXT_STATUS_BUF_HI(engine, i)	_MMIO((engine)->mmio_base + 0x370 + (i) * 8 + 4)
+
+#define _RING_CSB_OFFSET(i)			((i) < 6 ? \
+						 (0x370 + (i) * 8) : \
+						 (0x3c0 + ((i) - 6) * 8))
+#define RING_CSB_OFFSET(engine, i)		((engine)->mmio_base + _RING_CSB_OFFSET(i))
+#define RING_CSB_LO(engine, i)			_MMIO(RING_CSB_OFFSET(engine, i))
+#define RING_CSB_HI(engine, i)			_MMIO(RING_CSB_OFFSET(engine, i) + 4)
 #define RING_CONTEXT_STATUS_PTR(engine)		_MMIO((engine)->mmio_base + 0x3a0)
 #define RING_EXECLIST_SQ_CONTENTS(engine)	_MMIO((engine)->mmio_base + 0x510)
 #define RING_EXECLIST_CONTROL(engine)		_MMIO((engine)->mmio_base + 0x550)
@@ -55,10 +59,11 @@
 #define GEN8_CSB_PTR_MASK 0x7
 #define GEN8_CSB_READ_PTR_MASK (GEN8_CSB_PTR_MASK << 8)
 #define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0)
-#define GEN8_CSB_WRITE_PTR(csb_status) \
-	(((csb_status) & GEN8_CSB_WRITE_PTR_MASK) >> 0)
-#define GEN8_CSB_READ_PTR(csb_status) \
-	(((csb_status) & GEN8_CSB_READ_PTR_MASK) >> 8)
+
+#define GEN11_CSB_ENTRIES 12
+#define GEN11_CSB_PTR_MASK 0xf
+#define GEN11_CSB_READ_PTR_MASK (GEN11_CSB_PTR_MASK << 8)
+#define GEN11_CSB_WRITE_PTR_MASK (GEN11_CSB_PTR_MASK << 0)
 
 enum {
 	INTEL_CONTEXT_SCHEDULE_IN = 0,
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 1ae74e579386..64a54d8f9b2b 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -332,6 +332,11 @@ struct intel_engine_execlists {
 	 */
 	u32 preempt_complete_status;
 
+	/**
+	 * @csb_size: context status buffer FIFO size
+	 */
+	u8 csb_size;
+
 	/**
 	 * @csb_head: context status buffer head
 	 */
-- 
2.17.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 21+ messages in thread
* [PATCH 1/3] drm/i915: Prepare for larger CSB status FIFO size
@ 2018-11-27 17:38 Mika Kuoppala
  2018-11-27 17:46 ` Chris Wilson
  2018-11-27 19:00 ` Daniele Ceraolo Spurio
  0 siblings, 2 replies; 21+ messages in thread
From: Mika Kuoppala @ 2018-11-27 17:38 UTC (permalink / raw)
  To: intel-gfx

Make csb entry count variable in preparation for larger
CSB status FIFO size found on gen11+ hardware.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_engine_cs.c  | 16 +++++++++-------
 drivers/gpu/drm/i915/intel_lrc.c        | 24 +++++++++++++++++-------
 drivers/gpu/drm/i915/intel_lrc.h        |  9 +++++----
 drivers/gpu/drm/i915/intel_ringbuffer.h | 15 +++++++++------
 4 files changed, 40 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 759c0fd58f8c..218ef817da1d 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1347,27 +1347,29 @@ static void intel_engine_print_registers(const struct intel_engine_cs *engine,
 		unsigned int idx;
 		u8 read, write;
 
-		drm_printf(m, "\tExeclist status: 0x%08x %08x\n",
+		drm_printf(m, "\tExeclist status: 0x%08x %08x, entries %u\n",
 			   I915_READ(RING_EXECLIST_STATUS_LO(engine)),
-			   I915_READ(RING_EXECLIST_STATUS_HI(engine)));
+			   I915_READ(RING_EXECLIST_STATUS_HI(engine)),
+			   execlists->csb_entries);
 
 		read = execlists->csb_head;
 		write = READ_ONCE(*execlists->csb_write);
 
 		drm_printf(m, "\tExeclist CSB read %d, write %d [mmio:%d], tasklet queued? %s (%s)\n",
 			   read, write,
-			   GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine))),
+			   I915_READ(RING_CONTEXT_STATUS_PTR(engine)) &
+			   GEN11_CSB_WRITE_PTR_MASK,
 			   yesno(test_bit(TASKLET_STATE_SCHED,
 					  &engine->execlists.tasklet.state)),
 			   enableddisabled(!atomic_read(&engine->execlists.tasklet.count)));
-		if (read >= GEN8_CSB_ENTRIES)
+		if (read >= execlists->csb_entries)
 			read = 0;
-		if (write >= GEN8_CSB_ENTRIES)
+		if (write >= execlists->csb_entries)
 			write = 0;
 		if (read > write)
-			write += GEN8_CSB_ENTRIES;
+			write += execlists->csb_entries;
 		while (read < write) {
-			idx = ++read % GEN8_CSB_ENTRIES;
+			idx = ++read % execlists->csb_entries;
 			drm_printf(m, "\tExeclist CSB[%d]: 0x%08x [mmio:0x%08x], context: %d [mmio:%d]\n",
 				   idx,
 				   hws[idx * 2],
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 08fd9b12e4d7..5487fe496bb6 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -767,6 +767,7 @@ execlists_cancel_port_requests(struct intel_engine_execlists * const execlists)
 
 static void reset_csb_pointers(struct intel_engine_execlists *execlists)
 {
+	u32 reset_val;
 	/*
 	 * After a reset, the HW starts writing into CSB entry [0]. We
 	 * therefore have to set our HEAD pointer back one entry so that
@@ -776,8 +777,19 @@ static void reset_csb_pointers(struct intel_engine_execlists *execlists)
 	 * inline comparison of our cached head position against the last HW
 	 * write works even before the first interrupt.
 	 */
-	execlists->csb_head = execlists->csb_write_reset;
-	WRITE_ONCE(*execlists->csb_write, execlists->csb_write_reset);
+	execlists->csb_head = execlists->csb_entries - 1;
+
+	if (execlists_mmio_mode(execlists)) {
+		const u32 mask = execlists->csb_entries == GEN8_CSB_ENTRIES ?
+			GEN8_CSB_WRITE_PTR_MASK :
+			GEN11_CSB_WRITE_PTR_MASK;
+
+		reset_val = _MASKED_FIELD(mask, execlists->csb_head);
+	} else {
+		reset_val = execlists->csb_head;
+	}
+
+	WRITE_ONCE(*execlists->csb_write, reset_val);
 }
 
 static void nop_submission_tasklet(unsigned long data)
@@ -895,7 +907,7 @@ static void process_csb(struct intel_engine_cs *engine)
 		unsigned int status;
 		unsigned int count;
 
-		if (++head == GEN8_CSB_ENTRIES)
+		if (++head == execlists->csb_entries)
 			head = 0;
 
 		/*
@@ -2264,6 +2276,8 @@ static int logical_ring_init(struct intel_engine_cs *engine)
 			upper_32_bits(ce->lrc_desc);
 	}
 
+	execlists->csb_entries = GEN8_CSB_ENTRIES;
+
 	execlists->csb_read =
 		i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine));
 	if (csb_force_mmio(i915)) {
@@ -2271,16 +2285,12 @@ static int logical_ring_init(struct intel_engine_cs *engine)
 			(i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
 
 		execlists->csb_write = (u32 __force *)execlists->csb_read;
-		execlists->csb_write_reset =
-			_MASKED_FIELD(GEN8_CSB_WRITE_PTR_MASK,
-				      GEN8_CSB_ENTRIES - 1);
 	} else {
 		execlists->csb_status =
 			&engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
 
 		execlists->csb_write =
 			&engine->status_page.page_addr[intel_hws_csb_write_index(i915)];
-		execlists->csb_write_reset = GEN8_CSB_ENTRIES - 1;
 	}
 	reset_csb_pointers(execlists);
 
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index f5a5502ecf70..e865cba43a26 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -55,10 +55,11 @@
 #define GEN8_CSB_PTR_MASK 0x7
 #define GEN8_CSB_READ_PTR_MASK (GEN8_CSB_PTR_MASK << 8)
 #define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0)
-#define GEN8_CSB_WRITE_PTR(csb_status) \
-	(((csb_status) & GEN8_CSB_WRITE_PTR_MASK) >> 0)
-#define GEN8_CSB_READ_PTR(csb_status) \
-	(((csb_status) & GEN8_CSB_READ_PTR_MASK) >> 8)
+
+#define GEN11_CSB_ENTRIES 12
+#define GEN11_CSB_PTR_MASK 0xf
+#define GEN11_CSB_READ_PTR_MASK (GEN11_CSB_PTR_MASK << 8)
+#define GEN11_CSB_WRITE_PTR_MASK (GEN11_CSB_PTR_MASK << 0)
 
 enum {
 	INTEL_CONTEXT_SCHEDULE_IN = 0,
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 8a2270b209b0..d9520a52fe29 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -339,13 +339,9 @@ struct intel_engine_execlists {
 	u32 preempt_complete_status;
 
 	/**
-	 * @csb_write_reset: reset value for CSB write pointer
-	 *
-	 * As the CSB write pointer maybe either in HWSP or as a field
-	 * inside an mmio register, we want to reprogram it slightly
-	 * differently to avoid later confusion.
+	 * @csb_entries: number of CSB entries
 	 */
-	u32 csb_write_reset;
+	u8 csb_entries;
 
 	/**
 	 * @csb_head: context status buffer head
@@ -714,6 +710,13 @@ execlists_is_active(const struct intel_engine_execlists *execlists,
 	return test_bit(bit, (unsigned long *)&execlists->active);
 }
 
+static inline bool
+execlists_mmio_mode(const struct intel_engine_execlists * const execlists)
+{
+	return (unsigned long)execlists->csb_read ==
+		(unsigned long)execlists->csb_write;
+}
+
 void execlists_user_begin(struct intel_engine_execlists *execlists,
 			  const struct execlist_port *port);
 void execlists_user_end(struct intel_engine_execlists *execlists);
-- 
2.17.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 21+ messages in thread
end of thread, other threads:[~2018-12-19 16:48 UTC | newest]

Thread overview: 21+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-12-18 13:24 [PATCH 1/3] drm/i915: Prepare for larger CSB status FIFO size Mika Kuoppala
2018-12-18 13:24 ` [PATCH 2/3] drm/i915/icl: Switch to using 12 deep CSB status FIFO Mika Kuoppala
2018-12-18 13:24 ` [PATCH 3/3] drm/i915/icl: Introduce gen11 flush/invalidate Mika Kuoppala
2018-12-18 13:47 ` [PATCH 1/3] drm/i915: Prepare for larger CSB status FIFO size Chris Wilson
2018-12-19 12:27   ` Mika Kuoppala
2018-12-19 12:40     ` Chris Wilson
2018-12-19 13:17       ` Mika Kuoppala
2018-12-19 13:22         ` Mika Kuoppala
2018-12-19 13:26       ` Mika Kuoppala
2018-12-18 14:05 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] " Patchwork
2018-12-18 14:22 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-12-19 12:36 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915: Prepare for larger CSB status FIFO size (rev2) Patchwork
2018-12-19 13:05 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-12-19 13:29 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915: Prepare for larger CSB status FIFO size (rev3) Patchwork
2018-12-19 13:58 ` ✓ Fi.CI.BAT: success " Patchwork
2018-12-19 14:46 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915: Prepare for larger CSB status FIFO size (rev4) Patchwork
2018-12-19 15:08 ` ✓ Fi.CI.BAT: success " Patchwork
2018-12-19 16:48 ` ✗ Fi.CI.IGT: failure " Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2018-11-27 17:38 [PATCH 1/3] drm/i915: Prepare for larger CSB status FIFO size Mika Kuoppala
2018-11-27 17:46 ` Chris Wilson
2018-11-27 19:00 ` Daniele Ceraolo Spurio

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