Re: [PATCH] [V2] uartlite: move from byte accesses to word accesses

[Peter Korsgaard <jacmet@sunsite.dk>]

>>>>> "John" == John Linn <john.linn@xilinx.com> writes:

 John> Byte accesses for I/O devices in Xilinx IP are going to be less
 John> desired in the future such that the driver is being changed to
 John> use 32 bit accesses.

 John> This change facilitates using the uartlite IP over a PCIe bus
 John> which only allows 32 bit accesses.

 John> Signed-off-by: John Linn <john.linn@xilinx.com>
 John> ---
 John>  drivers/serial/uartlite.c |   36 ++++++++++++++++++------------------
 John>  1 files changed, 18 insertions(+), 18 deletions(-)

 John> diff --git a/drivers/serial/uartlite.c b/drivers/serial/uartlite.c
 John> index 377f271..9f83949 100644
 John> --- a/drivers/serial/uartlite.c
 John> +++ b/drivers/serial/uartlite.c
 John> @@ -86,7 +86,7 @@ static int ulite_receive(struct uart_port *port, int stat)
 John>  	/* stats */
 John>  	if (stat & ULITE_STATUS_RXVALID) {
 port-> icount.rx++;
 John> -		ch = readb(port->membase + ULITE_RX);
 John> +		ch = (u8)in_be32(port->membase + ULITE_RX);
 

I don't believe all those (u8) casts are needed (and they could
potentially mask away other problems in the future).

Other than that,

Acked-by: Peter Korsgaard <jacmet@sunsite.dk>

-- 
Bye, Peter Korsgaard