[PATCH] [V2] uartlite: move from byte accesses to word accesses

[PATCH] [V2] uartlite: move from byte accesses to word accesses

[John Linn]

Byte accesses for I/O devices in Xilinx IP are going to be less
desired in the future such that the driver is being changed to
use 32 bit accesses.

This change facilitates using the uartlite IP over a PCIe bus
which only allows 32 bit accesses.

Signed-off-by: John Linn <john.linn@xilinx.com>
---
 drivers/serial/uartlite.c |   36 ++++++++++++++++++------------------
 1 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/serial/uartlite.c b/drivers/serial/uartlite.c
index 377f271..9f83949 100644
--- a/drivers/serial/uartlite.c
+++ b/drivers/serial/uartlite.c
@@ -86,7 +86,7 @@ static int ulite_receive(struct uart_port *port, int stat)
 	/* stats */
 	if (stat & ULITE_STATUS_RXVALID) {
 		port->icount.rx++;
-		ch = readb(port->membase + ULITE_RX);
+		ch = (u8)in_be32(port->membase + ULITE_RX);
 
 		if (stat & ULITE_STATUS_PARITY)
 			port->icount.parity++;
@@ -131,7 +131,7 @@ static int ulite_transmit(struct uart_port *port, int stat)
 		return 0;
 
 	if (port->x_char) {
-		writeb(port->x_char, port->membase + ULITE_TX);
+		out_be32(port->membase + ULITE_TX, (u32)port->x_char);
 		port->x_char = 0;
 		port->icount.tx++;
 		return 1;
@@ -140,7 +140,7 @@ static int ulite_transmit(struct uart_port *port, int stat)
 	if (uart_circ_empty(xmit) || uart_tx_stopped(port))
 		return 0;
 
-	writeb(xmit->buf[xmit->tail], port->membase + ULITE_TX);
+	out_be32(port->membase + ULITE_TX, (u32)xmit->buf[xmit->tail]);
 	xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1);
 	port->icount.tx++;
 
@@ -157,7 +157,7 @@ static irqreturn_t ulite_isr(int irq, void *dev_id)
 	int busy, n = 0;
 
 	do {
-		int stat = readb(port->membase + ULITE_STATUS);
+		int stat = in_be32(port->membase + ULITE_STATUS);
 		busy  = ulite_receive(port, stat);
 		busy |= ulite_transmit(port, stat);
 		n++;
@@ -178,7 +178,7 @@ static unsigned int ulite_tx_empty(struct uart_port *port)
 	unsigned int ret;
 
 	spin_lock_irqsave(&port->lock, flags);
-	ret = readb(port->membase + ULITE_STATUS);
+	ret = in_be32(port->membase + ULITE_STATUS);
 	spin_unlock_irqrestore(&port->lock, flags);
 
 	return ret & ULITE_STATUS_TXEMPTY ? TIOCSER_TEMT : 0;
@@ -201,7 +201,7 @@ static void ulite_stop_tx(struct uart_port *port)
 
 static void ulite_start_tx(struct uart_port *port)
 {
-	ulite_transmit(port, readb(port->membase + ULITE_STATUS));
+	ulite_transmit(port, (u8)in_be32(port->membase + ULITE_STATUS));
 }
 
 static void ulite_stop_rx(struct uart_port *port)
@@ -230,17 +230,17 @@ static int ulite_startup(struct uart_port *port)
 	if (ret)
 		return ret;
 
-	writeb(ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX,
-	       port->membase + ULITE_CONTROL);
-	writeb(ULITE_CONTROL_IE, port->membase + ULITE_CONTROL);
+	out_be32(port->membase + ULITE_CONTROL,
+			ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX);
+	out_be32(port->membase + ULITE_CONTROL, ULITE_CONTROL_IE);
 
 	return 0;
 }
 
 static void ulite_shutdown(struct uart_port *port)
 {
-	writeb(0, port->membase + ULITE_CONTROL);
-	readb(port->membase + ULITE_CONTROL); /* dummy */
+	out_be32(port->membase + ULITE_CONTROL, 0);
+	in_be32(port->membase + ULITE_CONTROL); /* dummy */
 	free_irq(port->irq, port);
 }
 
@@ -348,11 +348,11 @@ static struct uart_ops ulite_ops = {
 static void ulite_console_wait_tx(struct uart_port *port)
 {
 	int i;
-	u8 val;
+	u32 val;
 
 	/* Spin waiting for TX fifo to have space available */
 	for (i = 0; i < 100000; i++) {
-		val = readb(port->membase + ULITE_STATUS);
+		val = in_be32(port->membase + ULITE_STATUS);
 		if ((val & ULITE_STATUS_TXFULL) == 0)
 			break;
 		cpu_relax();
@@ -362,7 +362,7 @@ static void ulite_console_wait_tx(struct uart_port *port)
 static void ulite_console_putchar(struct uart_port *port, int ch)
 {
 	ulite_console_wait_tx(port);
-	writeb(ch, port->membase + ULITE_TX);
+	out_be32(port->membase + ULITE_TX, (u32)ch);
 }
 
 static void ulite_console_write(struct console *co, const char *s,
@@ -379,8 +379,8 @@ static void ulite_console_write(struct console *co, const char *s,
 		spin_lock_irqsave(&port->lock, flags);
 
 	/* save and disable interrupt */
-	ier = readb(port->membase + ULITE_STATUS) & ULITE_STATUS_IE;
-	writeb(0, port->membase + ULITE_CONTROL);
+	ier = in_be32(port->membase + ULITE_STATUS) & ULITE_STATUS_IE;
+	out_be32(port->membase + ULITE_CONTROL, 0);
 
 	uart_console_write(port, s, count, ulite_console_putchar);
 
@@ -388,7 +388,7 @@ static void ulite_console_write(struct console *co, const char *s,
 
 	/* restore interrupt state */
 	if (ier)
-		writeb(ULITE_CONTROL_IE, port->membase + ULITE_CONTROL);
+		out_be32(port->membase + ULITE_CONTROL, ULITE_CONTROL_IE);
 
 	if (locked)
 		spin_unlock_irqrestore(&port->lock, flags);
@@ -601,7 +601,7 @@ ulite_of_probe(struct of_device *op, const struct of_device_id *match)
 
 	id = of_get_property(op->node, "port-number", NULL);
 
-	return ulite_assign(&op->dev, id ? *id : -1, res.start+3, irq);
+	return ulite_assign(&op->dev, id ? *id : -1, res.start, irq);
 }
 
 static int __devexit ulite_of_remove(struct of_device *op)
-- 
1.6.2.1



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RE: [PATCH] [V2] uartlite: move from byte accesses to word accesses

[John Linn]

> -----Original Message-----
> From: John Linn [mailto:john.linn@xilinx.com]
> Sent: Wednesday, January 20, 2010 5:07 PM
> To: linux-serial@vger.kernel.org; jacmet@sunsite.dk;
grant.likely@secretlab.ca;
> michal.simek@petalogix.com; john.williams@petalogix.com
> Cc: John Linn
> Subject: [PATCH] [V2] uartlite: move from byte accesses to word
accesses
> 
> Byte accesses for I/O devices in Xilinx IP are going to be less
> desired in the future such that the driver is being changed to
> use 32 bit accesses.
> 
> This change facilitates using the uartlite IP over a PCIe bus
> which only allows 32 bit accesses.
> 
> Signed-off-by: John Linn <john.linn@xilinx.com>
> ---

I apologize I forgot to put a note about how V2 is different.  The
commit message is the only thing that changed based on Peter's input.

Thanks,
John

>  drivers/serial/uartlite.c |   36 ++++++++++++++++++------------------
>  1 files changed, 18 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/serial/uartlite.c b/drivers/serial/uartlite.c
> index 377f271..9f83949 100644
> --- a/drivers/serial/uartlite.c
> +++ b/drivers/serial/uartlite.c
> @@ -86,7 +86,7 @@ static int ulite_receive(struct uart_port *port, int
stat)

<snip>

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Re: [PATCH] [V2] uartlite: move from byte accesses to word accesses

[Peter Korsgaard]

>>>>> "John" == John Linn <john.linn@xilinx.com> writes:

 John> Byte accesses for I/O devices in Xilinx IP are going to be less
 John> desired in the future such that the driver is being changed to
 John> use 32 bit accesses.

 John> This change facilitates using the uartlite IP over a PCIe bus
 John> which only allows 32 bit accesses.

 John> Signed-off-by: John Linn <john.linn@xilinx.com>
 John> ---
 John>  drivers/serial/uartlite.c |   36 ++++++++++++++++++------------------
 John>  1 files changed, 18 insertions(+), 18 deletions(-)

 John> diff --git a/drivers/serial/uartlite.c b/drivers/serial/uartlite.c
 John> index 377f271..9f83949 100644
 John> --- a/drivers/serial/uartlite.c
 John> +++ b/drivers/serial/uartlite.c
 John> @@ -86,7 +86,7 @@ static int ulite_receive(struct uart_port *port, int stat)
 John>  	/* stats */
 John>  	if (stat & ULITE_STATUS_RXVALID) {
 port-> icount.rx++;
 John> -		ch = readb(port->membase + ULITE_RX);
 John> +		ch = (u8)in_be32(port->membase + ULITE_RX);
 

I don't believe all those (u8) casts are needed (and they could
potentially mask away other problems in the future).

Other than that,

Acked-by: Peter Korsgaard <jacmet@sunsite.dk>

-- 
Bye, Peter Korsgaard

RE: [PATCH] [V2] uartlite: move from byte accesses to word accesses

[John Linn]

> -----Original Message-----
> From: Peter Korsgaard [mailto:jacmet@gmail.com] On Behalf Of Peter
Korsgaard
> Sent: Thursday, January 21, 2010 1:26 AM
> To: John Linn
> Cc: linux-serial@vger.kernel.org; grant.likely@secretlab.ca;
michal.simek@petalogix.com;
> john.williams@petalogix.com
> Subject: Re: [PATCH] [V2] uartlite: move from byte accesses to word
accesses
> 
> >>>>> "John" == John Linn <john.linn@xilinx.com> writes:
> 
>  John> Byte accesses for I/O devices in Xilinx IP are going to be less
>  John> desired in the future such that the driver is being changed to
>  John> use 32 bit accesses.
> 
>  John> This change facilitates using the uartlite IP over a PCIe bus
>  John> which only allows 32 bit accesses.
> 
>  John> Signed-off-by: John Linn <john.linn@xilinx.com>
>  John> ---
>  John>  drivers/serial/uartlite.c |   36
++++++++++++++++++------------------
>  John>  1 files changed, 18 insertions(+), 18 deletions(-)
> 
>  John> diff --git a/drivers/serial/uartlite.c
b/drivers/serial/uartlite.c
>  John> index 377f271..9f83949 100644
>  John> --- a/drivers/serial/uartlite.c
>  John> +++ b/drivers/serial/uartlite.c
>  John> @@ -86,7 +86,7 @@ static int ulite_receive(struct uart_port
*port, int stat)
>  John>  	/* stats */
>  John>  	if (stat & ULITE_STATUS_RXVALID) {
>  port-> icount.rx++;
>  John> -		ch = readb(port->membase + ULITE_RX);
>  John> +		ch = (u8)in_be32(port->membase + ULITE_RX);
> 
> 
> I don't believe all those (u8) casts are needed (and they could
> potentially mask away other problems in the future).
> 

I'll send out a V3 for the patch.  Sorry I dropped the ball and didn't
get this taken care of.

Thanks,
John

> Other than that,
> 
> Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
> 
> --
> Bye, Peter Korsgaard


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