* [PATCH 01/15] drm/i915/dsb: feature flag added for display state buffer.
2019-07-01 6:26 [PATCH 00/15] DSB enablement Animesh Manna
@ 2019-07-01 6:26 ` Animesh Manna
2019-07-01 6:26 ` [PATCH 02/15] drm/i915/dsb: DSB context creation Animesh Manna
` (18 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Animesh Manna @ 2019-07-01 6:26 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
From gen12 onwards Display State Buffer(DSB) is hardware capability
added which allows driver to batch submit display HW programming.
Feature flag has_dsb added to identify the driver/platform support
at runtime.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7e981b03face..ca6d3e2fe7a6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2287,6 +2287,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
+#define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb)
+
/*
* For now, anything with a GuC requires uCode loading, and then supports
* command submission once loaded. But these are logically independent
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index ddafc819bf30..7afe537f9335 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -132,6 +132,7 @@ enum intel_ppgtt_type {
func(has_csr); \
func(has_ddi); \
func(has_dp_mst); \
+ func(has_dsb); \
func(has_fbc); \
func(has_gmch); \
func(has_hotplug); \
--
2.21.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 02/15] drm/i915/dsb: DSB context creation.
2019-07-01 6:26 [PATCH 00/15] DSB enablement Animesh Manna
2019-07-01 6:26 ` [PATCH 01/15] drm/i915/dsb: feature flag added for display state buffer Animesh Manna
@ 2019-07-01 6:26 ` Animesh Manna
2019-07-01 6:26 ` [PATCH 03/15] drm/i915/dsb: single register write function for DSB Animesh Manna
` (17 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Animesh Manna @ 2019-07-01 6:26 UTC (permalink / raw)
To: intel-gfx; +Cc: Michel Thierry, Jani Nikula
The function will internally get the gem buffer from global GTT
which is mapped in cpu domain to feed the data + opcode for DSB engine.
Cc: Imre Deak <imre.deak@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_drv.h | 4 ++
drivers/gpu/drm/i915/intel_dsb.c | 65 ++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_dsb.h | 31 +++++++++++++++
5 files changed, 102 insertions(+)
create mode 100644 drivers/gpu/drm/i915/intel_dsb.c
create mode 100644 drivers/gpu/drm/i915/intel_dsb.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 3bd8f0349a8a..3416ba15b949 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -49,6 +49,7 @@ i915-y += i915_drv.o \
i915_sysfs.o \
intel_csr.o \
intel_device_info.o \
+ intel_dsb.o \
intel_pm.o \
intel_runtime_pm.o \
intel_sideband.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ca6d3e2fe7a6..237c17427780 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -76,6 +76,7 @@
#include "gt/intel_workarounds.h"
#include "intel_device_info.h"
+#include "intel_dsb.h"
#include "intel_runtime_pm.h"
#include "intel_uc.h"
#include "intel_uncore.h"
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1d58f7ec5d84..a05a047d78af 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -988,6 +988,10 @@ struct intel_crtc {
/* scalers available on this crtc */
int num_scalers;
+
+ /* per pipe DSB related info */
+ struct intel_dsb dsb[MAX_DSB_PER_PIPE];
+ int dsb_in_use;
};
struct intel_plane {
diff --git a/drivers/gpu/drm/i915/intel_dsb.c b/drivers/gpu/drm/i915/intel_dsb.c
new file mode 100644
index 000000000000..de6a8a901d88
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dsb.c
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ */
+
+#include "i915_drv.h"
+
+#define DSB_BUF_SIZE (2 * PAGE_SIZE)
+
+struct intel_dsb *
+intel_dsb_get(struct intel_crtc *crtc)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *i915 = to_i915(dev);
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ struct intel_dsb *dsb;
+ intel_wakeref_t wakeref;
+ int i;
+
+ WARN_ON(crtc->dsb_in_use >= MAX_DSB_PER_PIPE);
+
+ for (i = 0; i < MAX_DSB_PER_PIPE; i++) {
+ if (!crtc->dsb[i].cmd_buf) {
+ dsb = &crtc->dsb[i];
+ dsb->id = i;
+ }
+ }
+
+ dsb = &crtc->dsb[crtc->dsb_in_use];
+ dsb->crtc = crtc;
+ if (!HAS_DSB(i915))
+ return dsb;
+
+ wakeref = intel_runtime_pm_get(&i915->runtime_pm);
+ mutex_lock(&i915->drm.struct_mutex);
+
+ obj = i915_gem_object_create_shmem(i915, DSB_BUF_SIZE);
+ if (IS_ERR(obj))
+ goto err;
+
+ vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
+ if (IS_ERR(vma)) {
+ DRM_DEBUG_KMS("Vma creation failed.\n");
+ i915_gem_object_put(obj);
+ goto err;
+ }
+
+ dsb->cmd_buf = i915_gem_object_pin_map(vma->obj, I915_MAP_WC);
+ if (IS_ERR(dsb->cmd_buf)) {
+ DRM_DEBUG_KMS("Command buffer creation failed.\n");
+ dsb->cmd_buf = NULL;
+ goto err;
+ }
+ crtc->dsb_in_use++;
+ dsb->cmd_buf_head = (uintptr_t)i915_ggtt_offset(vma);
+ dsb->vma = vma;
+
+ memset(dsb->cmd_buf, 0, DSB_BUF_SIZE);
+err:
+ mutex_unlock(&i915->drm.struct_mutex);
+ intel_runtime_pm_put(&i915->runtime_pm, wakeref);
+ return dsb;
+}
diff --git a/drivers/gpu/drm/i915/intel_dsb.h b/drivers/gpu/drm/i915/intel_dsb.h
new file mode 100644
index 000000000000..50a2a6590a71
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dsb.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef _INTEL_DSB_H
+#define _INTEL_DSB_H
+
+struct intel_crtc;
+struct i915_vma;
+
+enum dsb_id {
+ INVALID_DSB = -1,
+ DSB1,
+ DSB2,
+ DSB3,
+ MAX_DSB_PER_PIPE
+};
+
+struct intel_dsb {
+ struct intel_crtc *crtc;
+ enum dsb_id id;
+ u32 *cmd_buf;
+ u32 cmd_buf_head;
+ struct i915_vma *vma;
+};
+
+struct intel_dsb *
+intel_dsb_get(struct intel_crtc *crtc);
+
+#endif
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 03/15] drm/i915/dsb: single register write function for DSB.
2019-07-01 6:26 [PATCH 00/15] DSB enablement Animesh Manna
2019-07-01 6:26 ` [PATCH 01/15] drm/i915/dsb: feature flag added for display state buffer Animesh Manna
2019-07-01 6:26 ` [PATCH 02/15] drm/i915/dsb: DSB context creation Animesh Manna
@ 2019-07-01 6:26 ` Animesh Manna
2019-07-01 6:26 ` [PATCH 04/15] drm/i915/dsb: Added enum for reg write capability Animesh Manna
` (16 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Animesh Manna @ 2019-07-01 6:26 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
DSB support single register write through opcode 0x1. Generic
api created which accumulate all single register write in a batch
buffer and once DSB is triggered, it will program all the registers
at the same time.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/intel_dsb.c | 36 ++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_dsb.h | 9 ++++++++
2 files changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsb.c b/drivers/gpu/drm/i915/intel_dsb.c
index de6a8a901d88..d9f51a28f8c4 100644
--- a/drivers/gpu/drm/i915/intel_dsb.c
+++ b/drivers/gpu/drm/i915/intel_dsb.c
@@ -8,6 +8,20 @@
#define DSB_BUF_SIZE (2 * PAGE_SIZE)
+/* DSB opcodes. */
+#define DSB_OPCODE_SHIFT 24
+#define DSB_OPCODE_NOOP 0x0
+#define DSB_OPCODE_MMIO_WRITE 0x1
+#define DSB_OPCODE_WAIT_FOR_US 0x2
+#define DSB_OPCODE_WAIT_FOR_LINES 0x3
+#define DSB_OPCODE_WAIT_FOR_VBLANK 0x4
+#define DSB_OPCODE_WAIT_FOR_SL_IN 0x5
+#define DSB_OPCODE_WAIT_FOR_SL_OUT 0x6
+#define DSB_OPCODE_GENERATE_INT 0x7
+#define DSB_OPCODE_INDEXED_WRITE 0x9
+#define DSB_OPCODE_POLL 0xA
+#define DSB_BYTE_EN (0xf << 20)
+
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc)
{
@@ -63,3 +77,25 @@ intel_dsb_get(struct intel_crtc *crtc)
intel_runtime_pm_put(&i915->runtime_pm, wakeref);
return dsb;
}
+
+void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
+{
+ struct intel_crtc *crtc = dsb->crtc;
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ u32 *buf = dsb->cmd_buf;
+
+ if (!buf) {
+ I915_WRITE(reg, val);
+ return;
+ }
+
+ if (WARN_ON(dsb->free_pos >= DSB_BUF_SIZE)) {
+ DRM_DEBUG_KMS("DSB buffer overflow.\n");
+ return;
+ }
+
+ buf[dsb->free_pos++] = val;
+ buf[dsb->free_pos++] = (DSB_OPCODE_MMIO_WRITE <<
+ DSB_OPCODE_SHIFT) | DSB_BYTE_EN |
+ i915_mmio_reg_offset(reg);
+}
diff --git a/drivers/gpu/drm/i915/intel_dsb.h b/drivers/gpu/drm/i915/intel_dsb.h
index 50a2a6590a71..2015c372b0d5 100644
--- a/drivers/gpu/drm/i915/intel_dsb.h
+++ b/drivers/gpu/drm/i915/intel_dsb.h
@@ -6,6 +6,8 @@
#ifndef _INTEL_DSB_H
#define _INTEL_DSB_H
+#include "i915_reg.h"
+
struct intel_crtc;
struct i915_vma;
@@ -23,9 +25,16 @@ struct intel_dsb {
u32 *cmd_buf;
u32 cmd_buf_head;
struct i915_vma *vma;
+
+ /*
+ * free_pos will point the first free entry position
+ * and help in calculating cmd_buf_tail.
+ */
+ int free_pos;
};
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc);
+void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
#endif
--
2.21.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 04/15] drm/i915/dsb: Added enum for reg write capability.
2019-07-01 6:26 [PATCH 00/15] DSB enablement Animesh Manna
` (2 preceding siblings ...)
2019-07-01 6:26 ` [PATCH 03/15] drm/i915/dsb: single register write function for DSB Animesh Manna
@ 2019-07-01 6:26 ` Animesh Manna
2019-07-01 6:26 ` [PATCH 05/15] drm/i915/dsb: Indexed register write function for DSB Animesh Manna
` (15 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Animesh Manna @ 2019-07-01 6:26 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
DSB can access specific register, To identify those register
which can be written through DSB, enum reg_write_cap is added
to hold the capability.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7e6009cefb18..b2e8349f3295 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -178,11 +178,22 @@
*/
#define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val))
+/*
+ * Added enum to hold the capability for those registers which can be written
+ * through DSB.
+ */
+enum reg_write_cap {
+ MMIO_WRITE,
+ DSB_WRITE,
+ DSB_INDEX_WRITE
+};
+
typedef struct {
u32 reg;
+ enum reg_write_cap cap;
} i915_reg_t;
-#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
+#define _MMIO(r, ...) ((const i915_reg_t){ .reg = (r), ##__VA_ARGS__})
#define INVALID_MMIO_REG _MMIO(0)
--
2.21.0
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 05/15] drm/i915/dsb: Indexed register write function for DSB.
2019-07-01 6:26 [PATCH 00/15] DSB enablement Animesh Manna
` (3 preceding siblings ...)
2019-07-01 6:26 ` [PATCH 04/15] drm/i915/dsb: Added enum for reg write capability Animesh Manna
@ 2019-07-01 6:26 ` Animesh Manna
2019-07-01 6:26 ` [PATCH 06/15] drm/i915/dsb: Update i915_write to call dsb-write Animesh Manna
` (14 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Animesh Manna @ 2019-07-01 6:26 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
DSB can program large set of data through indexed register write
(opcode 0x9) in one shot. Will be using for bulk register programming
e.g. gamma lut programming, HDR meta data programming.
Cc: Shashank Sharma <shashank.sharma@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/intel_dsb.c | 42 ++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_dsb.h | 6 +++++
2 files changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsb.c b/drivers/gpu/drm/i915/intel_dsb.c
index d9f51a28f8c4..31e1093977b6 100644
--- a/drivers/gpu/drm/i915/intel_dsb.c
+++ b/drivers/gpu/drm/i915/intel_dsb.c
@@ -21,6 +21,7 @@
#define DSB_OPCODE_INDEXED_WRITE 0x9
#define DSB_OPCODE_POLL 0xA
#define DSB_BYTE_EN (0xf << 20)
+#define DSB_REG_VALUE_MASK 0xfffff
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc)
@@ -78,6 +79,42 @@ intel_dsb_get(struct intel_crtc *crtc)
return dsb;
}
+static void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
+ u32 val)
+{
+ u32 *buf = dsb->cmd_buf;
+ u32 reg_val;
+
+ reg_val = buf[dsb->ins_start_offset + 1] & DSB_REG_VALUE_MASK;
+ if (reg_val != i915_mmio_reg_offset(reg)) {
+ /* Every instruction should be 8 byte aligned. */
+ if (dsb->free_pos & 0x1)
+ dsb->free_pos++;
+
+ /* Update the size. */
+ dsb->ins_start_offset = dsb->free_pos;
+ buf[dsb->free_pos++] = 1;
+
+ /* Update the opcode and reg. */
+ buf[dsb->free_pos++] = (DSB_OPCODE_INDEXED_WRITE <<
+ DSB_OPCODE_SHIFT) |
+ i915_mmio_reg_offset(reg);
+
+ /* Update the value. */
+ buf[dsb->free_pos++] = val;
+ } else {
+ /* Update the new value. */
+ buf[dsb->free_pos++] = val;
+
+ /* Update the size. */
+ buf[dsb->ins_start_offset]++;
+ }
+
+ /* if number of data words is odd, then the last dword should be 0.*/
+ if (dsb->free_pos & 0x1)
+ buf[dsb->free_pos] = 0;
+}
+
void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
{
struct intel_crtc *crtc = dsb->crtc;
@@ -94,6 +131,11 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
return;
}
+ if (reg.cap == DSB_INDEX_WRITE) {
+ intel_dsb_indexed_reg_write(dsb, reg, val);
+ return;
+ }
+
buf[dsb->free_pos++] = val;
buf[dsb->free_pos++] = (DSB_OPCODE_MMIO_WRITE <<
DSB_OPCODE_SHIFT) | DSB_BYTE_EN |
diff --git a/drivers/gpu/drm/i915/intel_dsb.h b/drivers/gpu/drm/i915/intel_dsb.h
index 2015c372b0d5..1fa893cc8c2e 100644
--- a/drivers/gpu/drm/i915/intel_dsb.h
+++ b/drivers/gpu/drm/i915/intel_dsb.h
@@ -31,6 +31,12 @@ struct intel_dsb {
* and help in calculating cmd_buf_tail.
*/
int free_pos;
+
+ /*
+ * ins_start_offset will help to store start address
+ * of the dsb instuction of auto-increment register.
+ */
+ u32 ins_start_offset;
};
struct intel_dsb *
--
2.21.0
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 06/15] drm/i915/dsb: Update i915_write to call dsb-write.
2019-07-01 6:26 [PATCH 00/15] DSB enablement Animesh Manna
` (4 preceding siblings ...)
2019-07-01 6:26 ` [PATCH 05/15] drm/i915/dsb: Indexed register write function for DSB Animesh Manna
@ 2019-07-01 6:26 ` Animesh Manna
2019-07-01 6:26 ` [PATCH 07/15] drm/i915/dsb: Register definition of DSB registers Animesh Manna
` (13 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Animesh Manna @ 2019-07-01 6:26 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Existing mmio-reg-write need intel_uncore handle which is part
of dev_priv structure and the same design is followed by
adding dsb handle in dev_priv for programming registers through DSB.
I915_WRITE is modified to check for register capability and call
dsb-reg-write based on its capability.
No changes in I915_READ definition as DSB do not have support to
read any register.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 6 +++++-
drivers/gpu/drm/i915/intel_dsb.c | 2 +-
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 237c17427780..cd0ebc62fa92 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1880,6 +1880,8 @@ struct drm_i915_private {
/* Mutex to protect the above hdcp component related values. */
struct mutex hdcp_comp_mutex;
+ struct intel_dsb *dsb;
+
/*
* NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
* will be rejected. Instead look for a better place.
@@ -2716,7 +2718,9 @@ extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
#define I915_READ(reg__) __I915_REG_OP(read, dev_priv, (reg__))
-#define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
+#define I915_WRITE(reg__, val__) \
+ (reg__.cap) ? intel_dsb_reg_write(dev_priv->dsb, (reg__), (val__)) : \
+ __I915_REG_OP(write, dev_priv, (reg__), (val__))
#define POSTING_READ(reg__) __I915_REG_OP(posting_read, dev_priv, (reg__))
diff --git a/drivers/gpu/drm/i915/intel_dsb.c b/drivers/gpu/drm/i915/intel_dsb.c
index 31e1093977b6..aa5361c2d70e 100644
--- a/drivers/gpu/drm/i915/intel_dsb.c
+++ b/drivers/gpu/drm/i915/intel_dsb.c
@@ -122,7 +122,7 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
u32 *buf = dsb->cmd_buf;
if (!buf) {
- I915_WRITE(reg, val);
+ intel_uncore_write(&(dev_priv)->uncore, reg, val);
return;
}
--
2.21.0
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 07/15] drm/i915/dsb: Register definition of DSB registers.
2019-07-01 6:26 [PATCH 00/15] DSB enablement Animesh Manna
` (5 preceding siblings ...)
2019-07-01 6:26 ` [PATCH 06/15] drm/i915/dsb: Update i915_write to call dsb-write Animesh Manna
@ 2019-07-01 6:26 ` Animesh Manna
2019-07-01 6:26 ` [PATCH 08/15] drm/i915/dsb: Check DSB engine status Animesh Manna
` (12 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Animesh Manna @ 2019-07-01 6:26 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Added key register definitions of DSB.
dsb-ctrl register is required to enable dsb-engine.
head-ptr register hold the head of buffer address from where the
execution will start.
Programming tail-ptr register is a trigger point to start execution.
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b2e8349f3295..8ef23e731cfe 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11485,4 +11485,19 @@ enum skl_power_gate {
#define PORT_TX_DFLEXDPCSSS _MMIO(FIA1_BASE + 0x00894)
#define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
+/* This register controls the Display State Buffer (DSB) engines. */
+#define _DSBSL_INSTANCE_BASE 0x70B00
+#define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \
+ (pipe) * 0x1000 + (id) * 100)
+#define DSB_HEAD_PTR(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
+#define DSB_TAIL_PTR(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
+#define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
+#define DSB_ENABLE (1 << 31)
+#define DSB_BUFFER_REITERATE (1 << 29)
+#define DSB_WAIT_FOR_VBLANK (1 << 28)
+#define DSB_WAIT_FOR_LINE_IN_RANGE (1 << 27)
+#define DSB_HALT (1 << 16)
+#define DSB_NON_POSTED_ENABLE (1 << 8)
+#define DSB_STATUS (1 << 0)
+
#endif /* _I915_REG_H_ */
--
2.21.0
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 08/15] drm/i915/dsb: Check DSB engine status.
2019-07-01 6:26 [PATCH 00/15] DSB enablement Animesh Manna
` (6 preceding siblings ...)
2019-07-01 6:26 ` [PATCH 07/15] drm/i915/dsb: Register definition of DSB registers Animesh Manna
@ 2019-07-01 6:26 ` Animesh Manna
2019-07-01 6:26 ` [PATCH 09/15] drm/i915/dsb: functions to enable/disable DSB engine Animesh Manna
` (11 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Animesh Manna @ 2019-07-01 6:26 UTC (permalink / raw)
To: intel-gfx; +Cc: Michel Thierry, Jani Nikula
As per bspec check for DSB status before programming any
of its register. Inline function added to check the dsb status.
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/intel_dsb.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsb.c b/drivers/gpu/drm/i915/intel_dsb.c
index aa5361c2d70e..9ad4fc8b9f1e 100644
--- a/drivers/gpu/drm/i915/intel_dsb.c
+++ b/drivers/gpu/drm/i915/intel_dsb.c
@@ -23,6 +23,15 @@
#define DSB_BYTE_EN (0xf << 20)
#define DSB_REG_VALUE_MASK 0xfffff
+static inline bool is_dsb_busy(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = dsb->crtc;
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+
+ return DSB_STATUS & I915_READ(DSB_CTRL(pipe, dsb->id));
+}
+
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc)
{
--
2.21.0
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 09/15] drm/i915/dsb: functions to enable/disable DSB engine.
2019-07-01 6:26 [PATCH 00/15] DSB enablement Animesh Manna
` (7 preceding siblings ...)
2019-07-01 6:26 ` [PATCH 08/15] drm/i915/dsb: Check DSB engine status Animesh Manna
@ 2019-07-01 6:26 ` Animesh Manna
2019-07-01 6:26 ` [PATCH 10/15] drm/i915/dsb: function to trigger workload execution of DSB Animesh Manna
` (10 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Animesh Manna @ 2019-07-01 6:26 UTC (permalink / raw)
To: intel-gfx; +Cc: Michel Thierry, Jani Nikula
DSB will be used for performance improvement for some special scenario.
DSB engine will be enabled based on need and after completion of its work
will be disabled. Api added for enable/disable operation by using DSB_CTRL
register.
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/intel_dsb.c | 40 ++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsb.c b/drivers/gpu/drm/i915/intel_dsb.c
index 9ad4fc8b9f1e..33c812019cec 100644
--- a/drivers/gpu/drm/i915/intel_dsb.c
+++ b/drivers/gpu/drm/i915/intel_dsb.c
@@ -32,6 +32,46 @@ static inline bool is_dsb_busy(struct intel_dsb *dsb)
return DSB_STATUS & I915_READ(DSB_CTRL(pipe, dsb->id));
}
+static bool intel_dsb_enable_engine(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = dsb->crtc;
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ u32 dsb_ctrl;
+
+ dsb_ctrl = I915_READ(DSB_CTRL(pipe, dsb->id));
+
+ if (DSB_STATUS & dsb_ctrl) {
+ DRM_DEBUG_KMS("DSB engine is busy.\n");
+ return false;
+ }
+
+ dsb_ctrl |= DSB_ENABLE;
+ I915_WRITE(DSB_CTRL(pipe, dsb->id), dsb_ctrl);
+
+ return true;
+}
+
+static bool intel_dsb_disable_engine(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = dsb->crtc;
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ u32 dsb_ctrl;
+
+ dsb_ctrl = I915_READ(DSB_CTRL(pipe, dsb->id));
+
+ if (DSB_STATUS & dsb_ctrl) {
+ DRM_DEBUG_KMS("DSB engine is busy.\n");
+ return false;
+ }
+
+ dsb_ctrl &= ~DSB_ENABLE;
+ I915_WRITE(DSB_CTRL(pipe, dsb->id), dsb_ctrl);
+
+ return true;
+}
+
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc)
{
--
2.21.0
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 10/15] drm/i915/dsb: function to trigger workload execution of DSB.
2019-07-01 6:26 [PATCH 00/15] DSB enablement Animesh Manna
` (8 preceding siblings ...)
2019-07-01 6:26 ` [PATCH 09/15] drm/i915/dsb: functions to enable/disable DSB engine Animesh Manna
@ 2019-07-01 6:26 ` Animesh Manna
2019-07-01 6:26 ` [PATCH 11/15] drm/i915/dsb: function to destroy DSB context Animesh Manna
` (9 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Animesh Manna @ 2019-07-01 6:26 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Batch buffer will be created through dsb-reg-write function which can have
single/multiple request based on usecase and once the buffer is ready
commit function will trigger the execution of the batch buffer. All
the registers will be updated simultaneously.
Cc: Imre Deak <imre.deak@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/intel_dsb.c | 43 ++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_dsb.h | 1 +
2 files changed, 44 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsb.c b/drivers/gpu/drm/i915/intel_dsb.c
index 33c812019cec..0270f4fef600 100644
--- a/drivers/gpu/drm/i915/intel_dsb.c
+++ b/drivers/gpu/drm/i915/intel_dsb.c
@@ -190,3 +190,46 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
DSB_OPCODE_SHIFT) | DSB_BYTE_EN |
i915_mmio_reg_offset(reg);
}
+
+void intel_dsb_commit(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = dsb->crtc;
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ enum pipe pipe = crtc->pipe;
+ u32 cmd_buf_tail, cmd_buf_size;
+
+ if (!dsb->free_pos)
+ return;
+
+ if (!intel_dsb_enable_engine(dsb))
+ goto reset;
+
+ if (is_dsb_busy(dsb)) {
+ DRM_DEBUG_KMS("HEAD_PTR write failed - dsb engine is busy.\n");
+ goto reset;
+ }
+ I915_WRITE(DSB_HEAD_PTR(pipe, dsb->id), dsb->cmd_buf_head);
+
+ cmd_buf_size = dsb->free_pos * 4;
+ cmd_buf_tail = round_up((dsb->cmd_buf_head + cmd_buf_size),
+ CACHELINE_BYTES);
+
+ if (is_dsb_busy(dsb)) {
+ DRM_DEBUG_KMS("TAIL_PTR write failed - dsb engine is busy.\n");
+ goto reset;
+ }
+ DRM_DEBUG_KMS("DSB execution started - buf-size %u, head 0x%x,"
+ "tail 0x%x\n", cmd_buf_size, dsb->cmd_buf_head,
+ cmd_buf_tail);
+ I915_WRITE(DSB_TAIL_PTR(pipe, dsb->id), cmd_buf_tail);
+ if (wait_for(!is_dsb_busy(dsb), 1)) {
+ DRM_ERROR("Timed out waiting for DSB workload completion.\n");
+ goto reset;
+ }
+
+reset:
+ memset(dsb->cmd_buf, 0, DSB_BUF_SIZE);
+ dsb->free_pos = 0;
+ intel_dsb_disable_engine(dsb);
+}
diff --git a/drivers/gpu/drm/i915/intel_dsb.h b/drivers/gpu/drm/i915/intel_dsb.h
index 1fa893cc8c2e..7330add3c96f 100644
--- a/drivers/gpu/drm/i915/intel_dsb.h
+++ b/drivers/gpu/drm/i915/intel_dsb.h
@@ -42,5 +42,6 @@ struct intel_dsb {
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc);
void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
+void intel_dsb_commit(struct intel_dsb *dsb);
#endif
--
2.21.0
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 11/15] drm/i915/dsb: function to destroy DSB context.
2019-07-01 6:26 [PATCH 00/15] DSB enablement Animesh Manna
` (9 preceding siblings ...)
2019-07-01 6:26 ` [PATCH 10/15] drm/i915/dsb: function to trigger workload execution of DSB Animesh Manna
@ 2019-07-01 6:26 ` Animesh Manna
2019-07-01 6:26 ` [PATCH 12/15] drm/i915/dsb: Early prepare of dsb context Animesh Manna
` (8 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Animesh Manna @ 2019-07-01 6:26 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Freed the gem object after completion of dsb workload.
Cc: Shashank Sharma <shashank.sharma@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/intel_dsb.c | 16 ++++++++++++++++
drivers/gpu/drm/i915/intel_dsb.h | 1 +
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsb.c b/drivers/gpu/drm/i915/intel_dsb.c
index 0270f4fef600..dddaae27d7b5 100644
--- a/drivers/gpu/drm/i915/intel_dsb.c
+++ b/drivers/gpu/drm/i915/intel_dsb.c
@@ -233,3 +233,19 @@ void intel_dsb_commit(struct intel_dsb *dsb)
dsb->free_pos = 0;
intel_dsb_disable_engine(dsb);
}
+
+void intel_dsb_put(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = dsb->crtc;
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct i915_vma *vma = dsb->vma;
+
+ if (dsb->cmd_buf) {
+ mutex_lock(&i915->drm.struct_mutex);
+ crtc->dsb_in_use--;
+ i915_gem_object_unpin_map(vma->obj);
+ i915_vma_unpin_and_release(&vma, 0);
+ dsb->cmd_buf = NULL;
+ mutex_unlock(&i915->drm.struct_mutex);
+ }
+}
diff --git a/drivers/gpu/drm/i915/intel_dsb.h b/drivers/gpu/drm/i915/intel_dsb.h
index 7330add3c96f..7b94fd9bc067 100644
--- a/drivers/gpu/drm/i915/intel_dsb.h
+++ b/drivers/gpu/drm/i915/intel_dsb.h
@@ -43,5 +43,6 @@ struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc);
void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
void intel_dsb_commit(struct intel_dsb *dsb);
+void intel_dsb_put(struct intel_dsb *dsb);
#endif
--
2.21.0
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 12/15] drm/i915/dsb: Early prepare of dsb context.
2019-07-01 6:26 [PATCH 00/15] DSB enablement Animesh Manna
` (10 preceding siblings ...)
2019-07-01 6:26 ` [PATCH 11/15] drm/i915/dsb: function to destroy DSB context Animesh Manna
@ 2019-07-01 6:26 ` Animesh Manna
2019-07-01 6:26 ` [PATCH 13/15] drm/i915/dsb: Cleanup of DSB context Animesh Manna
` (7 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Animesh Manna @ 2019-07-01 6:26 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
The dsb get call added part of the prepare so that we don't
have things that can fail in the commit proper.
The allocated dsb-context will be tracked under intel_crtc_state
instead of intel_crtc per atomic-commit.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 17 +++++++++++++++++
drivers/gpu/drm/i915/intel_drv.h | 2 ++
2 files changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e55bd75528c1..6dea61689290 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13708,6 +13708,22 @@ static void skl_update_crtcs(struct drm_atomic_state *state)
icl_dbuf_slices_update(dev_priv, required_slices);
}
+static void intel_prepare_dsb(struct drm_atomic_state *state)
+{
+ struct drm_crtc_state *crtc_state;
+ struct drm_crtc *crtc;
+ struct intel_crtc_state *config;
+ int i;
+
+ if (!state)
+ return;
+
+ for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
+ config = to_intel_crtc_state(crtc_state);
+ config->dsb = intel_dsb_get(to_intel_crtc(crtc));
+ }
+}
+
static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
{
struct intel_atomic_state *state, *next;
@@ -14074,6 +14090,7 @@ static int intel_atomic_commit(struct drm_device *dev,
dev_priv->wm.distrust_bios_wm = false;
intel_shared_dpll_swap_state(state);
intel_atomic_track_fbs(state);
+ intel_prepare_dsb(state);
if (intel_state->modeset) {
memcpy(dev_priv->min_cdclk, intel_state->min_cdclk,
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a05a047d78af..bfea0e21de63 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -946,6 +946,8 @@ struct intel_crtc_state {
/* Forward Error correction State */
bool fec_enable;
+
+ struct intel_dsb *dsb;
};
struct intel_crtc {
--
2.21.0
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 13/15] drm/i915/dsb: Cleanup of DSB context.
2019-07-01 6:26 [PATCH 00/15] DSB enablement Animesh Manna
` (11 preceding siblings ...)
2019-07-01 6:26 ` [PATCH 12/15] drm/i915/dsb: Early prepare of dsb context Animesh Manna
@ 2019-07-01 6:26 ` Animesh Manna
2019-07-01 6:26 ` [PATCH 14/15] drm/i915/dsb: Documentation for DSB Animesh Manna
` (6 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Animesh Manna @ 2019-07-01 6:26 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
DSB context destroyed using intel_dsb_put() in cleanup function.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6dea61689290..7c2dabc46d1f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13724,6 +13724,22 @@ static void intel_prepare_dsb(struct drm_atomic_state *state)
}
}
+static void intel_cleanup_dsb(struct drm_atomic_state *state)
+{
+ struct drm_crtc_state *crtc_state;
+ struct drm_crtc *crtc;
+ struct intel_crtc_state *config;
+ int i;
+
+ if (!state)
+ return;
+
+ for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
+ config = to_intel_crtc_state(crtc_state);
+ intel_dsb_put(config->dsb);
+ }
+}
+
static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
{
struct intel_atomic_state *state, *next;
@@ -13772,6 +13788,7 @@ static void intel_atomic_cleanup_work(struct work_struct *work)
container_of(work, struct drm_atomic_state, commit_work);
struct drm_i915_private *i915 = to_i915(state->dev);
+ intel_cleanup_dsb(state);
drm_atomic_helper_cleanup_planes(&i915->drm, state);
drm_atomic_helper_commit_cleanup_done(state);
drm_atomic_state_put(state);
--
2.21.0
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 14/15] drm/i915/dsb: Documentation for DSB.
2019-07-01 6:26 [PATCH 00/15] DSB enablement Animesh Manna
` (12 preceding siblings ...)
2019-07-01 6:26 ` [PATCH 13/15] drm/i915/dsb: Cleanup of DSB context Animesh Manna
@ 2019-07-01 6:26 ` Animesh Manna
2019-07-01 6:26 ` [PATCH 15/15] drm/i915/dsb: Enable gamma lut programming using DSB Animesh Manna
` (5 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Animesh Manna @ 2019-07-01 6:26 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Added docbook info regarding Display State Buffer(DSB) which
is added from gen12 onwards to batch submit display HW programming.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
Documentation/gpu/i915.rst | 9 ++++++
drivers/gpu/drm/i915/intel_dsb.c | 54 ++++++++++++++++++++++++++++++++
2 files changed, 63 insertions(+)
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index c38ef0dda605..c5bd804eca55 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -249,6 +249,15 @@ Display PLLs
.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.h
:internal:
+Display State Buffer
+--------------------
+
+.. kernel-doc:: drivers/gpu/drm/i915/intel_dsb.c
+ :doc: DSB
+
+.. kernel-doc:: drivers/gpu/drm/i915/intel_dsb.c
+ :internal:
+
Memory Management and Command Submission
========================================
diff --git a/drivers/gpu/drm/i915/intel_dsb.c b/drivers/gpu/drm/i915/intel_dsb.c
index dddaae27d7b5..b74126c99a16 100644
--- a/drivers/gpu/drm/i915/intel_dsb.c
+++ b/drivers/gpu/drm/i915/intel_dsb.c
@@ -8,6 +8,23 @@
#define DSB_BUF_SIZE (2 * PAGE_SIZE)
+/**
+ * DOC: DSB
+ *
+ * A DSB (Display State Buffer) is a queue of MMIO instructions in the memory
+ * which can be offloaded to DSB HW in Display Controller. DSB HW is a DMA
+ * engine that can be programmed to download the DSB from memory.
+ * It allows driver to batch submit display HW programming. This helps to
+ * reduce loading time and CPU activity, thereby making the context switch
+ * faster. DSB Support added from Gen12 Intel graphics based platform.
+ *
+ * DSB's can access only the pipe, plane, and transcoder Data Island Packet
+ * registers.
+ *
+ * DSB HW can support only register writes (both indexed and direct MMIO
+ * writes). There are no registers reads possible with DSB HW engine.
+ */
+
/* DSB opcodes. */
#define DSB_OPCODE_SHIFT 24
#define DSB_OPCODE_NOOP 0x0
@@ -72,6 +89,17 @@ static bool intel_dsb_disable_engine(struct intel_dsb *dsb)
return true;
}
+/**
+ * intel_dsb_get() - Allocate dsb context and return a dsb instance.
+ * @crtc: intel_crtc structure to get pipe info.
+ *
+ * This function will give handle of the DSB instance which
+ * user want to operate on.
+ *
+ * Return : address of Intel_dsb instance requested for.
+ * In failure case, the dsb instance will not have any command buffer.
+ */
+
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc)
{
@@ -164,6 +192,18 @@ static void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
buf[dsb->free_pos] = 0;
}
+/**
+ * intel_dsb_reg_write() -Write to the dsb context for normal
+ * register.
+ * @dsb: intel_dsb structure.
+ * @reg: register address.
+ * @val: value.
+ *
+ * This function is used for writing register-value pair in command
+ * buffer of DSB. During command buffer overflow, a warning
+ * is thrown and rest all erroneous condition register programming is done
+ * through mmio write.
+ */
void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
{
struct intel_crtc *crtc = dsb->crtc;
@@ -191,6 +231,13 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
i915_mmio_reg_offset(reg);
}
+/**
+ * intel_dsb_commit() - Trigger workload execution of DSB.
+ * @dsb: intel_dsb structure.
+ *
+ * This function is used to do actual write to hardware using DSB.
+ * On errors, fall back to MMIO. Also this function help to reset the context.
+ */
void intel_dsb_commit(struct intel_dsb *dsb)
{
struct intel_crtc *crtc = dsb->crtc;
@@ -234,6 +281,13 @@ void intel_dsb_commit(struct intel_dsb *dsb)
intel_dsb_disable_engine(dsb);
}
+/**
+ * intel_dsb_put() - To destroy DSB context.
+ * @dsb: intel_dsb structure.
+ *
+ * This function is used to destroy the dsb-context by doing unpin
+ * and release the vma object.
+ */
void intel_dsb_put(struct intel_dsb *dsb)
{
struct intel_crtc *crtc = dsb->crtc;
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 15/15] drm/i915/dsb: Enable gamma lut programming using DSB.
2019-07-01 6:26 [PATCH 00/15] DSB enablement Animesh Manna
` (13 preceding siblings ...)
2019-07-01 6:26 ` [PATCH 14/15] drm/i915/dsb: Documentation for DSB Animesh Manna
@ 2019-07-01 6:26 ` Animesh Manna
2019-07-01 7:09 ` ✗ Fi.CI.CHECKPATCH: warning for DSB enablement Patchwork
` (4 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Animesh Manna @ 2019-07-01 6:26 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Gamma lut programming can be programmed using DSB
where bulk register programming can be done using indexed
register write which takes number of data and the mmio offset
to be written.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 4 ++++
drivers/gpu/drm/i915/i915_reg.h | 25 +++++++++++++++-------
2 files changed, 21 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 23a84dd7989f..8534daed05a6 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -882,7 +882,9 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state)
{
const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ dev_priv->dsb = crtc_state->dsb;
if (crtc_state->base.degamma_lut)
glk_load_degamma_lut(crtc_state);
@@ -900,6 +902,8 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state)
bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
ivb_load_lut_ext_max(crtc);
}
+
+ intel_dsb_commit(dev_priv->dsb);
}
static u32 chv_cgm_degamma_ldw(const struct drm_color_lut *color)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8ef23e731cfe..b72c7e89739a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -242,7 +242,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define _PORT(port, a, b) _PICK_EVEN(port, a, b)
#define _PLL(pll, a, b) _PICK_EVEN(pll, a, b)
-#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
+#define _MMIO_PIPE(pipe, a, b, ...) _MMIO(_PIPE(pipe, a, b), ##__VA_ARGS__)
#define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b))
#define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
#define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
@@ -10185,11 +10185,18 @@ enum skl_power_gate {
#define _PAL_PREC_EXT2_GC_MAX_B 0x4AC30
#define _PAL_PREC_EXT2_GC_MAX_C 0x4B430
-#define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B)
-#define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
-#define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)
-#define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
-#define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4)
+#define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, \
+ _PAL_PREC_INDEX_B, \
+ DSB_WRITE)
+#define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, \
+ _PAL_PREC_DATA_B, \
+ DSB_INDEX_WRITE)
+#define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4, \
+ DSB_WRITE)
+#define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4, \
+ DSB_WRITE)
+#define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4, \
+ DSB_WRITE)
#define _PRE_CSC_GAMC_INDEX_A 0x4A484
#define _PRE_CSC_GAMC_INDEX_B 0x4AC84
@@ -10213,10 +10220,12 @@ enum skl_power_gate {
#define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \
_PAL_PREC_MULTI_SEG_INDEX_A, \
- _PAL_PREC_MULTI_SEG_INDEX_B)
+ _PAL_PREC_MULTI_SEG_INDEX_B, \
+ DSB_WRITE)
#define PREC_PAL_MULTI_SEG_DATA(pipe) _MMIO_PIPE(pipe, \
_PAL_PREC_MULTI_SEG_DATA_A, \
- _PAL_PREC_MULTI_SEG_DATA_B)
+ _PAL_PREC_MULTI_SEG_DATA_B, \
+ DSB_INDEX_WRITE)
/* pipe CSC & degamma/gamma LUTs on CHV */
#define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for DSB enablement.
2019-07-01 6:26 [PATCH 00/15] DSB enablement Animesh Manna
` (14 preceding siblings ...)
2019-07-01 6:26 ` [PATCH 15/15] drm/i915/dsb: Enable gamma lut programming using DSB Animesh Manna
@ 2019-07-01 7:09 ` Patchwork
2019-07-01 7:16 ` ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2019-07-01 7:09 UTC (permalink / raw)
To: Animesh Manna; +Cc: intel-gfx
== Series Details ==
Series: DSB enablement.
URL : https://patchwork.freedesktop.org/series/63013/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d1b2b4d2b22b drm/i915/dsb: feature flag added for display state buffer.
f910e626c852 drm/i915/dsb: DSB context creation.
-:55: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#55:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 120 lines checked
208d2a783e08 drm/i915/dsb: single register write function for DSB.
efc2e0d931ee drm/i915/dsb: Added enum for reg write capability.
080a458a7c02 drm/i915/dsb: Indexed register write function for DSB.
d3e8201962eb drm/i915/dsb: Update i915_write to call dsb-write.
-:42: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#42: FILE: drivers/gpu/drm/i915/i915_drv.h:2721:
+#define I915_WRITE(reg__, val__) \
+ (reg__.cap) ? intel_dsb_reg_write(dev_priv->dsb, (reg__), (val__)) : \
+ __I915_REG_OP(write, dev_priv, (reg__), (val__))
-:42: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'reg__' - possible side-effects?
#42: FILE: drivers/gpu/drm/i915/i915_drv.h:2721:
+#define I915_WRITE(reg__, val__) \
+ (reg__.cap) ? intel_dsb_reg_write(dev_priv->dsb, (reg__), (val__)) : \
+ __I915_REG_OP(write, dev_priv, (reg__), (val__))
-:42: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'val__' - possible side-effects?
#42: FILE: drivers/gpu/drm/i915/i915_drv.h:2721:
+#define I915_WRITE(reg__, val__) \
+ (reg__.cap) ? intel_dsb_reg_write(dev_priv->dsb, (reg__), (val__)) : \
+ __I915_REG_OP(write, dev_priv, (reg__), (val__))
total: 1 errors, 0 warnings, 2 checks, 26 lines checked
aa9a108cf7a9 drm/i915/dsb: Register definition of DSB registers.
5f19d6c09a08 drm/i915/dsb: Check DSB engine status.
905948da193a drm/i915/dsb: functions to enable/disable DSB engine.
531a3721623a drm/i915/dsb: function to trigger workload execution of DSB.
6c5b6c287545 drm/i915/dsb: function to destroy DSB context.
ce2dd71592dd drm/i915/dsb: Early prepare of dsb context.
f102c82be397 drm/i915/dsb: Cleanup of DSB context.
e96046cb8f4f drm/i915/dsb: Documentation for DSB.
5fcaa6842b63 drm/i915/dsb: Enable gamma lut programming using DSB.
-:66: WARNING:LONG_LINE: line over 100 characters
#66: FILE: drivers/gpu/drm/i915/i915_reg.h:10194:
+#define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4, \
-:68: WARNING:LONG_LINE: line over 100 characters
#68: FILE: drivers/gpu/drm/i915/i915_reg.h:10196:
+#define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4, \
-:70: WARNING:LONG_LINE: line over 100 characters
#70: FILE: drivers/gpu/drm/i915/i915_reg.h:10198:
+#define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4, \
total: 0 errors, 3 warnings, 0 checks, 62 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread* ✗ Fi.CI.SPARSE: warning for DSB enablement.
2019-07-01 6:26 [PATCH 00/15] DSB enablement Animesh Manna
` (15 preceding siblings ...)
2019-07-01 7:09 ` ✗ Fi.CI.CHECKPATCH: warning for DSB enablement Patchwork
@ 2019-07-01 7:16 ` Patchwork
2019-07-01 7:39 ` ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2019-07-01 7:16 UTC (permalink / raw)
To: Animesh Manna; +Cc: intel-gfx
== Series Details ==
Series: DSB enablement.
URL : https://patchwork.freedesktop.org/series/63013/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/dsb: feature flag added for display state buffer.
Okay!
Commit: drm/i915/dsb: DSB context creation.
+./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000000000000000 becomes 0)
Commit: drm/i915/dsb: single register write function for DSB.
Okay!
Commit: drm/i915/dsb: Added enum for reg write capability.
Okay!
Commit: drm/i915/dsb: Indexed register write function for DSB.
Okay!
Commit: drm/i915/dsb: Update i915_write to call dsb-write.
Okay!
Commit: drm/i915/dsb: Register definition of DSB registers.
Okay!
Commit: drm/i915/dsb: Check DSB engine status.
Okay!
Commit: drm/i915/dsb: functions to enable/disable DSB engine.
+ ^~~~~~~~~~~~~~~~~~~~~~~
+ ^~~~~~~~~~~~~~~~~~~~~~~~
+cc1: all warnings being treated as errors
+drivers/gpu/drm/i915/intel_dsb.c:35:13: error: ‘intel_dsb_enable_engine’ defined but not used [-Werror=unused-function]
+drivers/gpu/drm/i915/intel_dsb.c:55:13: error: ‘intel_dsb_disable_engine’ defined but not used [-Werror=unused-function]
+make[1]: *** [drivers/gpu/drm/i915] Error 2
+make[1]: *** Waiting for unfinished jobs....
+make[2]: *** [drivers/gpu/drm/i915/intel_dsb.o] Error 1
+make: *** [drivers/gpu/drm/] Error 2
+ static bool intel_dsb_disable_engine(struct intel_dsb *dsb)
+ static bool intel_dsb_enable_engine(struct intel_dsb *dsb)
Commit: drm/i915/dsb: function to trigger workload execution of DSB.
- ^~~~~~~~~~~~~~~~~~~~~~~
- ^~~~~~~~~~~~~~~~~~~~~~~~
-cc1: all warnings being treated as errors
+drivers/gpu/drm/i915/display/icl_dsi.c:135:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/icl_dsi.c:1425:25: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/icl_dsi.c:1425:25: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/icl_dsi.c:1426:26: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/icl_dsi.c:1426:26: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_audio.c:306:15: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_audio.c:306:15: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_audio.c:482:15: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_audio.c:601:15: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_audio.c:971:34: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_audio.c:971:34: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_bw.c:129:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_bw.c:129:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_bw.c:169:19: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_bw.c:169:19: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_bw.c:171:20: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_bw.c:171:20: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_bw.c:191:30: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_bw.c:191:30: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_bw.c:195:44: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_bw.c:195:44: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_bw.c:244:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_bw.c:244:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_bw.c:244:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_bw.c:244:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_bw.c:244:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_bw.c:244:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_bw.c:244:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_bw.c:244:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_bw.c:244:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_bw.c:244:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_bw.c:244:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_bw.c:244:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_bw.c:244:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_bw.c:244:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_cdclk.c:2251:37: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_cdclk.c:2254:37: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_cdclk.c:2263:29: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_cdclk.c:2271:29: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_cdclk.c:2280:29: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_cdclk.c:2312:29: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_cdclk.c:2312:29: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_cdclk.c:2348:37: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_cdclk.c:2348:37: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_cdclk.c:2541:17: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_cdclk.c:2541:17: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_cdclk.c:2575:17: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_cdclk.c:2575:17: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:121:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:121:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:121:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:121:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:121:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:121:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:121:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:227:29: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:227:29: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:227:29: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:227:29: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:227:29: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:227:29: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:227:29: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:237:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:237:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:237:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:237:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:237:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:237:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:237:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:240:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:240:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:240:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:240:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:240:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:240:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:240:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:243:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:243:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:243:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:243:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:243:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:243:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:243:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:245:38: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:245:38: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:245:38: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:245:38: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:245:38: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:245:38: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:245:38: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:248:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:248:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:248:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:248:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:248:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:248:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:248:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:251:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:251:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:251:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:251:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:251:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:251:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:251:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:341:37: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:341:37: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:341:37: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:341:37: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:341:37: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:341:37: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_color.c:341:37: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_ddi.c:671:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_ddi.c:673:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_display.c:1202:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/display/intel_display.c:1205:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/display/intel_display.c:1208:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/display/intel_display.c:1211:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/display/intel_display.c:14391:21: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_display.c:14391:21: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_display.c:2420:13: error: undefined identifier '__builtin_add_overflow_p'
+drivers/gpu/drm/i915/display/intel_display.c:2792:28: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_display.c:2792:28: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_display.c:7372:26: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_display.c:883:21: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_display.c:883:21: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c:158:21: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c:158:21: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c:158:21: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c:158:21: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c:158:21: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c:158:21: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c:158:21: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:1442:39: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:1442:39: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:1442:39: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:1442:39: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:1442:39: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:1442:39: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:1442:39: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:1442:39: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:1806:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:1806:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:1939:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:1959:25: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:1959:25: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:1981:58: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:1981:58: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:255:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:255:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:255:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:255:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:255:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:255:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:255:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:255:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:255:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:255:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:255:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:255:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:255:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:255:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:300:30: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:300:30: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:394:28: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:394:28: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:4371:26: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:4371:26: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:4414:27: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:4414:27: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:5941:30: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:6645:31: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:6674:9: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:6674:9: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:6674:9: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:6674:9: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:6675:9: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:6675:9: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:6675:9: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:6675:9: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:6676:9: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:6676:9: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:6676:9: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:6676:9: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:6677:9: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:6677:9: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:6677:9: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:6677:9: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:6678:9: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:6678:9: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:6678:9: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:6678:9: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_fbc.c:92:25: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_fbc.c:94:25: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_gmbus.c:469:31: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_gmbus.c:471:31: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_gmbus.c:471:31: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_gmbus.c:533:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_gmbus.c:533:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_hdmi.c:2091:34: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_hdmi.c:2091:34: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_hdmi.c:2108:42: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_hdmi.c:2108:42: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_hdmi.c:2112:42: warning: ex
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread* ✓ Fi.CI.BAT: success for DSB enablement.
2019-07-01 6:26 [PATCH 00/15] DSB enablement Animesh Manna
` (16 preceding siblings ...)
2019-07-01 7:16 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2019-07-01 7:39 ` Patchwork
2019-07-01 9:05 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-08-09 9:42 ` [PATCH 00/15] " Jani Nikula
19 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2019-07-01 7:39 UTC (permalink / raw)
To: Animesh Manna; +Cc: intel-gfx
== Series Details ==
Series: DSB enablement.
URL : https://patchwork.freedesktop.org/series/63013/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6388 -> Patchwork_13476
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/
Known issues
------------
Here are the changes found in Patchwork_13476 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_mmap@basic-small-bo:
- fi-glk-dsi: [PASS][1] -> [INCOMPLETE][2] ([fdo#103359] / [fdo#110715] / [k.org#198133])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6388/fi-glk-dsi/igt@gem_mmap@basic-small-bo.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/fi-glk-dsi/igt@gem_mmap@basic-small-bo.html
* igt@i915_module_load@reload:
- fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6388/fi-blb-e6850/igt@i915_module_load@reload.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/fi-blb-e6850/igt@i915_module_load@reload.html
* igt@prime_vgem@basic-fence-flip:
- fi-ilk-650: [PASS][5] -> [DMESG-WARN][6] ([fdo#106387]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6388/fi-ilk-650/igt@prime_vgem@basic-fence-flip.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/fi-ilk-650/igt@prime_vgem@basic-fence-flip.html
#### Possible fixes ####
* igt@i915_selftest@live_blt:
- fi-skl-iommu: [INCOMPLETE][7] ([fdo#108602]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6388/fi-skl-iommu/igt@i915_selftest@live_blt.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/fi-skl-iommu/igt@i915_selftest@live_blt.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [FAIL][9] ([fdo#109635 ]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6388/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7567u: [FAIL][11] ([fdo#109485]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6388/fi-kbl-7567u/igt@kms_chamelium@hdmi-hpd-fast.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/fi-kbl-7567u/igt@kms_chamelium@hdmi-hpd-fast.html
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#110715]: https://bugs.freedesktop.org/show_bug.cgi?id=110715
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (50 -> 42)
------------------------------
Additional (3): fi-hsw-peppy fi-icl-u3 fi-cml-u
Missing (11): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-pnv-d510 fi-icl-y fi-icl-guc fi-icl-dsi fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_6388 -> Patchwork_13476
CI_DRM_6388: 2307d0a7a88d1e98df2214f16d93efd68fb5fcd9 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5075: 03779dd3de8a57544f124d9952a6d2b3e34e34ca @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13476: 5fcaa6842b634e04a4a1fced696ec893510c99e3 @ git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/build_32bit.log
CALL scripts/checksyscalls.sh
CALL scripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
5fcaa6842b63 drm/i915/dsb: Enable gamma lut programming using DSB.
e96046cb8f4f drm/i915/dsb: Documentation for DSB.
f102c82be397 drm/i915/dsb: Cleanup of DSB context.
ce2dd71592dd drm/i915/dsb: Early prepare of dsb context.
6c5b6c287545 drm/i915/dsb: function to destroy DSB context.
531a3721623a drm/i915/dsb: function to trigger workload execution of DSB.
905948da193a drm/i915/dsb: functions to enable/disable DSB engine.
5f19d6c09a08 drm/i915/dsb: Check DSB engine status.
aa9a108cf7a9 drm/i915/dsb: Register definition of DSB registers.
d3e8201962eb drm/i915/dsb: Update i915_write to call dsb-write.
080a458a7c02 drm/i915/dsb: Indexed register write function for DSB.
efc2e0d931ee drm/i915/dsb: Added enum for reg write capability.
208d2a783e08 drm/i915/dsb: single register write function for DSB.
f910e626c852 drm/i915/dsb: DSB context creation.
d1b2b4d2b22b drm/i915/dsb: feature flag added for display state buffer.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread* ✗ Fi.CI.IGT: failure for DSB enablement.
2019-07-01 6:26 [PATCH 00/15] DSB enablement Animesh Manna
` (17 preceding siblings ...)
2019-07-01 7:39 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-07-01 9:05 ` Patchwork
2019-08-09 9:42 ` [PATCH 00/15] " Jani Nikula
19 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2019-07-01 9:05 UTC (permalink / raw)
To: Animesh Manna; +Cc: intel-gfx
== Series Details ==
Series: DSB enablement.
URL : https://patchwork.freedesktop.org/series/63013/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6388_full -> Patchwork_13476_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_13476_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_13476_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_13476_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_busy@extended-modeset-hang-oldfb-render-a:
- shard-snb: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6388/shard-snb7/igt@kms_busy@extended-modeset-hang-oldfb-render-a.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/shard-snb4/igt@kms_busy@extended-modeset-hang-oldfb-render-a.html
* igt@kms_color@pipe-b-ctm-negative:
- shard-skl: [PASS][3] -> [INCOMPLETE][4] +20 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6388/shard-skl10/igt@kms_color@pipe-b-ctm-negative.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/shard-skl4/igt@kms_color@pipe-b-ctm-negative.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-iclb: [PASS][5] -> [DMESG-FAIL][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6388/shard-iclb3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@runner@aborted:
- shard-iclb: NOTRUN -> ([FAIL][7], [FAIL][8], [FAIL][9]) ([fdo#108866])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/shard-iclb5/igt@runner@aborted.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/shard-iclb3/igt@runner@aborted.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/shard-iclb7/igt@runner@aborted.html
- shard-snb: NOTRUN -> [FAIL][10]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/shard-snb4/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_13476_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
- shard-iclb: [PASS][11] -> [DMESG-WARN][12] ([fdo#110222])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6388/shard-iclb1/igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/shard-iclb3/igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a.html
* igt@kms_color@pipe-a-degamma:
- shard-hsw: [PASS][13] -> [INCOMPLETE][14] ([fdo#103540]) +23 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6388/shard-hsw4/igt@kms_color@pipe-a-degamma.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/shard-hsw1/igt@kms_color@pipe-a-degamma.html
* igt@kms_color@pipe-b-degamma:
- shard-kbl: [PASS][15] -> [INCOMPLETE][16] ([fdo#103665]) +22 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6388/shard-kbl7/igt@kms_color@pipe-b-degamma.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/shard-kbl4/igt@kms_color@pipe-b-degamma.html
* igt@kms_color@pipe-c-ctm-0-25:
- shard-apl: [PASS][17] -> [INCOMPLETE][18] ([fdo#103927]) +20 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6388/shard-apl3/igt@kms_color@pipe-c-ctm-0-25.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/shard-apl5/igt@kms_color@pipe-c-ctm-0-25.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-apl: [PASS][19] -> [DMESG-WARN][20] ([fdo#108566]) +3 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6388/shard-apl4/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/shard-apl6/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_cursor_legacy@all-pipes-forked-bo:
- shard-glk: [PASS][21] -> [INCOMPLETE][22] ([fdo#103359] / [k.org#198133]) +20 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6388/shard-glk1/igt@kms_cursor_legacy@all-pipes-forked-bo.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/shard-glk4/igt@kms_cursor_legacy@all-pipes-forked-bo.html
* igt@kms_cursor_legacy@pipe-b-forked-move:
- shard-iclb: [PASS][23] -> [DMESG-WARN][24] ([fdo#107122])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6388/shard-iclb2/igt@kms_cursor_legacy@pipe-b-forked-move.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/shard-iclb5/igt@kms_cursor_legacy@pipe-b-forked-move.html
* igt@kms_cursor_legacy@pipe-b-torture-move:
- shard-iclb: [PASS][25] -> [INCOMPLETE][26] ([fdo#107713]) +14 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6388/shard-iclb3/igt@kms_cursor_legacy@pipe-b-torture-move.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/shard-iclb1/igt@kms_cursor_legacy@pipe-b-torture-move.html
- shard-snb: [PASS][27] -> [INCOMPLETE][28] ([fdo#105411]) +5 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6388/shard-snb1/igt@kms_cursor_legacy@pipe-b-torture-move.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/shard-snb2/igt@kms_cursor_legacy@pipe-b-torture-move.html
* igt@kms_cursor_legacy@pipe-c-torture-move:
- shard-skl: [PASS][29] -> [INCOMPLETE][30] ([fdo#104108]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6388/shard-skl5/igt@kms_cursor_legacy@pipe-c-torture-move.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/shard-skl1/igt@kms_cursor_legacy@pipe-c-torture-move.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [PASS][31] -> [FAIL][32] ([fdo#105363]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6388/shard-skl2/igt@kms_flip@flip-vs-expired-vblank.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/shard-skl9/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-glk: [PASS][33] -> [FAIL][34] ([fdo#105363])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6388/shard-glk2/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/shard-glk3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend:
- shard-kbl: [PASS][35] -> [DMESG-WARN][36] ([fdo#108566])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6388/shard-kbl2/igt@kms_flip@flip-vs-suspend.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/shard-kbl6/igt@kms_flip@flip-vs-suspend.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-pwrite:
- shard-hsw: [PASS][37] -> [SKIP][38] ([fdo#109271]) +7 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6388/shard-hsw4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-pwrite.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/shard-hsw1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbc-indfb-scaledprimary:
- shard-iclb: [PASS][39] -> [FAIL][40] ([fdo#103167]) +4 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6388/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-indfb-scaledprimary.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-indfb-scaledprimary.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [PASS][41] -> [FAIL][42] ([fdo#108145])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6388/shard-skl3/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][43] -> [FAIL][44] ([fdo#108145] / [fdo#110403]) +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6388/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [PASS][45] -> [SKIP][46] ([fdo#109441]) +2 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6388/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/shard-iclb6/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@perf@blocking:
- shard-skl: [PASS][47] -> [FAIL][48] ([fdo#110728])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6388/shard-skl4/igt@perf@blocking.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/shard-skl5/igt@perf@blocking.html
* igt@perf_pmu@rc6:
- shard-kbl: [PASS][49] -> [SKIP][50] ([fdo#109271])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6388/shard-kbl6/igt@perf_pmu@rc6.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/shard-kbl2/igt@perf_pmu@rc6.html
#### Possible fixes ####
* igt@i915_pm_rpm@i2c:
- shard-hsw: [FAIL][51] ([fdo#104097]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6388/shard-hsw2/igt@i915_pm_rpm@i2c.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/shard-hsw7/igt@i915_pm_rpm@i2c.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [DMESG-WARN][53] ([fdo#108566]) -> [PASS][54] +3 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6388/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_flip@flip-vs-suspend:
- shard-glk: [INCOMPLETE][55] ([fdo#103359] / [k.org#198133]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6388/shard-glk2/igt@kms_flip@flip-vs-suspend.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/shard-glk6/igt@kms_flip@flip-vs-suspend.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-wc:
- shard-glk: [FAIL][57] ([fdo#103167]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6388/shard-glk7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-wc.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/shard-glk1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-move:
- shard-hsw: [SKIP][59] ([fdo#109271]) -> [PASS][60] +11 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6388/shard-hsw1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-move.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/shard-hsw4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite:
- shard-iclb: [FAIL][61] ([fdo#103167]) -> [PASS][62] +4 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6388/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-skl: [INCOMPLETE][63] ([fdo#104108]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6388/shard-skl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/shard-skl9/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
#### Warnings ####
* igt@i915_pm_lpsp@non-edp:
- shard-apl: [SKIP][65] ([fdo#109271]) -> [INCOMPLETE][66] ([fdo#103927])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6388/shard-apl2/igt@i915_pm_lpsp@non-edp.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/shard-apl1/igt@i915_pm_lpsp@non-edp.html
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104097]: https://bugs.freedesktop.org/show_bug.cgi?id=104097
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#107122]: https://bugs.freedesktop.org/show_bug.cgi?id=107122
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108866]: https://bugs.freedesktop.org/show_bug.cgi?id=108866
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110222]: https://bugs.freedesktop.org/show_bug.cgi?id=110222
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
[fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_6388 -> Patchwork_13476
CI_DRM_6388: 2307d0a7a88d1e98df2214f16d93efd68fb5fcd9 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5075: 03779dd3de8a57544f124d9952a6d2b3e34e34ca @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13476: 5fcaa6842b634e04a4a1fced696ec893510c99e3 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13476/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH 00/15] DSB enablement.
2019-07-01 6:26 [PATCH 00/15] DSB enablement Animesh Manna
` (18 preceding siblings ...)
2019-07-01 9:05 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2019-08-09 9:42 ` Jani Nikula
2019-08-12 8:52 ` Animesh Manna
19 siblings, 1 reply; 22+ messages in thread
From: Jani Nikula @ 2019-08-09 9:42 UTC (permalink / raw)
To: Animesh Manna, intel-gfx; +Cc: Michel Thierry, Lucas De Marchi
On Mon, 01 Jul 2019, Animesh Manna <animesh.manna@intel.com> wrote:
> Display State Buffer (DSB) is hardware capability which allows
> driver to batch submit HW programming.
>
> As part of initial enablement common api created which currently used
> to program gamma lut proramming.
>
> Going forwad DSB support can be added for HDR and flip related operation.
>
> Few changes of this patch series is not tested, sending version 1
> for design review, will be testing in parallel.
Our CI reported on the same day that this series oopses on a lot of
platforms. Have you investigated and fixed those issues? Please post the
fixed series.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH 00/15] DSB enablement.
2019-08-09 9:42 ` [PATCH 00/15] " Jani Nikula
@ 2019-08-12 8:52 ` Animesh Manna
0 siblings, 0 replies; 22+ messages in thread
From: Animesh Manna @ 2019-08-12 8:52 UTC (permalink / raw)
To: Jani Nikula, intel-gfx; +Cc: Michel Thierry, Lucas De Marchi
On 8/9/2019 3:12 PM, Jani Nikula wrote:
> On Mon, 01 Jul 2019, Animesh Manna <animesh.manna@intel.com> wrote:
>> Display State Buffer (DSB) is hardware capability which allows
>> driver to batch submit HW programming.
>>
>> As part of initial enablement common api created which currently used
>> to program gamma lut proramming.
>>
>> Going forwad DSB support can be added for HDR and flip related operation.
>>
>> Few changes of this patch series is not tested, sending version 1
>> for design review, will be testing in parallel.
> Our CI reported on the same day that this series oopses on a lot of
> platforms. Have you investigated and fixed those issues? Please post the
> fixed series.
Found the issue and fixed it (changes added in 15th patch), have sent to
trybot, will post the patches soon.
Regards,
Animesh
>
> BR,
> Jani.
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread