Bay Trail PTE fixes

Bay Trail PTE fixes

[Kenneth Graunke]

This refactors our PTE encoding functions, splitting them out into
per-generation functions.  Patch 2 fixes the page table entries for
the latest revision of Bay Trail, which is necessary to avoid GPU hangs.

I've tested these patches on Bay Trail and Haswell.  Not SNB/IVB.

[PATCH 1/3] drm/i915: Add PTE encoding function to the gtt/ppgtt vtables.

[Kenneth Graunke]

Sandybridge/Ivybridge, Bay Trail, and Haswell all have slightly
different page table entry formats.  Rather than polluting one function
with generation checks, simply use a function pointer and set up the
correct PTE encoding function at startup.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
---
 drivers/gpu/drm/i915/i915_drv.h     |  6 ++++++
 drivers/gpu/drm/i915/i915_gem_gtt.c | 22 +++++++++++++---------
 2 files changed, 19 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bd2d7f1..8b58997 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -430,6 +430,9 @@ struct i915_gtt {
 				   struct sg_table *st,
 				   unsigned int pg_start,
 				   enum i915_cache_level cache_level);
+	uint32_t (*pte_encode)(struct drm_device *dev,
+			       dma_addr_t addr,
+			       enum i915_cache_level level);
 };
 #define gtt_total_entries(gtt) ((gtt).total >> PAGE_SHIFT)
 
@@ -451,6 +454,9 @@ struct i915_hw_ppgtt {
 			       struct sg_table *st,
 			       unsigned int pg_start,
 			       enum i915_cache_level cache_level);
+	uint32_t (*pte_encode)(struct drm_device *dev,
+			       dma_addr_t addr,
+			       enum i915_cache_level level);
 	int (*enable)(struct drm_device *dev);
 	void (*cleanup)(struct i915_hw_ppgtt *ppgtt);
 };
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 50df194..9db65c1 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -154,9 +154,9 @@ static void gen6_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt,
 	unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 	unsigned last_pte, i;
 
-	scratch_pte = gen6_pte_encode(ppgtt->dev,
-				      ppgtt->scratch_page_dma_addr,
-				      I915_CACHE_LLC);
+	scratch_pte = ppgtt->pte_encode(ppgtt->dev,
+					ppgtt->scratch_page_dma_addr,
+					I915_CACHE_LLC);
 
 	while (num_entries) {
 		last_pte = first_pte + num_entries;
@@ -191,8 +191,8 @@ static void gen6_ppgtt_insert_entries(struct i915_hw_ppgtt *ppgtt,
 		dma_addr_t page_addr;
 
 		page_addr = sg_page_iter_dma_address(&sg_iter);
-		pt_vaddr[act_pte] = gen6_pte_encode(ppgtt->dev, page_addr,
-						    cache_level);
+		pt_vaddr[act_pte] = ppgtt->pte_encode(ppgtt->dev, page_addr,
+						      cache_level);
 		if (++act_pte == I915_PPGTT_PT_ENTRIES) {
 			kunmap_atomic(pt_vaddr);
 			act_pt++;
@@ -236,6 +236,7 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
 	first_pd_entry_in_global_pt =
 		gtt_total_entries(dev_priv->gtt) - I915_PPGTT_PD_ENTRIES;
 
+	ppgtt->pte_encode = gen6_pte_encode;
 	ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES;
 	ppgtt->enable = gen6_ppgtt_enable;
 	ppgtt->clear_range = gen6_ppgtt_clear_range;
@@ -438,7 +439,8 @@ static void gen6_ggtt_insert_entries(struct drm_device *dev,
 
 	for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
 		addr = sg_page_iter_dma_address(&sg_iter);
-		iowrite32(gen6_pte_encode(dev, addr, level), &gtt_entries[i]);
+		iowrite32(dev_priv->gtt.pte_encode(dev, addr, level),
+			  &gtt_entries[i]);
 		i++;
 	}
 
@@ -450,7 +452,7 @@ static void gen6_ggtt_insert_entries(struct drm_device *dev,
 	 */
 	if (i != 0)
 		WARN_ON(readl(&gtt_entries[i-1])
-			!= gen6_pte_encode(dev, addr, level));
+			!= dev_priv->gtt.pte_encode(dev, addr, level));
 
 	/* This next bit makes the above posting read even more important. We
 	 * want to flush the TLBs only after we're certain all the PTE updates
@@ -475,8 +477,9 @@ static void gen6_ggtt_clear_range(struct drm_device *dev,
 		 first_entry, num_entries, max_entries))
 		num_entries = max_entries;
 
-	scratch_pte = gen6_pte_encode(dev, dev_priv->gtt.scratch_page_dma,
-				      I915_CACHE_LLC);
+	scratch_pte = dev_priv->gtt.pte_encode(dev,
+					       dev_priv->gtt.scratch_page_dma,
+					       I915_CACHE_LLC);
 	for (i = 0; i < num_entries; i++)
 		iowrite32(scratch_pte, &gtt_base[i]);
 	readl(gtt_base);
@@ -823,6 +826,7 @@ int i915_gem_gtt_init(struct drm_device *dev)
 	} else {
 		dev_priv->gtt.gtt_probe = gen6_gmch_probe;
 		dev_priv->gtt.gtt_remove = gen6_gmch_remove;
+		dev_priv->gtt.pte_encode = gen6_pte_encode;
 	}
 
 	ret = dev_priv->gtt.gtt_probe(dev, &dev_priv->gtt.total,
-- 
1.8.2.1

[PATCH 2/3] drm/i915: Fix page table entries for Bay Trail.

[Kenneth Graunke]

On Bay Trail, bit 1 means "writeable by the GPU."  Failing to set that
means basically anything using the GPU will cause hangs.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 33 +++++++++++++++++++++++++++++++--
 1 file changed, 31 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 9db65c1..db5c654 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -75,6 +75,27 @@ static inline gen6_gtt_pte_t gen6_pte_encode(struct drm_device *dev,
 	return pte;
 }
 
+#define BYT_PTE_WRITEABLE		(1 << 1)
+#define BYT_PTE_SNOOPED_BY_CPU_CACHES	(1 << 2)
+
+static inline gen6_gtt_pte_t byt_pte_encode(struct drm_device *dev,
+					    dma_addr_t addr,
+					    enum i915_cache_level level)
+{
+	gen6_gtt_pte_t pte = GEN6_PTE_VALID;
+	pte |= GEN6_PTE_ADDR_ENCODE(addr);
+
+	/* Mark the page as writeable.  Other platforms don't have a
+	 * setting for read-only/writable, so this matches that behavior.
+	 */
+	pte |= BYT_PTE_WRITEABLE;
+
+	if (level != I915_CACHE_NONE)
+		pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
+
+	return pte;
+}
+
 static int gen6_ppgtt_enable(struct drm_device *dev)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
@@ -236,7 +257,11 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
 	first_pd_entry_in_global_pt =
 		gtt_total_entries(dev_priv->gtt) - I915_PPGTT_PD_ENTRIES;
 
-	ppgtt->pte_encode = gen6_pte_encode;
+	if (IS_VALLEYVIEW(dev)) {
+		ppgtt->pte_encode = byt_pte_encode;
+	} else {
+		ppgtt->pte_encode = gen6_pte_encode;
+	}
 	ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES;
 	ppgtt->enable = gen6_ppgtt_enable;
 	ppgtt->clear_range = gen6_ppgtt_clear_range;
@@ -826,7 +851,11 @@ int i915_gem_gtt_init(struct drm_device *dev)
 	} else {
 		dev_priv->gtt.gtt_probe = gen6_gmch_probe;
 		dev_priv->gtt.gtt_remove = gen6_gmch_remove;
-		dev_priv->gtt.pte_encode = gen6_pte_encode;
+		if (IS_VALLEYVIEW(dev)) {
+			dev_priv->gtt.pte_encode = byt_pte_encode;
+		} else {
+			dev_priv->gtt.pte_encode = gen6_pte_encode;
+		}
 	}
 
 	ret = dev_priv->gtt.gtt_probe(dev, &dev_priv->gtt.total,
-- 
1.8.2.1

[PATCH 3/3] drm/i915: Split out Haswell code from gen6_pte_encode.

[Kenneth Graunke]

Now that we have function pointers, it's cleaner to just create a new
per-platform PTE encoding function.

This should be identical in behavior to the previous code.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 32 +++++++++++++++++++++-----------
 1 file changed, 21 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index db5c654..034a502 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -53,20 +53,13 @@ static inline gen6_gtt_pte_t gen6_pte_encode(struct drm_device *dev,
 
 	switch (level) {
 	case I915_CACHE_LLC_MLC:
-		/* Haswell doesn't set L3 this way */
-		if (IS_HASWELL(dev))
-			pte |= GEN6_PTE_CACHE_LLC;
-		else
-			pte |= GEN6_PTE_CACHE_LLC_MLC;
+		pte |= GEN6_PTE_CACHE_LLC_MLC;
 		break;
 	case I915_CACHE_LLC:
 		pte |= GEN6_PTE_CACHE_LLC;
 		break;
 	case I915_CACHE_NONE:
-		if (IS_HASWELL(dev))
-			pte |= HSW_PTE_UNCACHED;
-		else
-			pte |= GEN6_PTE_UNCACHED;
+		pte |= GEN6_PTE_UNCACHED;
 		break;
 	default:
 		BUG();
@@ -96,6 +89,19 @@ static inline gen6_gtt_pte_t byt_pte_encode(struct drm_device *dev,
 	return pte;
 }
 
+static inline gen6_gtt_pte_t hsw_pte_encode(struct drm_device *dev,
+					    dma_addr_t addr,
+					    enum i915_cache_level level)
+{
+	gen6_gtt_pte_t pte = GEN6_PTE_VALID;
+	pte |= GEN6_PTE_ADDR_ENCODE(addr);
+
+	if (level != I915_CACHE_NONE)
+		pte |= GEN6_PTE_CACHE_LLC;
+
+	return pte;
+}
+
 static int gen6_ppgtt_enable(struct drm_device *dev)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
@@ -257,7 +263,9 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
 	first_pd_entry_in_global_pt =
 		gtt_total_entries(dev_priv->gtt) - I915_PPGTT_PD_ENTRIES;
 
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_HASWELL(dev)) {
+		ppgtt->pte_encode = hsw_pte_encode;
+	} else if (IS_VALLEYVIEW(dev)) {
 		ppgtt->pte_encode = byt_pte_encode;
 	} else {
 		ppgtt->pte_encode = gen6_pte_encode;
@@ -851,7 +859,9 @@ int i915_gem_gtt_init(struct drm_device *dev)
 	} else {
 		dev_priv->gtt.gtt_probe = gen6_gmch_probe;
 		dev_priv->gtt.gtt_remove = gen6_gmch_remove;
-		if (IS_VALLEYVIEW(dev)) {
+		if (IS_HASWELL(dev)) {
+			dev_priv->gtt.pte_encode = hsw_pte_encode;
+		} else if (IS_VALLEYVIEW(dev)) {
 			dev_priv->gtt.pte_encode = byt_pte_encode;
 		} else {
 			dev_priv->gtt.pte_encode = gen6_pte_encode;
-- 
1.8.2.1

Re: Bay Trail PTE fixes

[Ben Widawsky]

On Thu, Apr 18, 2013 at 01:28:33PM -0700, Kenneth Graunke wrote:
> This refactors our PTE encoding functions, splitting them out into
> per-generation functions.  Patch 2 fixes the page table entries for
> the latest revision of Bay Trail, which is necessary to avoid GPU hangs.
> 
> I've tested these patches on Bay Trail and Haswell.  Not SNB/IVB.
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

These were internally
Tested-by: Daniel Leung <daniel.leung@linux.intel.com>

-- 
Ben Widawsky, Intel Open Source Technology Center

Re: [PATCH 1/3] drm/i915: Add PTE encoding function to the gtt/ppgtt vtables.

[Jani Nikula]

On Thu, 18 Apr 2013, Kenneth Graunke <kenneth@whitecape.org> wrote:
> Sandybridge/Ivybridge, Bay Trail, and Haswell all have slightly
> different page table entry formats.  Rather than polluting one function
> with generation checks, simply use a function pointer and set up the
> correct PTE encoding function at startup.
>
> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
> ---
>  drivers/gpu/drm/i915/i915_drv.h     |  6 ++++++
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 22 +++++++++++++---------
>  2 files changed, 19 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index bd2d7f1..8b58997 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -430,6 +430,9 @@ struct i915_gtt {
>  				   struct sg_table *st,
>  				   unsigned int pg_start,
>  				   enum i915_cache_level cache_level);
> +	uint32_t (*pte_encode)(struct drm_device *dev,
> +			       dma_addr_t addr,
> +			       enum i915_cache_level level);

To keep the gen6_gtt_pte_t typedef internal to i915_gem_gtt.c, or to
have the same return type in the function pointers and the functions. I
think I'd find the latter more aesthetically pleasing, but I'm not
insisting. Either way,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


>  };
>  #define gtt_total_entries(gtt) ((gtt).total >> PAGE_SHIFT)
>  
> @@ -451,6 +454,9 @@ struct i915_hw_ppgtt {
>  			       struct sg_table *st,
>  			       unsigned int pg_start,
>  			       enum i915_cache_level cache_level);
> +	uint32_t (*pte_encode)(struct drm_device *dev,
> +			       dma_addr_t addr,
> +			       enum i915_cache_level level);
>  	int (*enable)(struct drm_device *dev);
>  	void (*cleanup)(struct i915_hw_ppgtt *ppgtt);
>  };
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 50df194..9db65c1 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -154,9 +154,9 @@ static void gen6_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt,
>  	unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
>  	unsigned last_pte, i;
>  
> -	scratch_pte = gen6_pte_encode(ppgtt->dev,
> -				      ppgtt->scratch_page_dma_addr,
> -				      I915_CACHE_LLC);
> +	scratch_pte = ppgtt->pte_encode(ppgtt->dev,
> +					ppgtt->scratch_page_dma_addr,
> +					I915_CACHE_LLC);
>  
>  	while (num_entries) {
>  		last_pte = first_pte + num_entries;
> @@ -191,8 +191,8 @@ static void gen6_ppgtt_insert_entries(struct i915_hw_ppgtt *ppgtt,
>  		dma_addr_t page_addr;
>  
>  		page_addr = sg_page_iter_dma_address(&sg_iter);
> -		pt_vaddr[act_pte] = gen6_pte_encode(ppgtt->dev, page_addr,
> -						    cache_level);
> +		pt_vaddr[act_pte] = ppgtt->pte_encode(ppgtt->dev, page_addr,
> +						      cache_level);
>  		if (++act_pte == I915_PPGTT_PT_ENTRIES) {
>  			kunmap_atomic(pt_vaddr);
>  			act_pt++;
> @@ -236,6 +236,7 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
>  	first_pd_entry_in_global_pt =
>  		gtt_total_entries(dev_priv->gtt) - I915_PPGTT_PD_ENTRIES;
>  
> +	ppgtt->pte_encode = gen6_pte_encode;
>  	ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES;
>  	ppgtt->enable = gen6_ppgtt_enable;
>  	ppgtt->clear_range = gen6_ppgtt_clear_range;
> @@ -438,7 +439,8 @@ static void gen6_ggtt_insert_entries(struct drm_device *dev,
>  
>  	for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
>  		addr = sg_page_iter_dma_address(&sg_iter);
> -		iowrite32(gen6_pte_encode(dev, addr, level), &gtt_entries[i]);
> +		iowrite32(dev_priv->gtt.pte_encode(dev, addr, level),
> +			  &gtt_entries[i]);
>  		i++;
>  	}
>  
> @@ -450,7 +452,7 @@ static void gen6_ggtt_insert_entries(struct drm_device *dev,
>  	 */
>  	if (i != 0)
>  		WARN_ON(readl(&gtt_entries[i-1])
> -			!= gen6_pte_encode(dev, addr, level));
> +			!= dev_priv->gtt.pte_encode(dev, addr, level));
>  
>  	/* This next bit makes the above posting read even more important. We
>  	 * want to flush the TLBs only after we're certain all the PTE updates
> @@ -475,8 +477,9 @@ static void gen6_ggtt_clear_range(struct drm_device *dev,
>  		 first_entry, num_entries, max_entries))
>  		num_entries = max_entries;
>  
> -	scratch_pte = gen6_pte_encode(dev, dev_priv->gtt.scratch_page_dma,
> -				      I915_CACHE_LLC);
> +	scratch_pte = dev_priv->gtt.pte_encode(dev,
> +					       dev_priv->gtt.scratch_page_dma,
> +					       I915_CACHE_LLC);
>  	for (i = 0; i < num_entries; i++)
>  		iowrite32(scratch_pte, &gtt_base[i]);
>  	readl(gtt_base);
> @@ -823,6 +826,7 @@ int i915_gem_gtt_init(struct drm_device *dev)
>  	} else {
>  		dev_priv->gtt.gtt_probe = gen6_gmch_probe;
>  		dev_priv->gtt.gtt_remove = gen6_gmch_remove;
> +		dev_priv->gtt.pte_encode = gen6_pte_encode;
>  	}
>  
>  	ret = dev_priv->gtt.gtt_probe(dev, &dev_priv->gtt.total,
> -- 
> 1.8.2.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 2/3] drm/i915: Fix page table entries for Bay Trail.

[Jani Nikula]

On Thu, 18 Apr 2013, Kenneth Graunke <kenneth@whitecape.org> wrote:
> On Bay Trail, bit 1 means "writeable by the GPU."  Failing to set that
> means basically anything using the GPU will cause hangs.
>
> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 33 +++++++++++++++++++++++++++++++--
>  1 file changed, 31 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 9db65c1..db5c654 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -75,6 +75,27 @@ static inline gen6_gtt_pte_t gen6_pte_encode(struct drm_device *dev,
>  	return pte;
>  }
>  
> +#define BYT_PTE_WRITEABLE		(1 << 1)
> +#define BYT_PTE_SNOOPED_BY_CPU_CACHES	(1 << 2)
> +
> +static inline gen6_gtt_pte_t byt_pte_encode(struct drm_device *dev,

inline doesn't really make sense for functions used through
pointers... I wonder if the compiler should warn about taking address of
inline functions, or whether it just happily non-inlines. Too lazy to
check. ;)

Oh, this applies for patch 1 too; please drop inline from
gen6_pte_encode() there.

> +					    dma_addr_t addr,
> +					    enum i915_cache_level level)
> +{
> +	gen6_gtt_pte_t pte = GEN6_PTE_VALID;
> +	pte |= GEN6_PTE_ADDR_ENCODE(addr);
> +
> +	/* Mark the page as writeable.  Other platforms don't have a
> +	 * setting for read-only/writable, so this matches that behavior.
> +	 */
> +	pte |= BYT_PTE_WRITEABLE;
> +
> +	if (level != I915_CACHE_NONE)
> +		pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
> +
> +	return pte;
> +}
> +
>  static int gen6_ppgtt_enable(struct drm_device *dev)
>  {
>  	drm_i915_private_t *dev_priv = dev->dev_private;
> @@ -236,7 +257,11 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
>  	first_pd_entry_in_global_pt =
>  		gtt_total_entries(dev_priv->gtt) - I915_PPGTT_PD_ENTRIES;
>  
> -	ppgtt->pte_encode = gen6_pte_encode;
> +	if (IS_VALLEYVIEW(dev)) {
> +		ppgtt->pte_encode = byt_pte_encode;
> +	} else {
> +		ppgtt->pte_encode = gen6_pte_encode;
> +	}

HAS_ALIASING_PPGTT(dev) returns false for VLV. Do we need this in
preparation for future, or can we just drop this?

>  	ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES;
>  	ppgtt->enable = gen6_ppgtt_enable;
>  	ppgtt->clear_range = gen6_ppgtt_clear_range;
> @@ -826,7 +851,11 @@ int i915_gem_gtt_init(struct drm_device *dev)
>  	} else {
>  		dev_priv->gtt.gtt_probe = gen6_gmch_probe;
>  		dev_priv->gtt.gtt_remove = gen6_gmch_remove;
> -		dev_priv->gtt.pte_encode = gen6_pte_encode;
> +		if (IS_VALLEYVIEW(dev)) {
> +			dev_priv->gtt.pte_encode = byt_pte_encode;
> +		} else {
> +			dev_priv->gtt.pte_encode = gen6_pte_encode;
> +		}

The rest looks good. With the bikesheds addressed (by patches or
counter-arguments ;)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

>  	}
>  
>  	ret = dev_priv->gtt.gtt_probe(dev, &dev_priv->gtt.total,
> -- 
> 1.8.2.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 3/3] drm/i915: Split out Haswell code from gen6_pte_encode.

[Jani Nikula]

On Thu, 18 Apr 2013, Kenneth Graunke <kenneth@whitecape.org> wrote:
> Now that we have function pointers, it's cleaner to just create a new
> per-platform PTE encoding function.
>
> This should be identical in behavior to the previous code.

It does drop the extra paranoia BUG() on unknown cache level. We should
have seen those by now, so I don't mind.

Please drop the inline here too. Otherwise,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


>
> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 32 +++++++++++++++++++++-----------
>  1 file changed, 21 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index db5c654..034a502 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -53,20 +53,13 @@ static inline gen6_gtt_pte_t gen6_pte_encode(struct drm_device *dev,
>  
>  	switch (level) {
>  	case I915_CACHE_LLC_MLC:
> -		/* Haswell doesn't set L3 this way */
> -		if (IS_HASWELL(dev))
> -			pte |= GEN6_PTE_CACHE_LLC;
> -		else
> -			pte |= GEN6_PTE_CACHE_LLC_MLC;
> +		pte |= GEN6_PTE_CACHE_LLC_MLC;
>  		break;
>  	case I915_CACHE_LLC:
>  		pte |= GEN6_PTE_CACHE_LLC;
>  		break;
>  	case I915_CACHE_NONE:
> -		if (IS_HASWELL(dev))
> -			pte |= HSW_PTE_UNCACHED;
> -		else
> -			pte |= GEN6_PTE_UNCACHED;
> +		pte |= GEN6_PTE_UNCACHED;
>  		break;
>  	default:
>  		BUG();
> @@ -96,6 +89,19 @@ static inline gen6_gtt_pte_t byt_pte_encode(struct drm_device *dev,
>  	return pte;
>  }
>  
> +static inline gen6_gtt_pte_t hsw_pte_encode(struct drm_device *dev,
> +					    dma_addr_t addr,
> +					    enum i915_cache_level level)
> +{
> +	gen6_gtt_pte_t pte = GEN6_PTE_VALID;
> +	pte |= GEN6_PTE_ADDR_ENCODE(addr);
> +
> +	if (level != I915_CACHE_NONE)
> +		pte |= GEN6_PTE_CACHE_LLC;
> +
> +	return pte;
> +}
> +
>  static int gen6_ppgtt_enable(struct drm_device *dev)
>  {
>  	drm_i915_private_t *dev_priv = dev->dev_private;
> @@ -257,7 +263,9 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
>  	first_pd_entry_in_global_pt =
>  		gtt_total_entries(dev_priv->gtt) - I915_PPGTT_PD_ENTRIES;
>  
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_HASWELL(dev)) {
> +		ppgtt->pte_encode = hsw_pte_encode;
> +	} else if (IS_VALLEYVIEW(dev)) {
>  		ppgtt->pte_encode = byt_pte_encode;
>  	} else {
>  		ppgtt->pte_encode = gen6_pte_encode;
> @@ -851,7 +859,9 @@ int i915_gem_gtt_init(struct drm_device *dev)
>  	} else {
>  		dev_priv->gtt.gtt_probe = gen6_gmch_probe;
>  		dev_priv->gtt.gtt_remove = gen6_gmch_remove;
> -		if (IS_VALLEYVIEW(dev)) {
> +		if (IS_HASWELL(dev)) {
> +			dev_priv->gtt.pte_encode = hsw_pte_encode;
> +		} else if (IS_VALLEYVIEW(dev)) {
>  			dev_priv->gtt.pte_encode = byt_pte_encode;
>  		} else {
>  			dev_priv->gtt.pte_encode = gen6_pte_encode;
> -- 
> 1.8.2.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 2/3] drm/i915: Fix page table entries for Bay Trail.

[Kenneth Graunke]

On Bay Trail, bit 1 means "writeable by the GPU."  Failing to set that
means basically anything using the GPU will cause hangs.

v2: Drop accidental inline keyword on byt_pte_encode.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jani Nikula <jani.nikula@intel.com> [v1]
Tested-by: Daniel Leung <daniel.leung@linux.intel.com> [v1]
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 33 +++++++++++++++++++++++++++++++--
 1 file changed, 31 insertions(+), 2 deletions(-)

To address Jani's comment about PPGTT - Daniel thinks Jesse has patches
for aliasing PPGTT floating around that could land at some point.  Also,
if we get real PPGTT, we'll also need this.  Either way, setting it up
is trivial and leaving it out could lead to bugs later.

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 92e147f..62058dc 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -73,6 +73,27 @@ static gen6_gtt_pte_t gen6_pte_encode(struct drm_device *dev,
 	return pte;
 }
 
+#define BYT_PTE_WRITEABLE		(1 << 1)
+#define BYT_PTE_SNOOPED_BY_CPU_CACHES	(1 << 2)
+
+static gen6_gtt_pte_t byt_pte_encode(struct drm_device *dev,
+				     dma_addr_t addr,
+				     enum i915_cache_level level)
+{
+	gen6_gtt_pte_t pte = GEN6_PTE_VALID;
+	pte |= GEN6_PTE_ADDR_ENCODE(addr);
+
+	/* Mark the page as writeable.  Other platforms don't have a
+	 * setting for read-only/writable, so this matches that behavior.
+	 */
+	pte |= BYT_PTE_WRITEABLE;
+
+	if (level != I915_CACHE_NONE)
+		pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
+
+	return pte;
+}
+
 static int gen6_ppgtt_enable(struct drm_device *dev)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
@@ -234,7 +255,11 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
 	first_pd_entry_in_global_pt =
 		gtt_total_entries(dev_priv->gtt) - I915_PPGTT_PD_ENTRIES;
 
-	ppgtt->pte_encode = gen6_pte_encode;
+	if (IS_VALLEYVIEW(dev)) {
+		ppgtt->pte_encode = byt_pte_encode;
+	} else {
+		ppgtt->pte_encode = gen6_pte_encode;
+	}
 	ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES;
 	ppgtt->enable = gen6_ppgtt_enable;
 	ppgtt->clear_range = gen6_ppgtt_clear_range;
@@ -824,7 +849,11 @@ int i915_gem_gtt_init(struct drm_device *dev)
 	} else {
 		dev_priv->gtt.gtt_probe = gen6_gmch_probe;
 		dev_priv->gtt.gtt_remove = gen6_gmch_remove;
-		dev_priv->gtt.pte_encode = gen6_pte_encode;
+		if (IS_VALLEYVIEW(dev)) {
+			dev_priv->gtt.pte_encode = byt_pte_encode;
+		} else {
+			dev_priv->gtt.pte_encode = gen6_pte_encode;
+		}
 	}
 
 	ret = dev_priv->gtt.gtt_probe(dev, &dev_priv->gtt.total,
-- 
1.8.2.1