[Intel-gfx] [PATCH v2 1/3] drm/i915/power: move dc state members to struct i915_power_domains

[Intel-gfx] [PATCH v2 1/3] drm/i915/power: move dc state members to struct i915_power_domains

[Jani Nikula]

There's only one reference to the struct intel_dmc members dc_state,
target_dc_state, and allowed_dc_mask within intel_dmc.c, begging the
question why they are under struct intel_dmc to begin with.

Moreover, the only references to i915->display.dmc outside of
intel_dmc.c are to these members.

They don't belong. Move them from struct intel_dmc to struct
i915_power_domains, which seems like a more suitable place.

Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 .../drm/i915/display/intel_display_power.c    | 25 ++++++++-------
 .../drm/i915/display/intel_display_power.h    |  4 +++
 .../i915/display/intel_display_power_well.c   | 31 +++++++++++--------
 drivers/gpu/drm/i915/display/intel_dmc.c      |  3 +-
 drivers/gpu/drm/i915/display/intel_dmc.h      |  3 --
 drivers/gpu/drm/i915/display/intel_psr.c      |  3 +-
 6 files changed, 39 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 7222502a760c..4ed7e50e1c21 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -264,9 +264,10 @@ bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 }
 
 static u32
-sanitize_target_dc_state(struct drm_i915_private *dev_priv,
+sanitize_target_dc_state(struct drm_i915_private *i915,
 			 u32 target_dc_state)
 {
+	struct i915_power_domains *power_domains = &i915->display.power.domains;
 	static const u32 states[] = {
 		DC_STATE_EN_UPTO_DC6,
 		DC_STATE_EN_UPTO_DC5,
@@ -279,7 +280,7 @@ sanitize_target_dc_state(struct drm_i915_private *dev_priv,
 		if (target_dc_state != states[i])
 			continue;
 
-		if (dev_priv->display.dmc.allowed_dc_mask & target_dc_state)
+		if (power_domains->allowed_dc_mask & target_dc_state)
 			break;
 
 		target_dc_state = states[i + 1];
@@ -312,7 +313,7 @@ void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
 
 	state = sanitize_target_dc_state(dev_priv, state);
 
-	if (state == dev_priv->display.dmc.target_dc_state)
+	if (state == power_domains->target_dc_state)
 		goto unlock;
 
 	dc_off_enabled = intel_power_well_is_enabled(dev_priv, power_well);
@@ -323,7 +324,7 @@ void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
 	if (!dc_off_enabled)
 		intel_power_well_enable(dev_priv, power_well);
 
-	dev_priv->display.dmc.target_dc_state = state;
+	power_domains->target_dc_state = state;
 
 	if (!dc_off_enabled)
 		intel_power_well_disable(dev_priv, power_well);
@@ -992,10 +993,10 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
 	dev_priv->params.disable_power_well =
 		sanitize_disable_power_well_option(dev_priv,
 						   dev_priv->params.disable_power_well);
-	dev_priv->display.dmc.allowed_dc_mask =
+	power_domains->allowed_dc_mask =
 		get_allowed_dc_mask(dev_priv, dev_priv->params.enable_dc);
 
-	dev_priv->display.dmc.target_dc_state =
+	power_domains->target_dc_state =
 		sanitize_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
 
 	mutex_init(&power_domains->lock);
@@ -2053,7 +2054,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915,
 	 * resources as required and also enable deeper system power states
 	 * that would be blocked if the firmware was inactive.
 	 */
-	if (!(i915->display.dmc.allowed_dc_mask & DC_STATE_EN_DC9) &&
+	if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC9) &&
 	    suspend_mode == I915_DRM_SUSPEND_IDLE &&
 	    intel_dmc_has_payload(i915)) {
 		intel_display_power_flush_work(i915);
@@ -2242,22 +2243,22 @@ void intel_display_power_suspend(struct drm_i915_private *i915)
 
 void intel_display_power_resume(struct drm_i915_private *i915)
 {
+	struct i915_power_domains *power_domains = &i915->display.power.domains;
+
 	if (DISPLAY_VER(i915) >= 11) {
 		bxt_disable_dc9(i915);
 		icl_display_core_init(i915, true);
 		if (intel_dmc_has_payload(i915)) {
-			if (i915->display.dmc.allowed_dc_mask &
-			    DC_STATE_EN_UPTO_DC6)
+			if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
 				skl_enable_dc6(i915);
-			else if (i915->display.dmc.allowed_dc_mask &
-				 DC_STATE_EN_UPTO_DC5)
+			else if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
 				gen9_enable_dc5(i915);
 		}
 	} else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
 		bxt_disable_dc9(i915);
 		bxt_display_core_init(i915, true);
 		if (intel_dmc_has_payload(i915) &&
-		    (i915->display.dmc.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
+		    (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
 			gen9_enable_dc5(i915);
 	} else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
 		hsw_disable_pc8(i915);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 2154d900b1aa..8e96be8e6330 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -137,6 +137,10 @@ struct i915_power_domains {
 	bool display_core_suspended;
 	int power_well_count;
 
+	u32 dc_state;
+	u32 target_dc_state;
+	u32 allowed_dc_mask;
+
 	intel_wakeref_t init_wakeref;
 	intel_wakeref_t disable_wakeref;
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 56a20bf5825b..57df9fc985bf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -713,19 +713,20 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
 	return mask;
 }
 
-void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv)
+void gen9_sanitize_dc_state(struct drm_i915_private *i915)
 {
+	struct i915_power_domains *power_domains = &i915->display.power.domains;
 	u32 val;
 
-	if (!HAS_DISPLAY(dev_priv))
+	if (!HAS_DISPLAY(i915))
 		return;
 
-	val = intel_de_read(dev_priv, DC_STATE_EN) & gen9_dc_mask(dev_priv);
+	val = intel_de_read(i915, DC_STATE_EN) & gen9_dc_mask(i915);
 
-	drm_dbg_kms(&dev_priv->drm,
+	drm_dbg_kms(&i915->drm,
 		    "Resetting DC state tracking from %02x to %02x\n",
-		    dev_priv->display.dmc.dc_state, val);
-	dev_priv->display.dmc.dc_state = val;
+		    power_domains->dc_state, val);
+	power_domains->dc_state = val;
 }
 
 /**
@@ -753,6 +754,7 @@ void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv)
  */
 void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
 {
+	struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
 	u32 val;
 	u32 mask;
 
@@ -760,8 +762,8 @@ void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
 		return;
 
 	if (drm_WARN_ON_ONCE(&dev_priv->drm,
-			     state & ~dev_priv->display.dmc.allowed_dc_mask))
-		state &= dev_priv->display.dmc.allowed_dc_mask;
+			     state & ~power_domains->allowed_dc_mask))
+		state &= power_domains->allowed_dc_mask;
 
 	val = intel_de_read(dev_priv, DC_STATE_EN);
 	mask = gen9_dc_mask(dev_priv);
@@ -769,16 +771,16 @@ void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
 		    val & mask, state);
 
 	/* Check if DMC is ignoring our DC state requests */
-	if ((val & mask) != dev_priv->display.dmc.dc_state)
+	if ((val & mask) != power_domains->dc_state)
 		drm_err(&dev_priv->drm, "DC state mismatch (0x%x -> 0x%x)\n",
-			dev_priv->display.dmc.dc_state, val & mask);
+			power_domains->dc_state, val & mask);
 
 	val &= ~mask;
 	val |= state;
 
 	gen9_write_dc_state(dev_priv, val);
 
-	dev_priv->display.dmc.dc_state = val & mask;
+	power_domains->dc_state = val & mask;
 }
 
 static void tgl_enable_dc3co(struct drm_i915_private *dev_priv)
@@ -970,9 +972,10 @@ static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
 
 void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
 {
+	struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
 	struct intel_cdclk_config cdclk_config = {};
 
-	if (dev_priv->display.dmc.target_dc_state == DC_STATE_EN_DC3CO) {
+	if (power_domains->target_dc_state == DC_STATE_EN_DC3CO) {
 		tgl_disable_dc3co(dev_priv);
 		return;
 	}
@@ -1011,10 +1014,12 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
 					   struct i915_power_well *power_well)
 {
+	struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
+
 	if (!intel_dmc_has_payload(dev_priv))
 		return;
 
-	switch (dev_priv->display.dmc.target_dc_state) {
+	switch (power_domains->target_dc_state) {
 	case DC_STATE_EN_DC3CO:
 		tgl_enable_dc3co(dev_priv);
 		break;
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index f70ada2357dc..ab4fdedd4c5f 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -449,6 +449,7 @@ void intel_dmc_disable_pipe(struct drm_i915_private *i915, enum pipe pipe)
  */
 void intel_dmc_load_program(struct drm_i915_private *dev_priv)
 {
+	struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
 	struct intel_dmc *dmc = &dev_priv->display.dmc;
 	enum intel_dmc_id dmc_id;
 	u32 i;
@@ -481,7 +482,7 @@ void intel_dmc_load_program(struct drm_i915_private *dev_priv)
 		}
 	}
 
-	dev_priv->display.dmc.dc_state = 0;
+	power_domains->dc_state = 0;
 
 	gen9_set_dc_state_debugmask(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index c9808bbe7162..90910cecc2f6 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -40,9 +40,6 @@ struct intel_dmc {
 		bool present;
 	} dmc_info[DMC_FW_MAX];
 
-	u32 dc_state;
-	u32 target_dc_state;
-	u32 allowed_dc_mask;
 	intel_wakeref_t wakeref;
 };
 
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 2954759e9d12..cf13580af34a 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -702,6 +702,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
 {
 	const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay;
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+	struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
 	u32 exit_scanlines;
 
 	/*
@@ -718,7 +719,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
 	if (crtc_state->enable_psr2_sel_fetch)
 		return;
 
-	if (!(dev_priv->display.dmc.allowed_dc_mask & DC_STATE_EN_DC3CO))
+	if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC3CO))
 		return;
 
 	if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state))
-- 
2.34.1

[Intel-gfx] [PATCH v2 2/3] drm/i915/dmc: add i915_to_dmc() and dmc->i915 and use them

[Jani Nikula]

Start preparing for dynamically allocated struct intel_dmc by adding
i915_to_dmc() and dmc->i915, and using them.

Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dmc.c | 90 ++++++++++++++----------
 drivers/gpu/drm/i915/display/intel_dmc.h |  1 +
 2 files changed, 55 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index ab4fdedd4c5f..1d156ac2eb4c 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -38,6 +38,11 @@
  * low-power state and comes back to normal.
  */
 
+static struct intel_dmc *i915_to_dmc(struct drm_i915_private *i915)
+{
+	return &i915->display.dmc;
+}
+
 #define DMC_VERSION(major, minor)	((major) << 16 | (minor))
 #define DMC_VERSION_MAJOR(version)	((version) >> 16)
 #define DMC_VERSION_MINOR(version)	((version) & 0xffff)
@@ -259,7 +264,9 @@ static bool is_valid_dmc_id(enum intel_dmc_id dmc_id)
 
 static bool has_dmc_id_fw(struct drm_i915_private *i915, enum intel_dmc_id dmc_id)
 {
-	return i915->display.dmc.dmc_info[dmc_id].payload;
+	struct intel_dmc *dmc = i915_to_dmc(i915);
+
+	return dmc && dmc->dmc_info[dmc_id].payload;
 }
 
 bool intel_dmc_has_payload(struct drm_i915_private *i915)
@@ -450,7 +457,7 @@ void intel_dmc_disable_pipe(struct drm_i915_private *i915, enum pipe pipe)
 void intel_dmc_load_program(struct drm_i915_private *dev_priv)
 {
 	struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
-	struct intel_dmc *dmc = &dev_priv->display.dmc;
+	struct intel_dmc *dmc = i915_to_dmc(dev_priv);
 	enum intel_dmc_id dmc_id;
 	u32 i;
 
@@ -515,8 +522,11 @@ void intel_dmc_disable_program(struct drm_i915_private *i915)
 
 void assert_dmc_loaded(struct drm_i915_private *i915)
 {
-	drm_WARN_ONCE(&i915->drm,
-		      !intel_de_read(i915, DMC_PROGRAM(i915->display.dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
+	struct intel_dmc *dmc = i915_to_dmc(i915);
+
+	drm_WARN_ONCE(&i915->drm, !dmc, "DMC not initialized\n");
+	drm_WARN_ONCE(&i915->drm, dmc &&
+		      !intel_de_read(i915, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
 		      "DMC program storage start is NULL\n");
 	drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_SSP_BASE),
 		      "DMC SSP Base Not fine\n");
@@ -551,11 +561,10 @@ static void dmc_set_fw_offset(struct intel_dmc *dmc,
 			      const struct stepping_info *si,
 			      u8 package_ver)
 {
+	struct drm_i915_private *i915 = dmc->i915;
 	enum intel_dmc_id dmc_id;
 	unsigned int i;
 
-	struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), display.dmc);
-
 	for (i = 0; i < num_entries; i++) {
 		dmc_id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id;
 
@@ -582,7 +591,7 @@ static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc,
 				       const u32 *mmioaddr, u32 mmio_count,
 				       int header_ver, enum intel_dmc_id dmc_id)
 {
-	struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), display.dmc);
+	struct drm_i915_private *i915 = dmc->i915;
 	u32 start_range, end_range;
 	int i;
 
@@ -615,7 +624,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
 			       const struct intel_dmc_header_base *dmc_header,
 			       size_t rem_size, enum intel_dmc_id dmc_id)
 {
-	struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), display.dmc);
+	struct drm_i915_private *i915 = dmc->i915;
 	struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id];
 	unsigned int header_len_bytes, dmc_header_size, payload_size, i;
 	const u32 *mmioaddr, *mmiodata;
@@ -726,7 +735,7 @@ parse_dmc_fw_package(struct intel_dmc *dmc,
 		     const struct stepping_info *si,
 		     size_t rem_size)
 {
-	struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), display.dmc);
+	struct drm_i915_private *i915 = dmc->i915;
 	u32 package_size = sizeof(struct intel_package_header);
 	u32 num_entries, max_entries;
 	const struct intel_fw_info *fw_info;
@@ -780,7 +789,7 @@ static u32 parse_dmc_fw_css(struct intel_dmc *dmc,
 			    struct intel_css_header *css_header,
 			    size_t rem_size)
 {
-	struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), display.dmc);
+	struct drm_i915_private *i915 = dmc->i915;
 
 	if (rem_size < sizeof(struct intel_css_header)) {
 		drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n");
@@ -800,13 +809,12 @@ static u32 parse_dmc_fw_css(struct intel_dmc *dmc,
 	return sizeof(struct intel_css_header);
 }
 
-static void parse_dmc_fw(struct drm_i915_private *dev_priv,
-			 const struct firmware *fw)
+static void parse_dmc_fw(struct intel_dmc *dmc, const struct firmware *fw)
 {
+	struct drm_i915_private *dev_priv = dmc->i915;
 	struct intel_css_header *css_header;
 	struct intel_package_header *package_header;
 	struct intel_dmc_header_base *dmc_header;
-	struct intel_dmc *dmc = &dev_priv->display.dmc;
 	struct stepping_info display_info = { '*', '*'};
 	const struct stepping_info *si = intel_get_stepping_info(dev_priv, &display_info);
 	enum intel_dmc_id dmc_id;
@@ -833,7 +841,7 @@ static void parse_dmc_fw(struct drm_i915_private *dev_priv,
 	readcount += r;
 
 	for_each_dmc_id(dmc_id) {
-		if (!dev_priv->display.dmc.dmc_info[dmc_id].present)
+		if (!dmc->dmc_info[dmc_id].present)
 			continue;
 
 		offset = readcount + dmc->dmc_info[dmc_id].dmc_offset * 4;
@@ -872,16 +880,13 @@ static const char *dmc_fallback_path(struct drm_i915_private *i915)
 
 static void dmc_load_work_fn(struct work_struct *work)
 {
-	struct drm_i915_private *dev_priv;
-	struct intel_dmc *dmc;
+	struct intel_dmc *dmc = container_of(work, typeof(*dmc), work);
+	struct drm_i915_private *dev_priv = dmc->i915;
 	const struct firmware *fw = NULL;
 	const char *fallback_path;
 	int err;
 
-	dev_priv = container_of(work, typeof(*dev_priv), display.dmc.work);
-	dmc = &dev_priv->display.dmc;
-
-	err = request_firmware(&fw, dev_priv->display.dmc.fw_path, dev_priv->drm.dev);
+	err = request_firmware(&fw, dmc->fw_path, dev_priv->drm.dev);
 
 	if (err == -ENOENT && !dev_priv->params.dmc_firmware_path) {
 		fallback_path = dmc_fallback_path(dev_priv);
@@ -892,11 +897,11 @@ static void dmc_load_work_fn(struct work_struct *work)
 				    fallback_path);
 			err = request_firmware(&fw, fallback_path, dev_priv->drm.dev);
 			if (err == 0)
-				dev_priv->display.dmc.fw_path = fallback_path;
+				dmc->fw_path = fallback_path;
 		}
 	}
 
-	parse_dmc_fw(dev_priv, fw);
+	parse_dmc_fw(dmc, fw);
 
 	if (intel_dmc_has_payload(dev_priv)) {
 		intel_dmc_load_program(dev_priv);
@@ -904,7 +909,7 @@ static void dmc_load_work_fn(struct work_struct *work)
 
 		drm_info(&dev_priv->drm,
 			 "Finished loading DMC firmware %s (v%u.%u)\n",
-			 dev_priv->display.dmc.fw_path, DMC_VERSION_MAJOR(dmc->version),
+			 dmc->fw_path, DMC_VERSION_MAJOR(dmc->version),
 			 DMC_VERSION_MINOR(dmc->version));
 	} else {
 		drm_notice(&dev_priv->drm,
@@ -927,13 +932,16 @@ static void dmc_load_work_fn(struct work_struct *work)
  */
 void intel_dmc_init(struct drm_i915_private *dev_priv)
 {
-	struct intel_dmc *dmc = &dev_priv->display.dmc;
-
-	INIT_WORK(&dev_priv->display.dmc.work, dmc_load_work_fn);
+	struct intel_dmc *dmc;
 
 	if (!HAS_DMC(dev_priv))
 		return;
 
+	dmc = i915_to_dmc(dev_priv);
+	dmc->i915 = dev_priv;
+
+	INIT_WORK(&dmc->work, dmc_load_work_fn);
+
 	/*
 	 * Obtain a runtime pm reference, until DMC is loaded, to avoid entering
 	 * runtime-suspend.
@@ -999,7 +1007,7 @@ void intel_dmc_init(struct drm_i915_private *dev_priv)
 	}
 
 	drm_dbg_kms(&dev_priv->drm, "Loading %s\n", dmc->fw_path);
-	schedule_work(&dev_priv->display.dmc.work);
+	schedule_work(&dmc->work);
 }
 
 /**
@@ -1012,10 +1020,13 @@ void intel_dmc_init(struct drm_i915_private *dev_priv)
  */
 void intel_dmc_suspend(struct drm_i915_private *dev_priv)
 {
+	struct intel_dmc *dmc = i915_to_dmc(dev_priv);
+
 	if (!HAS_DMC(dev_priv))
 		return;
 
-	flush_work(&dev_priv->display.dmc.work);
+	if (dmc)
+		flush_work(&dmc->work);
 
 	/* Drop the reference held in case DMC isn't loaded. */
 	if (!intel_dmc_has_payload(dev_priv))
@@ -1051,6 +1062,7 @@ void intel_dmc_resume(struct drm_i915_private *dev_priv)
  */
 void intel_dmc_fini(struct drm_i915_private *dev_priv)
 {
+	struct intel_dmc *dmc = i915_to_dmc(dev_priv);
 	enum intel_dmc_id dmc_id;
 
 	if (!HAS_DMC(dev_priv))
@@ -1059,36 +1071,42 @@ void intel_dmc_fini(struct drm_i915_private *dev_priv)
 	intel_dmc_suspend(dev_priv);
 	drm_WARN_ON(&dev_priv->drm, dev_priv->display.dmc.wakeref);
 
-	for_each_dmc_id(dmc_id)
-		kfree(dev_priv->display.dmc.dmc_info[dmc_id].payload);
+	if (dmc) {
+		for_each_dmc_id(dmc_id)
+			kfree(dmc->dmc_info[dmc_id].payload);
+	}
 }
 
 void intel_dmc_print_error_state(struct drm_i915_error_state_buf *m,
 				 struct drm_i915_private *i915)
 {
-	struct intel_dmc *dmc = &i915->display.dmc;
+	struct intel_dmc *dmc = i915_to_dmc(i915);
 
 	if (!HAS_DMC(i915))
 		return;
 
+	i915_error_printf(m, "DMC initialized: %s\n", str_yes_no(dmc));
 	i915_error_printf(m, "DMC loaded: %s\n",
 			  str_yes_no(intel_dmc_has_payload(i915)));
-	i915_error_printf(m, "DMC fw version: %d.%d\n",
-			  DMC_VERSION_MAJOR(dmc->version),
-			  DMC_VERSION_MINOR(dmc->version));
+	if (dmc)
+		i915_error_printf(m, "DMC fw version: %d.%d\n",
+				  DMC_VERSION_MAJOR(dmc->version),
+				  DMC_VERSION_MINOR(dmc->version));
 }
 
 static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
 {
 	struct drm_i915_private *i915 = m->private;
+	struct intel_dmc *dmc = i915_to_dmc(i915);
 	intel_wakeref_t wakeref;
-	struct intel_dmc *dmc;
 	i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG;
 
 	if (!HAS_DMC(i915))
 		return -ENODEV;
 
-	dmc = &i915->display.dmc;
+	seq_printf(m, "DMC initialized: %s\n", str_yes_no(dmc));
+	if (!dmc)
+		return 0;
 
 	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
 
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index 90910cecc2f6..b74635497aa7 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -25,6 +25,7 @@ enum intel_dmc_id {
 };
 
 struct intel_dmc {
+	struct drm_i915_private *i915;
 	struct work_struct work;
 	const char *fw_path;
 	u32 max_fw_size; /* bytes */
-- 
2.34.1

[Intel-gfx] [PATCH v2 3/3] drm/i915/dmc: allocate dmc structure dynamically

[Jani Nikula]

sizeof(struct intel_dmc) > 1024 bytes, allocated on all platforms as
part of struct drm_i915_private, whether they have DMC or not.

Allocate struct intel_dmc dynamically, and hide all the dmc details
behind an opaque pointer in intel_dmc.c.

Care must be taken to take into account all cases: DMC not supported on
the platform, DMC supported but not initialized, and DMC initialized but
not loaded. For the second case, we need to move the wakeref out of
struct intel_dmc.

Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 .../gpu/drm/i915/display/intel_display_core.h |  8 ++-
 drivers/gpu/drm/i915/display/intel_dmc.c      | 50 +++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_dmc.h      | 34 +------------
 .../drm/i915/display/intel_modeset_setup.c    |  1 +
 4 files changed, 53 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index b870f7f47f2b..ff51149c5fcb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -19,7 +19,6 @@
 #include "intel_cdclk.h"
 #include "intel_display_limits.h"
 #include "intel_display_power.h"
-#include "intel_dmc.h"
 #include "intel_dpll_mgr.h"
 #include "intel_fbc.h"
 #include "intel_global_state.h"
@@ -40,6 +39,7 @@ struct intel_cdclk_vals;
 struct intel_color_funcs;
 struct intel_crtc;
 struct intel_crtc_state;
+struct intel_dmc;
 struct intel_dpll_funcs;
 struct intel_dpll_mgr;
 struct intel_fbdev;
@@ -340,6 +340,11 @@ struct intel_display {
 		spinlock_t phy_lock;
 	} dkl;
 
+	struct {
+		struct intel_dmc *dmc;
+		intel_wakeref_t wakeref;
+	} dmc;
+
 	struct {
 		/* VLV/CHV/BXT/GLK DSI MMIO register base address */
 		u32 mmio_base;
@@ -467,7 +472,6 @@ struct intel_display {
 
 	/* Grouping using named structs. Keep sorted. */
 	struct intel_audio audio;
-	struct intel_dmc dmc;
 	struct intel_dpll dpll;
 	struct intel_fbc *fbc[I915_MAX_FBCS];
 	struct intel_frontbuffer_tracking fb_tracking;
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 1d156ac2eb4c..8428d08e0c3d 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -38,9 +38,37 @@
  * low-power state and comes back to normal.
  */
 
+enum intel_dmc_id {
+	DMC_FW_MAIN = 0,
+	DMC_FW_PIPEA,
+	DMC_FW_PIPEB,
+	DMC_FW_PIPEC,
+	DMC_FW_PIPED,
+	DMC_FW_MAX
+};
+
+struct intel_dmc {
+	struct drm_i915_private *i915;
+	struct work_struct work;
+	const char *fw_path;
+	u32 max_fw_size; /* bytes */
+	u32 version;
+	struct dmc_fw_info {
+		u32 mmio_count;
+		i915_reg_t mmioaddr[20];
+		u32 mmiodata[20];
+		u32 dmc_offset;
+		u32 start_mmioaddr;
+		u32 dmc_fw_size; /*dwords */
+		u32 *payload;
+		bool present;
+	} dmc_info[DMC_FW_MAX];
+};
+
+/* Note: This may be NULL. */
 static struct intel_dmc *i915_to_dmc(struct drm_i915_private *i915)
 {
-	return &i915->display.dmc;
+	return i915->display.dmc.dmc;
 }
 
 #define DMC_VERSION(major, minor)	((major) << 16 | (minor))
@@ -937,7 +965,10 @@ void intel_dmc_init(struct drm_i915_private *dev_priv)
 	if (!HAS_DMC(dev_priv))
 		return;
 
-	dmc = i915_to_dmc(dev_priv);
+	dmc = kzalloc(sizeof(*dmc), GFP_KERNEL);
+	if (!dmc)
+		return;
+
 	dmc->i915 = dev_priv;
 
 	INIT_WORK(&dmc->work, dmc_load_work_fn);
@@ -991,10 +1022,9 @@ void intel_dmc_init(struct drm_i915_private *dev_priv)
 
 	if (dev_priv->params.dmc_firmware_path) {
 		if (strlen(dev_priv->params.dmc_firmware_path) == 0) {
-			dmc->fw_path = NULL;
 			drm_info(&dev_priv->drm,
 				 "Disabling DMC firmware and runtime PM\n");
-			return;
+			goto out;
 		}
 
 		dmc->fw_path = dev_priv->params.dmc_firmware_path;
@@ -1003,11 +1033,18 @@ void intel_dmc_init(struct drm_i915_private *dev_priv)
 	if (!dmc->fw_path) {
 		drm_dbg_kms(&dev_priv->drm,
 			    "No known DMC firmware for platform, disabling runtime PM\n");
-		return;
+		goto out;
 	}
 
+	dev_priv->display.dmc.dmc = dmc;
+
 	drm_dbg_kms(&dev_priv->drm, "Loading %s\n", dmc->fw_path);
 	schedule_work(&dmc->work);
+
+	return;
+
+out:
+	kfree(dmc);
 }
 
 /**
@@ -1074,6 +1111,9 @@ void intel_dmc_fini(struct drm_i915_private *dev_priv)
 	if (dmc) {
 		for_each_dmc_id(dmc_id)
 			kfree(dmc->dmc_info[dmc_id].payload);
+
+		kfree(dmc);
+		dev_priv->display.dmc.dmc = NULL;
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index b74635497aa7..fd607afff2ef 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -6,44 +6,12 @@
 #ifndef __INTEL_DMC_H__
 #define __INTEL_DMC_H__
 
-#include "i915_reg_defs.h"
-#include "intel_wakeref.h"
-#include <linux/workqueue.h>
+#include <linux/types.h>
 
 struct drm_i915_error_state_buf;
 struct drm_i915_private;
-
 enum pipe;
 
-enum intel_dmc_id {
-	DMC_FW_MAIN = 0,
-	DMC_FW_PIPEA,
-	DMC_FW_PIPEB,
-	DMC_FW_PIPEC,
-	DMC_FW_PIPED,
-	DMC_FW_MAX
-};
-
-struct intel_dmc {
-	struct drm_i915_private *i915;
-	struct work_struct work;
-	const char *fw_path;
-	u32 max_fw_size; /* bytes */
-	u32 version;
-	struct dmc_fw_info {
-		u32 mmio_count;
-		i915_reg_t mmioaddr[20];
-		u32 mmiodata[20];
-		u32 dmc_offset;
-		u32 start_mmioaddr;
-		u32 dmc_fw_size; /*dwords */
-		u32 *payload;
-		bool present;
-	} dmc_info[DMC_FW_MAX];
-
-	intel_wakeref_t wakeref;
-};
-
 void intel_dmc_init(struct drm_i915_private *i915);
 void intel_dmc_load_program(struct drm_i915_private *i915);
 void intel_dmc_disable_program(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index 5359b9663a07..42bfd56fcbe4 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -22,6 +22,7 @@
 #include "intel_display.h"
 #include "intel_display_power.h"
 #include "intel_display_types.h"
+#include "intel_dmc.h"
 #include "intel_modeset_setup.h"
 #include "intel_pch_display.h"
 #include "intel_pm.h"
-- 
2.34.1

Re: [Intel-gfx] [PATCH v2 3/3] drm/i915/dmc: allocate dmc structure dynamically

[Imre Deak]

On Thu, Feb 16, 2023 at 06:17:39PM +0200, Jani Nikula wrote:
> sizeof(struct intel_dmc) > 1024 bytes, allocated on all platforms as
> part of struct drm_i915_private, whether they have DMC or not.
> 
> Allocate struct intel_dmc dynamically, and hide all the dmc details
> behind an opaque pointer in intel_dmc.c.
> 
> Care must be taken to take into account all cases: DMC not supported on
> the platform, DMC supported but not initialized, and DMC initialized but
> not loaded. For the second case, we need to move the wakeref out of
> struct intel_dmc.
> 
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_display_core.h |  8 ++-
>  drivers/gpu/drm/i915/display/intel_dmc.c      | 50 +++++++++++++++++--
>  drivers/gpu/drm/i915/display/intel_dmc.h      | 34 +------------
>  .../drm/i915/display/intel_modeset_setup.c    |  1 +
>  4 files changed, 53 insertions(+), 40 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> index b870f7f47f2b..ff51149c5fcb 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -19,7 +19,6 @@
>  #include "intel_cdclk.h"
>  #include "intel_display_limits.h"
>  #include "intel_display_power.h"
> -#include "intel_dmc.h"
>  #include "intel_dpll_mgr.h"
>  #include "intel_fbc.h"
>  #include "intel_global_state.h"
> @@ -40,6 +39,7 @@ struct intel_cdclk_vals;
>  struct intel_color_funcs;
>  struct intel_crtc;
>  struct intel_crtc_state;
> +struct intel_dmc;
>  struct intel_dpll_funcs;
>  struct intel_dpll_mgr;
>  struct intel_fbdev;
> @@ -340,6 +340,11 @@ struct intel_display {
>  		spinlock_t phy_lock;
>  	} dkl;
>  
> +	struct {
> +		struct intel_dmc *dmc;
> +		intel_wakeref_t wakeref;
> +	} dmc;
> +
>  	struct {
>  		/* VLV/CHV/BXT/GLK DSI MMIO register base address */
>  		u32 mmio_base;
> @@ -467,7 +472,6 @@ struct intel_display {
>  
>  	/* Grouping using named structs. Keep sorted. */
>  	struct intel_audio audio;
> -	struct intel_dmc dmc;
>  	struct intel_dpll dpll;
>  	struct intel_fbc *fbc[I915_MAX_FBCS];
>  	struct intel_frontbuffer_tracking fb_tracking;
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index 1d156ac2eb4c..8428d08e0c3d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -38,9 +38,37 @@
>   * low-power state and comes back to normal.
>   */
>  
> +enum intel_dmc_id {
> +	DMC_FW_MAIN = 0,
> +	DMC_FW_PIPEA,
> +	DMC_FW_PIPEB,
> +	DMC_FW_PIPEC,
> +	DMC_FW_PIPED,
> +	DMC_FW_MAX
> +};
> +
> +struct intel_dmc {
> +	struct drm_i915_private *i915;
> +	struct work_struct work;
> +	const char *fw_path;
> +	u32 max_fw_size; /* bytes */
> +	u32 version;
> +	struct dmc_fw_info {
> +		u32 mmio_count;
> +		i915_reg_t mmioaddr[20];
> +		u32 mmiodata[20];
> +		u32 dmc_offset;
> +		u32 start_mmioaddr;
> +		u32 dmc_fw_size; /*dwords */
> +		u32 *payload;
> +		bool present;
> +	} dmc_info[DMC_FW_MAX];
> +};
> +
> +/* Note: This may be NULL. */
>  static struct intel_dmc *i915_to_dmc(struct drm_i915_private *i915)
>  {
> -	return &i915->display.dmc;
> +	return i915->display.dmc.dmc;
>  }
>  
>  #define DMC_VERSION(major, minor)	((major) << 16 | (minor))
> @@ -937,7 +965,10 @@ void intel_dmc_init(struct drm_i915_private *dev_priv)
>  	if (!HAS_DMC(dev_priv))
>  		return;
>  
> -	dmc = i915_to_dmc(dev_priv);
> +	dmc = kzalloc(sizeof(*dmc), GFP_KERNEL);
> +	if (!dmc)
> +		return;

Couldn't driver loading fail in this case instead (simplifying the
dmc==NULL checks elsewhere)?

> +
>  	dmc->i915 = dev_priv;
>  
>  	INIT_WORK(&dmc->work, dmc_load_work_fn);
> @@ -991,10 +1022,9 @@ void intel_dmc_init(struct drm_i915_private *dev_priv)
>  
>  	if (dev_priv->params.dmc_firmware_path) {
>  		if (strlen(dev_priv->params.dmc_firmware_path) == 0) {
> -			dmc->fw_path = NULL;
>  			drm_info(&dev_priv->drm,
>  				 "Disabling DMC firmware and runtime PM\n");
> -			return;
> +			goto out;
>  		}
>  
>  		dmc->fw_path = dev_priv->params.dmc_firmware_path;
> @@ -1003,11 +1033,18 @@ void intel_dmc_init(struct drm_i915_private *dev_priv)
>  	if (!dmc->fw_path) {
>  		drm_dbg_kms(&dev_priv->drm,
>  			    "No known DMC firmware for platform, disabling runtime PM\n");
> -		return;
> +		goto out;
>  	}
>  
> +	dev_priv->display.dmc.dmc = dmc;
> +
>  	drm_dbg_kms(&dev_priv->drm, "Loading %s\n", dmc->fw_path);
>  	schedule_work(&dmc->work);
> +
> +	return;
> +
> +out:
> +	kfree(dmc);
>  }
>  
>  /**
> @@ -1074,6 +1111,9 @@ void intel_dmc_fini(struct drm_i915_private *dev_priv)
>  	if (dmc) {
>  		for_each_dmc_id(dmc_id)
>  			kfree(dmc->dmc_info[dmc_id].payload);
> +
> +		kfree(dmc);
> +		dev_priv->display.dmc.dmc = NULL;
>  	}
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
> index b74635497aa7..fd607afff2ef 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.h
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.h
> @@ -6,44 +6,12 @@
>  #ifndef __INTEL_DMC_H__
>  #define __INTEL_DMC_H__
>  
> -#include "i915_reg_defs.h"
> -#include "intel_wakeref.h"
> -#include <linux/workqueue.h>
> +#include <linux/types.h>
>  
>  struct drm_i915_error_state_buf;
>  struct drm_i915_private;
> -
>  enum pipe;
>  
> -enum intel_dmc_id {
> -	DMC_FW_MAIN = 0,
> -	DMC_FW_PIPEA,
> -	DMC_FW_PIPEB,
> -	DMC_FW_PIPEC,
> -	DMC_FW_PIPED,
> -	DMC_FW_MAX
> -};
> -
> -struct intel_dmc {
> -	struct drm_i915_private *i915;
> -	struct work_struct work;
> -	const char *fw_path;
> -	u32 max_fw_size; /* bytes */
> -	u32 version;
> -	struct dmc_fw_info {
> -		u32 mmio_count;
> -		i915_reg_t mmioaddr[20];
> -		u32 mmiodata[20];
> -		u32 dmc_offset;
> -		u32 start_mmioaddr;
> -		u32 dmc_fw_size; /*dwords */
> -		u32 *payload;
> -		bool present;
> -	} dmc_info[DMC_FW_MAX];
> -
> -	intel_wakeref_t wakeref;
> -};
> -
>  void intel_dmc_init(struct drm_i915_private *i915);
>  void intel_dmc_load_program(struct drm_i915_private *i915);
>  void intel_dmc_disable_program(struct drm_i915_private *i915);
> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> index 5359b9663a07..42bfd56fcbe4 100644
> --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> @@ -22,6 +22,7 @@
>  #include "intel_display.h"
>  #include "intel_display_power.h"
>  #include "intel_display_types.h"
> +#include "intel_dmc.h"
>  #include "intel_modeset_setup.h"
>  #include "intel_pch_display.h"
>  #include "intel_pm.h"
> -- 
> 2.34.1
> 

Re: [Intel-gfx] [PATCH v2 3/3] drm/i915/dmc: allocate dmc structure dynamically

[Jani Nikula]

On Thu, 16 Feb 2023, Imre Deak <imre.deak@intel.com> wrote:
> On Thu, Feb 16, 2023 at 06:17:39PM +0200, Jani Nikula wrote:
>> sizeof(struct intel_dmc) > 1024 bytes, allocated on all platforms as
>> part of struct drm_i915_private, whether they have DMC or not.
>> 
>> Allocate struct intel_dmc dynamically, and hide all the dmc details
>> behind an opaque pointer in intel_dmc.c.
>> 
>> Care must be taken to take into account all cases: DMC not supported on
>> the platform, DMC supported but not initialized, and DMC initialized but
>> not loaded. For the second case, we need to move the wakeref out of
>> struct intel_dmc.
>> 
>> Cc: Imre Deak <imre.deak@intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>  .../gpu/drm/i915/display/intel_display_core.h |  8 ++-
>>  drivers/gpu/drm/i915/display/intel_dmc.c      | 50 +++++++++++++++++--
>>  drivers/gpu/drm/i915/display/intel_dmc.h      | 34 +------------
>>  .../drm/i915/display/intel_modeset_setup.c    |  1 +
>>  4 files changed, 53 insertions(+), 40 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
>> index b870f7f47f2b..ff51149c5fcb 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>> @@ -19,7 +19,6 @@
>>  #include "intel_cdclk.h"
>>  #include "intel_display_limits.h"
>>  #include "intel_display_power.h"
>> -#include "intel_dmc.h"
>>  #include "intel_dpll_mgr.h"
>>  #include "intel_fbc.h"
>>  #include "intel_global_state.h"
>> @@ -40,6 +39,7 @@ struct intel_cdclk_vals;
>>  struct intel_color_funcs;
>>  struct intel_crtc;
>>  struct intel_crtc_state;
>> +struct intel_dmc;
>>  struct intel_dpll_funcs;
>>  struct intel_dpll_mgr;
>>  struct intel_fbdev;
>> @@ -340,6 +340,11 @@ struct intel_display {
>>  		spinlock_t phy_lock;
>>  	} dkl;
>>  
>> +	struct {
>> +		struct intel_dmc *dmc;
>> +		intel_wakeref_t wakeref;
>> +	} dmc;
>> +
>>  	struct {
>>  		/* VLV/CHV/BXT/GLK DSI MMIO register base address */
>>  		u32 mmio_base;
>> @@ -467,7 +472,6 @@ struct intel_display {
>>  
>>  	/* Grouping using named structs. Keep sorted. */
>>  	struct intel_audio audio;
>> -	struct intel_dmc dmc;
>>  	struct intel_dpll dpll;
>>  	struct intel_fbc *fbc[I915_MAX_FBCS];
>>  	struct intel_frontbuffer_tracking fb_tracking;
>> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
>> index 1d156ac2eb4c..8428d08e0c3d 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
>> @@ -38,9 +38,37 @@
>>   * low-power state and comes back to normal.
>>   */
>>  
>> +enum intel_dmc_id {
>> +	DMC_FW_MAIN = 0,
>> +	DMC_FW_PIPEA,
>> +	DMC_FW_PIPEB,
>> +	DMC_FW_PIPEC,
>> +	DMC_FW_PIPED,
>> +	DMC_FW_MAX
>> +};
>> +
>> +struct intel_dmc {
>> +	struct drm_i915_private *i915;
>> +	struct work_struct work;
>> +	const char *fw_path;
>> +	u32 max_fw_size; /* bytes */
>> +	u32 version;
>> +	struct dmc_fw_info {
>> +		u32 mmio_count;
>> +		i915_reg_t mmioaddr[20];
>> +		u32 mmiodata[20];
>> +		u32 dmc_offset;
>> +		u32 start_mmioaddr;
>> +		u32 dmc_fw_size; /*dwords */
>> +		u32 *payload;
>> +		bool present;
>> +	} dmc_info[DMC_FW_MAX];
>> +};
>> +
>> +/* Note: This may be NULL. */
>>  static struct intel_dmc *i915_to_dmc(struct drm_i915_private *i915)
>>  {
>> -	return &i915->display.dmc;
>> +	return i915->display.dmc.dmc;
>>  }
>>  
>>  #define DMC_VERSION(major, minor)	((major) << 16 | (minor))
>> @@ -937,7 +965,10 @@ void intel_dmc_init(struct drm_i915_private *dev_priv)
>>  	if (!HAS_DMC(dev_priv))
>>  		return;
>>  
>> -	dmc = i915_to_dmc(dev_priv);
>> +	dmc = kzalloc(sizeof(*dmc), GFP_KERNEL);
>> +	if (!dmc)
>> +		return;
>
> Couldn't driver loading fail in this case instead (simplifying the
> dmc==NULL checks elsewhere)?

We could fail driver load, yes, but it still wouldn't simplify the NULL
checks because you could use i915.dmc_firmware_path="" to disable the
firmware, and what's the point in keeping the 1k memory allocated in
that case?

BR,
Jani.


>
>> +
>>  	dmc->i915 = dev_priv;
>>  
>>  	INIT_WORK(&dmc->work, dmc_load_work_fn);
>> @@ -991,10 +1022,9 @@ void intel_dmc_init(struct drm_i915_private *dev_priv)
>>  
>>  	if (dev_priv->params.dmc_firmware_path) {
>>  		if (strlen(dev_priv->params.dmc_firmware_path) == 0) {
>> -			dmc->fw_path = NULL;
>>  			drm_info(&dev_priv->drm,
>>  				 "Disabling DMC firmware and runtime PM\n");
>> -			return;
>> +			goto out;
>>  		}
>>  
>>  		dmc->fw_path = dev_priv->params.dmc_firmware_path;
>> @@ -1003,11 +1033,18 @@ void intel_dmc_init(struct drm_i915_private *dev_priv)
>>  	if (!dmc->fw_path) {
>>  		drm_dbg_kms(&dev_priv->drm,
>>  			    "No known DMC firmware for platform, disabling runtime PM\n");
>> -		return;
>> +		goto out;
>>  	}
>>  
>> +	dev_priv->display.dmc.dmc = dmc;
>> +
>>  	drm_dbg_kms(&dev_priv->drm, "Loading %s\n", dmc->fw_path);
>>  	schedule_work(&dmc->work);
>> +
>> +	return;
>> +
>> +out:
>> +	kfree(dmc);
>>  }
>>  
>>  /**
>> @@ -1074,6 +1111,9 @@ void intel_dmc_fini(struct drm_i915_private *dev_priv)
>>  	if (dmc) {
>>  		for_each_dmc_id(dmc_id)
>>  			kfree(dmc->dmc_info[dmc_id].payload);
>> +
>> +		kfree(dmc);
>> +		dev_priv->display.dmc.dmc = NULL;
>>  	}
>>  }
>>  
>> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
>> index b74635497aa7..fd607afff2ef 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dmc.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dmc.h
>> @@ -6,44 +6,12 @@
>>  #ifndef __INTEL_DMC_H__
>>  #define __INTEL_DMC_H__
>>  
>> -#include "i915_reg_defs.h"
>> -#include "intel_wakeref.h"
>> -#include <linux/workqueue.h>
>> +#include <linux/types.h>
>>  
>>  struct drm_i915_error_state_buf;
>>  struct drm_i915_private;
>> -
>>  enum pipe;
>>  
>> -enum intel_dmc_id {
>> -	DMC_FW_MAIN = 0,
>> -	DMC_FW_PIPEA,
>> -	DMC_FW_PIPEB,
>> -	DMC_FW_PIPEC,
>> -	DMC_FW_PIPED,
>> -	DMC_FW_MAX
>> -};
>> -
>> -struct intel_dmc {
>> -	struct drm_i915_private *i915;
>> -	struct work_struct work;
>> -	const char *fw_path;
>> -	u32 max_fw_size; /* bytes */
>> -	u32 version;
>> -	struct dmc_fw_info {
>> -		u32 mmio_count;
>> -		i915_reg_t mmioaddr[20];
>> -		u32 mmiodata[20];
>> -		u32 dmc_offset;
>> -		u32 start_mmioaddr;
>> -		u32 dmc_fw_size; /*dwords */
>> -		u32 *payload;
>> -		bool present;
>> -	} dmc_info[DMC_FW_MAX];
>> -
>> -	intel_wakeref_t wakeref;
>> -};
>> -
>>  void intel_dmc_init(struct drm_i915_private *i915);
>>  void intel_dmc_load_program(struct drm_i915_private *i915);
>>  void intel_dmc_disable_program(struct drm_i915_private *i915);
>> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
>> index 5359b9663a07..42bfd56fcbe4 100644
>> --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
>> +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
>> @@ -22,6 +22,7 @@
>>  #include "intel_display.h"
>>  #include "intel_display_power.h"
>>  #include "intel_display_types.h"
>> +#include "intel_dmc.h"
>>  #include "intel_modeset_setup.h"
>>  #include "intel_pch_display.h"
>>  #include "intel_pm.h"
>> -- 
>> 2.34.1
>> 

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v2 3/3] drm/i915/dmc: allocate dmc structure dynamically

[Imre Deak]

On Fri, Feb 17, 2023 at 12:04:14PM +0200, Jani Nikula wrote:
> On Thu, 16 Feb 2023, Imre Deak <imre.deak@intel.com> wrote:
> > On Thu, Feb 16, 2023 at 06:17:39PM +0200, Jani Nikula wrote:
> >> sizeof(struct intel_dmc) > 1024 bytes, allocated on all platforms as
> >> part of struct drm_i915_private, whether they have DMC or not.
> >> 
> >> Allocate struct intel_dmc dynamically, and hide all the dmc details
> >> behind an opaque pointer in intel_dmc.c.
> >> 
> >> Care must be taken to take into account all cases: DMC not supported on
> >> the platform, DMC supported but not initialized, and DMC initialized but
> >> not loaded. For the second case, we need to move the wakeref out of
> >> struct intel_dmc.
> >> 
> >> Cc: Imre Deak <imre.deak@intel.com>
> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >> ---
> >>  .../gpu/drm/i915/display/intel_display_core.h |  8 ++-
> >>  drivers/gpu/drm/i915/display/intel_dmc.c      | 50 +++++++++++++++++--
> >>  drivers/gpu/drm/i915/display/intel_dmc.h      | 34 +------------
> >>  .../drm/i915/display/intel_modeset_setup.c    |  1 +
> >>  4 files changed, 53 insertions(+), 40 deletions(-)
> >> 
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> >> index b870f7f47f2b..ff51149c5fcb 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> >> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> >> @@ -19,7 +19,6 @@
> >>  #include "intel_cdclk.h"
> >>  #include "intel_display_limits.h"
> >>  #include "intel_display_power.h"
> >> -#include "intel_dmc.h"
> >>  #include "intel_dpll_mgr.h"
> >>  #include "intel_fbc.h"
> >>  #include "intel_global_state.h"
> >> @@ -40,6 +39,7 @@ struct intel_cdclk_vals;
> >>  struct intel_color_funcs;
> >>  struct intel_crtc;
> >>  struct intel_crtc_state;
> >> +struct intel_dmc;
> >>  struct intel_dpll_funcs;
> >>  struct intel_dpll_mgr;
> >>  struct intel_fbdev;
> >> @@ -340,6 +340,11 @@ struct intel_display {
> >>  		spinlock_t phy_lock;
> >>  	} dkl;
> >>  
> >> +	struct {
> >> +		struct intel_dmc *dmc;
> >> +		intel_wakeref_t wakeref;
> >> +	} dmc;
> >> +
> >>  	struct {
> >>  		/* VLV/CHV/BXT/GLK DSI MMIO register base address */
> >>  		u32 mmio_base;
> >> @@ -467,7 +472,6 @@ struct intel_display {
> >>  
> >>  	/* Grouping using named structs. Keep sorted. */
> >>  	struct intel_audio audio;
> >> -	struct intel_dmc dmc;
> >>  	struct intel_dpll dpll;
> >>  	struct intel_fbc *fbc[I915_MAX_FBCS];
> >>  	struct intel_frontbuffer_tracking fb_tracking;
> >> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> >> index 1d156ac2eb4c..8428d08e0c3d 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> >> @@ -38,9 +38,37 @@
> >>   * low-power state and comes back to normal.
> >>   */
> >>  
> >> +enum intel_dmc_id {
> >> +	DMC_FW_MAIN = 0,
> >> +	DMC_FW_PIPEA,
> >> +	DMC_FW_PIPEB,
> >> +	DMC_FW_PIPEC,
> >> +	DMC_FW_PIPED,
> >> +	DMC_FW_MAX
> >> +};
> >> +
> >> +struct intel_dmc {
> >> +	struct drm_i915_private *i915;
> >> +	struct work_struct work;
> >> +	const char *fw_path;
> >> +	u32 max_fw_size; /* bytes */
> >> +	u32 version;
> >> +	struct dmc_fw_info {
> >> +		u32 mmio_count;
> >> +		i915_reg_t mmioaddr[20];
> >> +		u32 mmiodata[20];
> >> +		u32 dmc_offset;
> >> +		u32 start_mmioaddr;
> >> +		u32 dmc_fw_size; /*dwords */
> >> +		u32 *payload;
> >> +		bool present;
> >> +	} dmc_info[DMC_FW_MAX];
> >> +};
> >> +
> >> +/* Note: This may be NULL. */
> >>  static struct intel_dmc *i915_to_dmc(struct drm_i915_private *i915)
> >>  {
> >> -	return &i915->display.dmc;
> >> +	return i915->display.dmc.dmc;
> >>  }
> >>  
> >>  #define DMC_VERSION(major, minor)	((major) << 16 | (minor))
> >> @@ -937,7 +965,10 @@ void intel_dmc_init(struct drm_i915_private *dev_priv)
> >>  	if (!HAS_DMC(dev_priv))
> >>  		return;
> >>  
> >> -	dmc = i915_to_dmc(dev_priv);
> >> +	dmc = kzalloc(sizeof(*dmc), GFP_KERNEL);
> >> +	if (!dmc)
> >> +		return;
> >
> > Couldn't driver loading fail in this case instead (simplifying the
> > dmc==NULL checks elsewhere)?
> 
> We could fail driver load, yes, but it still wouldn't simplify the NULL
> checks because you could use i915.dmc_firmware_path="" to disable the
> firmware, and what's the point in keeping the 1k memory allocated in
> that case?

Right, only noticed the same later. But that's only a debug feature so
could be acceptable trade-off for simplicity imo; also the supported but
non-initialized state wouldn't be needed then either.

It's not a big deal and the check is local to intel_dmc.c, so either way
on the patchset:
Reviewed-by: Imre Deak <imre.deak@intel.com>

(Querying the DMC FW presence in IGT needs to be fixed before merging.)

> BR,
> Jani.
> 
> 
> >
> >> +
> >>  	dmc->i915 = dev_priv;
> >>  
> >>  	INIT_WORK(&dmc->work, dmc_load_work_fn);
> >> @@ -991,10 +1022,9 @@ void intel_dmc_init(struct drm_i915_private *dev_priv)
> >>  
> >>  	if (dev_priv->params.dmc_firmware_path) {
> >>  		if (strlen(dev_priv->params.dmc_firmware_path) == 0) {
> >> -			dmc->fw_path = NULL;
> >>  			drm_info(&dev_priv->drm,
> >>  				 "Disabling DMC firmware and runtime PM\n");
> >> -			return;
> >> +			goto out;
> >>  		}
> >>  
> >>  		dmc->fw_path = dev_priv->params.dmc_firmware_path;
> >> @@ -1003,11 +1033,18 @@ void intel_dmc_init(struct drm_i915_private *dev_priv)
> >>  	if (!dmc->fw_path) {
> >>  		drm_dbg_kms(&dev_priv->drm,
> >>  			    "No known DMC firmware for platform, disabling runtime PM\n");
> >> -		return;
> >> +		goto out;
> >>  	}
> >>  
> >> +	dev_priv->display.dmc.dmc = dmc;
> >> +
> >>  	drm_dbg_kms(&dev_priv->drm, "Loading %s\n", dmc->fw_path);
> >>  	schedule_work(&dmc->work);
> >> +
> >> +	return;
> >> +
> >> +out:
> >> +	kfree(dmc);
> >>  }
> >>  
> >>  /**
> >> @@ -1074,6 +1111,9 @@ void intel_dmc_fini(struct drm_i915_private *dev_priv)
> >>  	if (dmc) {
> >>  		for_each_dmc_id(dmc_id)
> >>  			kfree(dmc->dmc_info[dmc_id].payload);
> >> +
> >> +		kfree(dmc);
> >> +		dev_priv->display.dmc.dmc = NULL;
> >>  	}
> >>  }
> >>  
> >> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
> >> index b74635497aa7..fd607afff2ef 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_dmc.h
> >> +++ b/drivers/gpu/drm/i915/display/intel_dmc.h
> >> @@ -6,44 +6,12 @@
> >>  #ifndef __INTEL_DMC_H__
> >>  #define __INTEL_DMC_H__
> >>  
> >> -#include "i915_reg_defs.h"
> >> -#include "intel_wakeref.h"
> >> -#include <linux/workqueue.h>
> >> +#include <linux/types.h>
> >>  
> >>  struct drm_i915_error_state_buf;
> >>  struct drm_i915_private;
> >> -
> >>  enum pipe;
> >>  
> >> -enum intel_dmc_id {
> >> -	DMC_FW_MAIN = 0,
> >> -	DMC_FW_PIPEA,
> >> -	DMC_FW_PIPEB,
> >> -	DMC_FW_PIPEC,
> >> -	DMC_FW_PIPED,
> >> -	DMC_FW_MAX
> >> -};
> >> -
> >> -struct intel_dmc {
> >> -	struct drm_i915_private *i915;
> >> -	struct work_struct work;
> >> -	const char *fw_path;
> >> -	u32 max_fw_size; /* bytes */
> >> -	u32 version;
> >> -	struct dmc_fw_info {
> >> -		u32 mmio_count;
> >> -		i915_reg_t mmioaddr[20];
> >> -		u32 mmiodata[20];
> >> -		u32 dmc_offset;
> >> -		u32 start_mmioaddr;
> >> -		u32 dmc_fw_size; /*dwords */
> >> -		u32 *payload;
> >> -		bool present;
> >> -	} dmc_info[DMC_FW_MAX];
> >> -
> >> -	intel_wakeref_t wakeref;
> >> -};
> >> -
> >>  void intel_dmc_init(struct drm_i915_private *i915);
> >>  void intel_dmc_load_program(struct drm_i915_private *i915);
> >>  void intel_dmc_disable_program(struct drm_i915_private *i915);
> >> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> >> index 5359b9663a07..42bfd56fcbe4 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> >> @@ -22,6 +22,7 @@
> >>  #include "intel_display.h"
> >>  #include "intel_display_power.h"
> >>  #include "intel_display_types.h"
> >> +#include "intel_dmc.h"
> >>  #include "intel_modeset_setup.h"
> >>  #include "intel_pch_display.h"
> >>  #include "intel_pm.h"
> >> -- 
> >> 2.34.1
> >> 
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v2 3/3] drm/i915/dmc: allocate dmc structure dynamically

[Jani Nikula]

On Fri, 17 Feb 2023, Imre Deak <imre.deak@intel.com> wrote:
> On Fri, Feb 17, 2023 at 12:04:14PM +0200, Jani Nikula wrote:
>> On Thu, 16 Feb 2023, Imre Deak <imre.deak@intel.com> wrote:
>> > On Thu, Feb 16, 2023 at 06:17:39PM +0200, Jani Nikula wrote:
>> >> sizeof(struct intel_dmc) > 1024 bytes, allocated on all platforms as
>> >> part of struct drm_i915_private, whether they have DMC or not.
>> >> 
>> >> Allocate struct intel_dmc dynamically, and hide all the dmc details
>> >> behind an opaque pointer in intel_dmc.c.
>> >> 
>> >> Care must be taken to take into account all cases: DMC not supported on
>> >> the platform, DMC supported but not initialized, and DMC initialized but
>> >> not loaded. For the second case, we need to move the wakeref out of
>> >> struct intel_dmc.
>> >> 
>> >> Cc: Imre Deak <imre.deak@intel.com>
>> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> >> ---
>> >>  .../gpu/drm/i915/display/intel_display_core.h |  8 ++-
>> >>  drivers/gpu/drm/i915/display/intel_dmc.c      | 50 +++++++++++++++++--
>> >>  drivers/gpu/drm/i915/display/intel_dmc.h      | 34 +------------
>> >>  .../drm/i915/display/intel_modeset_setup.c    |  1 +
>> >>  4 files changed, 53 insertions(+), 40 deletions(-)
>> >> 
>> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
>> >> index b870f7f47f2b..ff51149c5fcb 100644
>> >> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
>> >> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>> >> @@ -19,7 +19,6 @@
>> >>  #include "intel_cdclk.h"
>> >>  #include "intel_display_limits.h"
>> >>  #include "intel_display_power.h"
>> >> -#include "intel_dmc.h"
>> >>  #include "intel_dpll_mgr.h"
>> >>  #include "intel_fbc.h"
>> >>  #include "intel_global_state.h"
>> >> @@ -40,6 +39,7 @@ struct intel_cdclk_vals;
>> >>  struct intel_color_funcs;
>> >>  struct intel_crtc;
>> >>  struct intel_crtc_state;
>> >> +struct intel_dmc;
>> >>  struct intel_dpll_funcs;
>> >>  struct intel_dpll_mgr;
>> >>  struct intel_fbdev;
>> >> @@ -340,6 +340,11 @@ struct intel_display {
>> >>  		spinlock_t phy_lock;
>> >>  	} dkl;
>> >>  
>> >> +	struct {
>> >> +		struct intel_dmc *dmc;
>> >> +		intel_wakeref_t wakeref;
>> >> +	} dmc;
>> >> +
>> >>  	struct {
>> >>  		/* VLV/CHV/BXT/GLK DSI MMIO register base address */
>> >>  		u32 mmio_base;
>> >> @@ -467,7 +472,6 @@ struct intel_display {
>> >>  
>> >>  	/* Grouping using named structs. Keep sorted. */
>> >>  	struct intel_audio audio;
>> >> -	struct intel_dmc dmc;
>> >>  	struct intel_dpll dpll;
>> >>  	struct intel_fbc *fbc[I915_MAX_FBCS];
>> >>  	struct intel_frontbuffer_tracking fb_tracking;
>> >> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
>> >> index 1d156ac2eb4c..8428d08e0c3d 100644
>> >> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
>> >> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
>> >> @@ -38,9 +38,37 @@
>> >>   * low-power state and comes back to normal.
>> >>   */
>> >>  
>> >> +enum intel_dmc_id {
>> >> +	DMC_FW_MAIN = 0,
>> >> +	DMC_FW_PIPEA,
>> >> +	DMC_FW_PIPEB,
>> >> +	DMC_FW_PIPEC,
>> >> +	DMC_FW_PIPED,
>> >> +	DMC_FW_MAX
>> >> +};
>> >> +
>> >> +struct intel_dmc {
>> >> +	struct drm_i915_private *i915;
>> >> +	struct work_struct work;
>> >> +	const char *fw_path;
>> >> +	u32 max_fw_size; /* bytes */
>> >> +	u32 version;
>> >> +	struct dmc_fw_info {
>> >> +		u32 mmio_count;
>> >> +		i915_reg_t mmioaddr[20];
>> >> +		u32 mmiodata[20];
>> >> +		u32 dmc_offset;
>> >> +		u32 start_mmioaddr;
>> >> +		u32 dmc_fw_size; /*dwords */
>> >> +		u32 *payload;
>> >> +		bool present;
>> >> +	} dmc_info[DMC_FW_MAX];
>> >> +};
>> >> +
>> >> +/* Note: This may be NULL. */
>> >>  static struct intel_dmc *i915_to_dmc(struct drm_i915_private *i915)
>> >>  {
>> >> -	return &i915->display.dmc;
>> >> +	return i915->display.dmc.dmc;
>> >>  }
>> >>  
>> >>  #define DMC_VERSION(major, minor)	((major) << 16 | (minor))
>> >> @@ -937,7 +965,10 @@ void intel_dmc_init(struct drm_i915_private *dev_priv)
>> >>  	if (!HAS_DMC(dev_priv))
>> >>  		return;
>> >>  
>> >> -	dmc = i915_to_dmc(dev_priv);
>> >> +	dmc = kzalloc(sizeof(*dmc), GFP_KERNEL);
>> >> +	if (!dmc)
>> >> +		return;
>> >
>> > Couldn't driver loading fail in this case instead (simplifying the
>> > dmc==NULL checks elsewhere)?
>> 
>> We could fail driver load, yes, but it still wouldn't simplify the NULL
>> checks because you could use i915.dmc_firmware_path="" to disable the
>> firmware, and what's the point in keeping the 1k memory allocated in
>> that case?
>
> Right, only noticed the same later. But that's only a debug feature so
> could be acceptable trade-off for simplicity imo; also the supported but
> non-initialized state wouldn't be needed then either.
>
> It's not a big deal and the check is local to intel_dmc.c, so either way
> on the patchset:
> Reviewed-by: Imre Deak <imre.deak@intel.com>
>
> (Querying the DMC FW presence in IGT needs to be fixed before merging.)

The IGT part seemed harder to fix than just preserving the debugfs
output for dmc == NULL. v3 at:

https://patchwork.freedesktop.org/series/114431/

>
>> BR,
>> Jani.
>> 
>> 
>> >
>> >> +
>> >>  	dmc->i915 = dev_priv;
>> >>  
>> >>  	INIT_WORK(&dmc->work, dmc_load_work_fn);
>> >> @@ -991,10 +1022,9 @@ void intel_dmc_init(struct drm_i915_private *dev_priv)
>> >>  
>> >>  	if (dev_priv->params.dmc_firmware_path) {
>> >>  		if (strlen(dev_priv->params.dmc_firmware_path) == 0) {
>> >> -			dmc->fw_path = NULL;
>> >>  			drm_info(&dev_priv->drm,
>> >>  				 "Disabling DMC firmware and runtime PM\n");
>> >> -			return;
>> >> +			goto out;
>> >>  		}
>> >>  
>> >>  		dmc->fw_path = dev_priv->params.dmc_firmware_path;
>> >> @@ -1003,11 +1033,18 @@ void intel_dmc_init(struct drm_i915_private *dev_priv)
>> >>  	if (!dmc->fw_path) {
>> >>  		drm_dbg_kms(&dev_priv->drm,
>> >>  			    "No known DMC firmware for platform, disabling runtime PM\n");
>> >> -		return;
>> >> +		goto out;
>> >>  	}
>> >>  
>> >> +	dev_priv->display.dmc.dmc = dmc;
>> >> +
>> >>  	drm_dbg_kms(&dev_priv->drm, "Loading %s\n", dmc->fw_path);
>> >>  	schedule_work(&dmc->work);
>> >> +
>> >> +	return;
>> >> +
>> >> +out:
>> >> +	kfree(dmc);
>> >>  }
>> >>  
>> >>  /**
>> >> @@ -1074,6 +1111,9 @@ void intel_dmc_fini(struct drm_i915_private *dev_priv)
>> >>  	if (dmc) {
>> >>  		for_each_dmc_id(dmc_id)
>> >>  			kfree(dmc->dmc_info[dmc_id].payload);
>> >> +
>> >> +		kfree(dmc);
>> >> +		dev_priv->display.dmc.dmc = NULL;
>> >>  	}
>> >>  }
>> >>  
>> >> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
>> >> index b74635497aa7..fd607afff2ef 100644
>> >> --- a/drivers/gpu/drm/i915/display/intel_dmc.h
>> >> +++ b/drivers/gpu/drm/i915/display/intel_dmc.h
>> >> @@ -6,44 +6,12 @@
>> >>  #ifndef __INTEL_DMC_H__
>> >>  #define __INTEL_DMC_H__
>> >>  
>> >> -#include "i915_reg_defs.h"
>> >> -#include "intel_wakeref.h"
>> >> -#include <linux/workqueue.h>
>> >> +#include <linux/types.h>
>> >>  
>> >>  struct drm_i915_error_state_buf;
>> >>  struct drm_i915_private;
>> >> -
>> >>  enum pipe;
>> >>  
>> >> -enum intel_dmc_id {
>> >> -	DMC_FW_MAIN = 0,
>> >> -	DMC_FW_PIPEA,
>> >> -	DMC_FW_PIPEB,
>> >> -	DMC_FW_PIPEC,
>> >> -	DMC_FW_PIPED,
>> >> -	DMC_FW_MAX
>> >> -};
>> >> -
>> >> -struct intel_dmc {
>> >> -	struct drm_i915_private *i915;
>> >> -	struct work_struct work;
>> >> -	const char *fw_path;
>> >> -	u32 max_fw_size; /* bytes */
>> >> -	u32 version;
>> >> -	struct dmc_fw_info {
>> >> -		u32 mmio_count;
>> >> -		i915_reg_t mmioaddr[20];
>> >> -		u32 mmiodata[20];
>> >> -		u32 dmc_offset;
>> >> -		u32 start_mmioaddr;
>> >> -		u32 dmc_fw_size; /*dwords */
>> >> -		u32 *payload;
>> >> -		bool present;
>> >> -	} dmc_info[DMC_FW_MAX];
>> >> -
>> >> -	intel_wakeref_t wakeref;
>> >> -};
>> >> -
>> >>  void intel_dmc_init(struct drm_i915_private *i915);
>> >>  void intel_dmc_load_program(struct drm_i915_private *i915);
>> >>  void intel_dmc_disable_program(struct drm_i915_private *i915);
>> >> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
>> >> index 5359b9663a07..42bfd56fcbe4 100644
>> >> --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
>> >> +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
>> >> @@ -22,6 +22,7 @@
>> >>  #include "intel_display.h"
>> >>  #include "intel_display_power.h"
>> >>  #include "intel_display_types.h"
>> >> +#include "intel_dmc.h"
>> >>  #include "intel_modeset_setup.h"
>> >>  #include "intel_pch_display.h"
>> >>  #include "intel_pm.h"
>> >> -- 
>> >> 2.34.1
>> >> 
>> 
>> -- 
>> Jani Nikula, Intel Open Source Graphics Center

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v2 1/3] drm/i915/power: move dc state members to struct i915_power_domains

[Imre Deak]

On Thu, Feb 16, 2023 at 06:17:37PM +0200, Jani Nikula wrote:
> There's only one reference to the struct intel_dmc members dc_state,
> target_dc_state, and allowed_dc_mask within intel_dmc.c, begging the
> question why they are under struct intel_dmc to begin with.
> 
> Moreover, the only references to i915->display.dmc outside of
> intel_dmc.c are to these members.
> 
> They don't belong. Move them from struct intel_dmc to struct
> i915_power_domains, which seems like a more suitable place.
> 
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  .../drm/i915/display/intel_display_power.c    | 25 ++++++++-------
>  .../drm/i915/display/intel_display_power.h    |  4 +++
>  .../i915/display/intel_display_power_well.c   | 31 +++++++++++--------
>  drivers/gpu/drm/i915/display/intel_dmc.c      |  3 +-
>  drivers/gpu/drm/i915/display/intel_dmc.h      |  3 --
>  drivers/gpu/drm/i915/display/intel_psr.c      |  3 +-
>  6 files changed, 39 insertions(+), 30 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 7222502a760c..4ed7e50e1c21 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -264,9 +264,10 @@ bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
>  }
>  
>  static u32
> -sanitize_target_dc_state(struct drm_i915_private *dev_priv,
> +sanitize_target_dc_state(struct drm_i915_private *i915,
>  			 u32 target_dc_state)
>  {
> +	struct i915_power_domains *power_domains = &i915->display.power.domains;
>  	static const u32 states[] = {
>  		DC_STATE_EN_UPTO_DC6,
>  		DC_STATE_EN_UPTO_DC5,
> @@ -279,7 +280,7 @@ sanitize_target_dc_state(struct drm_i915_private *dev_priv,
>  		if (target_dc_state != states[i])
>  			continue;
>  
> -		if (dev_priv->display.dmc.allowed_dc_mask & target_dc_state)
> +		if (power_domains->allowed_dc_mask & target_dc_state)
>  			break;
>  
>  		target_dc_state = states[i + 1];
> @@ -312,7 +313,7 @@ void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
>  
>  	state = sanitize_target_dc_state(dev_priv, state);
>  
> -	if (state == dev_priv->display.dmc.target_dc_state)
> +	if (state == power_domains->target_dc_state)
>  		goto unlock;
>  
>  	dc_off_enabled = intel_power_well_is_enabled(dev_priv, power_well);
> @@ -323,7 +324,7 @@ void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
>  	if (!dc_off_enabled)
>  		intel_power_well_enable(dev_priv, power_well);
>  
> -	dev_priv->display.dmc.target_dc_state = state;
> +	power_domains->target_dc_state = state;
>  
>  	if (!dc_off_enabled)
>  		intel_power_well_disable(dev_priv, power_well);
> @@ -992,10 +993,10 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
>  	dev_priv->params.disable_power_well =
>  		sanitize_disable_power_well_option(dev_priv,
>  						   dev_priv->params.disable_power_well);
> -	dev_priv->display.dmc.allowed_dc_mask =
> +	power_domains->allowed_dc_mask =
>  		get_allowed_dc_mask(dev_priv, dev_priv->params.enable_dc);
>  
> -	dev_priv->display.dmc.target_dc_state =
> +	power_domains->target_dc_state =
>  		sanitize_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
>  
>  	mutex_init(&power_domains->lock);
> @@ -2053,7 +2054,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915,
>  	 * resources as required and also enable deeper system power states
>  	 * that would be blocked if the firmware was inactive.
>  	 */
> -	if (!(i915->display.dmc.allowed_dc_mask & DC_STATE_EN_DC9) &&
> +	if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC9) &&
>  	    suspend_mode == I915_DRM_SUSPEND_IDLE &&
>  	    intel_dmc_has_payload(i915)) {
>  		intel_display_power_flush_work(i915);
> @@ -2242,22 +2243,22 @@ void intel_display_power_suspend(struct drm_i915_private *i915)
>  
>  void intel_display_power_resume(struct drm_i915_private *i915)
>  {
> +	struct i915_power_domains *power_domains = &i915->display.power.domains;
> +
>  	if (DISPLAY_VER(i915) >= 11) {
>  		bxt_disable_dc9(i915);
>  		icl_display_core_init(i915, true);
>  		if (intel_dmc_has_payload(i915)) {
> -			if (i915->display.dmc.allowed_dc_mask &
> -			    DC_STATE_EN_UPTO_DC6)
> +			if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
>  				skl_enable_dc6(i915);
> -			else if (i915->display.dmc.allowed_dc_mask &
> -				 DC_STATE_EN_UPTO_DC5)
> +			else if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
>  				gen9_enable_dc5(i915);
>  		}
>  	} else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
>  		bxt_disable_dc9(i915);
>  		bxt_display_core_init(i915, true);
>  		if (intel_dmc_has_payload(i915) &&
> -		    (i915->display.dmc.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
> +		    (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
>  			gen9_enable_dc5(i915);
>  	} else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
>  		hsw_disable_pc8(i915);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> index 2154d900b1aa..8e96be8e6330 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -137,6 +137,10 @@ struct i915_power_domains {
>  	bool display_core_suspended;
>  	int power_well_count;
>  
> +	u32 dc_state;
> +	u32 target_dc_state;
> +	u32 allowed_dc_mask;
> +
>  	intel_wakeref_t init_wakeref;
>  	intel_wakeref_t disable_wakeref;
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 56a20bf5825b..57df9fc985bf 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -713,19 +713,20 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
>  	return mask;
>  }
>  
> -void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv)
> +void gen9_sanitize_dc_state(struct drm_i915_private *i915)
>  {
> +	struct i915_power_domains *power_domains = &i915->display.power.domains;
>  	u32 val;
>  
> -	if (!HAS_DISPLAY(dev_priv))
> +	if (!HAS_DISPLAY(i915))
>  		return;
>  
> -	val = intel_de_read(dev_priv, DC_STATE_EN) & gen9_dc_mask(dev_priv);
> +	val = intel_de_read(i915, DC_STATE_EN) & gen9_dc_mask(i915);
>  
> -	drm_dbg_kms(&dev_priv->drm,
> +	drm_dbg_kms(&i915->drm,
>  		    "Resetting DC state tracking from %02x to %02x\n",
> -		    dev_priv->display.dmc.dc_state, val);
> -	dev_priv->display.dmc.dc_state = val;
> +		    power_domains->dc_state, val);
> +	power_domains->dc_state = val;
>  }
>  
>  /**
> @@ -753,6 +754,7 @@ void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv)
>   */
>  void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
>  {
> +	struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
>  	u32 val;
>  	u32 mask;
>  
> @@ -760,8 +762,8 @@ void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
>  		return;
>  
>  	if (drm_WARN_ON_ONCE(&dev_priv->drm,
> -			     state & ~dev_priv->display.dmc.allowed_dc_mask))
> -		state &= dev_priv->display.dmc.allowed_dc_mask;
> +			     state & ~power_domains->allowed_dc_mask))
> +		state &= power_domains->allowed_dc_mask;
>  
>  	val = intel_de_read(dev_priv, DC_STATE_EN);
>  	mask = gen9_dc_mask(dev_priv);
> @@ -769,16 +771,16 @@ void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
>  		    val & mask, state);
>  
>  	/* Check if DMC is ignoring our DC state requests */
> -	if ((val & mask) != dev_priv->display.dmc.dc_state)
> +	if ((val & mask) != power_domains->dc_state)
>  		drm_err(&dev_priv->drm, "DC state mismatch (0x%x -> 0x%x)\n",
> -			dev_priv->display.dmc.dc_state, val & mask);
> +			power_domains->dc_state, val & mask);
>  
>  	val &= ~mask;
>  	val |= state;
>  
>  	gen9_write_dc_state(dev_priv, val);
>  
> -	dev_priv->display.dmc.dc_state = val & mask;
> +	power_domains->dc_state = val & mask;
>  }
>  
>  static void tgl_enable_dc3co(struct drm_i915_private *dev_priv)
> @@ -970,9 +972,10 @@ static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
>  
>  void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
>  {
> +	struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
>  	struct intel_cdclk_config cdclk_config = {};
>  
> -	if (dev_priv->display.dmc.target_dc_state == DC_STATE_EN_DC3CO) {
> +	if (power_domains->target_dc_state == DC_STATE_EN_DC3CO) {
>  		tgl_disable_dc3co(dev_priv);
>  		return;
>  	}
> @@ -1011,10 +1014,12 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
>  static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
>  					   struct i915_power_well *power_well)
>  {
> +	struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
> +
>  	if (!intel_dmc_has_payload(dev_priv))
>  		return;
>  
> -	switch (dev_priv->display.dmc.target_dc_state) {
> +	switch (power_domains->target_dc_state) {
>  	case DC_STATE_EN_DC3CO:
>  		tgl_enable_dc3co(dev_priv);
>  		break;
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index f70ada2357dc..ab4fdedd4c5f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -449,6 +449,7 @@ void intel_dmc_disable_pipe(struct drm_i915_private *i915, enum pipe pipe)
>   */
>  void intel_dmc_load_program(struct drm_i915_private *dev_priv)
>  {
> +	struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
>  	struct intel_dmc *dmc = &dev_priv->display.dmc;
>  	enum intel_dmc_id dmc_id;
>  	u32 i;
> @@ -481,7 +482,7 @@ void intel_dmc_load_program(struct drm_i915_private *dev_priv)
>  		}
>  	}
>  
> -	dev_priv->display.dmc.dc_state = 0;
> +	power_domains->dc_state = 0;
>  
>  	gen9_set_dc_state_debugmask(dev_priv);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
> index c9808bbe7162..90910cecc2f6 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.h
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.h
> @@ -40,9 +40,6 @@ struct intel_dmc {
>  		bool present;
>  	} dmc_info[DMC_FW_MAX];
>  
> -	u32 dc_state;
> -	u32 target_dc_state;
> -	u32 allowed_dc_mask;
>  	intel_wakeref_t wakeref;
>  };
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 2954759e9d12..cf13580af34a 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -702,6 +702,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
>  {
>  	const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay;
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +	struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
>  	u32 exit_scanlines;
>  
>  	/*
> @@ -718,7 +719,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
>  	if (crtc_state->enable_psr2_sel_fetch)
>  		return;
>  
> -	if (!(dev_priv->display.dmc.allowed_dc_mask & DC_STATE_EN_DC3CO))
> +	if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC3CO))
>  		return;
>  
>  	if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state))
> -- 
> 2.34.1
> 

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/3] drm/i915/power: move dc state members to struct i915_power_domains

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/3] drm/i915/power: move dc state members to struct i915_power_domains
URL   : https://patchwork.freedesktop.org/series/114112/
State : warning

== Summary ==

Error: dim checkpatch failed
8986ed2489ba drm/i915/power: move dc state members to struct i915_power_domains
e0e2234f431c drm/i915/dmc: add i915_to_dmc() and dmc->i915 and use them
-:58: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#58: FILE: drivers/gpu/drm/i915/display/intel_dmc.c:529:
+		      !intel_de_read(i915, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),

total: 0 errors, 1 warnings, 0 checks, 254 lines checked
f09ec2f4fd56 drm/i915/dmc: allocate dmc structure dynamically

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2,1/3] drm/i915/power: move dc state members to struct i915_power_domains

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 17989 bytes --]

== Series Details ==

Series: series starting with [v2,1/3] drm/i915/power: move dc state members to struct i915_power_domains
URL   : https://patchwork.freedesktop.org/series/114112/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12751 -> Patchwork_114112v1
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_114112v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_114112v1, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/index.html

Participating hosts (38 -> 38)
------------------------------

  Additional (2): bat-atsm-1 fi-kbl-8809g 
  Missing    (2): fi-kbl-soraka fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_114112v1:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_exec_suspend@basic-s3@lmem0:
    - bat-dg2-11:         [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12751/bat-dg2-11/igt@gem_exec_suspend@basic-s3@lmem0.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/bat-dg2-11/igt@gem_exec_suspend@basic-s3@lmem0.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - bat-adlm-1:         [PASS][3] -> [SKIP][4] +2 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12751/bat-adlm-1/igt@i915_pm_rpm@basic-pci-d3-state.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/bat-adlm-1/igt@i915_pm_rpm@basic-pci-d3-state.html
    - bat-jsl-1:          [PASS][5] -> [SKIP][6] +2 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12751/bat-jsl-1/igt@i915_pm_rpm@basic-pci-d3-state.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/bat-jsl-1/igt@i915_pm_rpm@basic-pci-d3-state.html
    - fi-tgl-1115g4:      [PASS][7] -> [SKIP][8] +2 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12751/fi-tgl-1115g4/igt@i915_pm_rpm@basic-pci-d3-state.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/fi-tgl-1115g4/igt@i915_pm_rpm@basic-pci-d3-state.html
    - bat-rpls-1:         [PASS][9] -> [SKIP][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12751/bat-rpls-1/igt@i915_pm_rpm@basic-pci-d3-state.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/bat-rpls-1/igt@i915_pm_rpm@basic-pci-d3-state.html
    - bat-adlp-9:         [PASS][11] -> [SKIP][12] +2 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12751/bat-adlp-9/igt@i915_pm_rpm@basic-pci-d3-state.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/bat-adlp-9/igt@i915_pm_rpm@basic-pci-d3-state.html
    - bat-dg1-6:          [PASS][13] -> [SKIP][14] +2 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12751/bat-dg1-6/igt@i915_pm_rpm@basic-pci-d3-state.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/bat-dg1-6/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@i915_pm_rpm@basic-rte:
    - bat-rplp-1:         [PASS][15] -> [SKIP][16] +2 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12751/bat-rplp-1/igt@i915_pm_rpm@basic-rte.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/bat-rplp-1/igt@i915_pm_rpm@basic-rte.html
    - fi-rkl-11600:       [PASS][17] -> [SKIP][18] +2 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12751/fi-rkl-11600/igt@i915_pm_rpm@basic-rte.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/fi-rkl-11600/igt@i915_pm_rpm@basic-rte.html
    - bat-jsl-3:          [PASS][19] -> [SKIP][20] +2 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12751/bat-jsl-3/igt@i915_pm_rpm@basic-rte.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/bat-jsl-3/igt@i915_pm_rpm@basic-rte.html
    - bat-rpls-2:         [PASS][21] -> [SKIP][22] +2 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12751/bat-rpls-2/igt@i915_pm_rpm@basic-rte.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/bat-rpls-2/igt@i915_pm_rpm@basic-rte.html
    - bat-rpls-1:         [PASS][23] -> [ABORT][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12751/bat-rpls-1/igt@i915_pm_rpm@basic-rte.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/bat-rpls-1/igt@i915_pm_rpm@basic-rte.html

  * igt@i915_pm_rpm@module-reload:
    - bat-adlp-6:         [PASS][25] -> [SKIP][26] +2 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12751/bat-adlp-6/igt@i915_pm_rpm@module-reload.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/bat-adlp-6/igt@i915_pm_rpm@module-reload.html
    - bat-dg1-5:          [PASS][27] -> [SKIP][28] +2 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12751/bat-dg1-5/igt@i915_pm_rpm@module-reload.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/bat-dg1-5/igt@i915_pm_rpm@module-reload.html
    - bat-dg1-7:          [PASS][29] -> [SKIP][30] +2 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12751/bat-dg1-7/igt@i915_pm_rpm@module-reload.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/bat-dg1-7/igt@i915_pm_rpm@module-reload.html
    - bat-adln-1:         [PASS][31] -> [SKIP][32] +2 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12751/bat-adln-1/igt@i915_pm_rpm@module-reload.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/bat-adln-1/igt@i915_pm_rpm@module-reload.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_pm_rpm@module-reload:
    - {bat-adls-5}:       [PASS][33] -> [SKIP][34] +2 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12751/bat-adls-5/igt@i915_pm_rpm@module-reload.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/bat-adls-5/igt@i915_pm_rpm@module-reload.html

  
Known issues
------------

  Here are the changes found in Patchwork_114112v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@fbdev@eof:
    - bat-atsm-1:         NOTRUN -> [SKIP][35] ([i915#2582]) +4 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/bat-atsm-1/igt@fbdev@eof.html

  * igt@gem_mmap@basic:
    - bat-atsm-1:         NOTRUN -> [SKIP][36] ([i915#4083])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/bat-atsm-1/igt@gem_mmap@basic.html

  * igt@gem_tiled_fence_blits@basic:
    - bat-atsm-1:         NOTRUN -> [SKIP][37] ([i915#4077]) +2 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/bat-atsm-1/igt@gem_tiled_fence_blits@basic.html

  * igt@gem_tiled_pread_basic:
    - bat-atsm-1:         NOTRUN -> [SKIP][38] ([i915#4079]) +1 similar issue
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/bat-atsm-1/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - bat-dg2-8:          [PASS][39] -> [SKIP][40] ([i915#7714]) +2 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12751/bat-dg2-8/igt@i915_pm_rpm@basic-pci-d3-state.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/bat-dg2-8/igt@i915_pm_rpm@basic-pci-d3-state.html
    - fi-kbl-guc:         [PASS][41] -> [SKIP][42] ([fdo#109271]) +2 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12751/fi-kbl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/fi-kbl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html
    - fi-skl-6600u:       [PASS][43] -> [SKIP][44] ([fdo#109271]) +2 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12751/fi-skl-6600u/igt@i915_pm_rpm@basic-pci-d3-state.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/fi-skl-6600u/igt@i915_pm_rpm@basic-pci-d3-state.html
    - fi-glk-j4005:       [PASS][45] -> [SKIP][46] ([fdo#109271]) +2 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12751/fi-glk-j4005/igt@i915_pm_rpm@basic-pci-d3-state.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/fi-glk-j4005/igt@i915_pm_rpm@basic-pci-d3-state.html
    - fi-cfl-8700k:       [PASS][47] -> [SKIP][48] ([fdo#109271]) +2 similar issues
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12751/fi-cfl-8700k/igt@i915_pm_rpm@basic-pci-d3-state.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/fi-cfl-8700k/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@i915_pm_rpm@basic-rte:
    - fi-cfl-guc:         [PASS][49] -> [SKIP][50] ([fdo#109271]) +2 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12751/fi-cfl-guc/igt@i915_pm_rpm@basic-rte.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/fi-cfl-guc/igt@i915_pm_rpm@basic-rte.html
    - bat-dg2-9:          [PASS][51] -> [SKIP][52] ([i915#7714]) +2 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12751/bat-dg2-9/igt@i915_pm_rpm@basic-rte.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/bat-dg2-9/igt@i915_pm_rpm@basic-rte.html
    - fi-kbl-x1275:       [PASS][53] -> [SKIP][54] ([fdo#109271]) +2 similar issues
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12751/fi-kbl-x1275/igt@i915_pm_rpm@basic-rte.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/fi-kbl-x1275/igt@i915_pm_rpm@basic-rte.html
    - fi-cfl-8109u:       [PASS][55] -> [SKIP][56] ([fdo#109271]) +2 similar issues
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12751/fi-cfl-8109u/igt@i915_pm_rpm@basic-rte.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/fi-cfl-8109u/igt@i915_pm_rpm@basic-rte.html
    - fi-skl-guc:         [PASS][57] -> [SKIP][58] ([fdo#109271]) +2 similar issues
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12751/fi-skl-guc/igt@i915_pm_rpm@basic-rte.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/fi-skl-guc/igt@i915_pm_rpm@basic-rte.html

  * igt@i915_pm_rpm@module-reload:
    - fi-apl-guc:         [PASS][59] -> [SKIP][60] ([fdo#109271]) +2 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12751/fi-apl-guc/igt@i915_pm_rpm@module-reload.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/fi-apl-guc/igt@i915_pm_rpm@module-reload.html
    - bat-dg2-11:         [PASS][61] -> [SKIP][62] ([i915#7714]) +2 similar issues
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12751/bat-dg2-11/igt@i915_pm_rpm@module-reload.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/bat-dg2-11/igt@i915_pm_rpm@module-reload.html
    - fi-kbl-7567u:       [PASS][63] -> [SKIP][64] ([fdo#109271]) +2 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12751/fi-kbl-7567u/igt@i915_pm_rpm@module-reload.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/fi-kbl-7567u/igt@i915_pm_rpm@module-reload.html

  * igt@i915_pm_rps@basic-api:
    - bat-atsm-1:         NOTRUN -> [SKIP][65] ([i915#6621])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/bat-atsm-1/igt@i915_pm_rps@basic-api.html

  * igt@i915_selftest@live@gt_pm:
    - bat-rpls-2:         [PASS][66] -> [DMESG-FAIL][67] ([i915#4258])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12751/bat-rpls-2/igt@i915_selftest@live@gt_pm.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/bat-rpls-2/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@requests:
    - bat-rplp-1:         [PASS][68] -> [ABORT][69] ([i915#7913])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12751/bat-rplp-1/igt@i915_selftest@live@requests.html
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/bat-rplp-1/igt@i915_selftest@live@requests.html

  * igt@i915_suspend@basic-s3-without-i915:
    - bat-atsm-1:         NOTRUN -> [SKIP][70] ([i915#6645])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/bat-atsm-1/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_addfb_basic@size-max:
    - bat-atsm-1:         NOTRUN -> [SKIP][71] ([i915#6077]) +36 similar issues
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/bat-atsm-1/igt@kms_addfb_basic@size-max.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor:
    - bat-atsm-1:         NOTRUN -> [SKIP][72] ([i915#6078]) +14 similar issues
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/bat-atsm-1/igt@kms_cursor_legacy@basic-flip-after-cursor.html

  * igt@kms_flip@basic-plain-flip:
    - bat-atsm-1:         NOTRUN -> [SKIP][73] ([i915#6166]) +3 similar issues
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/bat-atsm-1/igt@kms_flip@basic-plain-flip.html

  * igt@kms_force_connector_basic@prune-stale-modes:
    - bat-atsm-1:         NOTRUN -> [SKIP][74] ([i915#6093]) +3 similar issues
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/bat-atsm-1/igt@kms_force_connector_basic@prune-stale-modes.html

  * igt@kms_pipe_crc_basic@hang-read-crc:
    - bat-atsm-1:         NOTRUN -> [SKIP][75] ([i915#1836]) +6 similar issues
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/bat-atsm-1/igt@kms_pipe_crc_basic@hang-read-crc.html

  * igt@kms_pipe_crc_basic@read-crc:
    - bat-adlp-9:         NOTRUN -> [SKIP][76] ([i915#3546]) +1 similar issue
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/bat-adlp-9/igt@kms_pipe_crc_basic@read-crc.html

  * igt@kms_prop_blob@basic:
    - bat-atsm-1:         NOTRUN -> [SKIP][77] ([i915#7357])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/bat-atsm-1/igt@kms_prop_blob@basic.html

  * igt@kms_psr@sprite_plane_onoff:
    - bat-atsm-1:         NOTRUN -> [SKIP][78] ([i915#1072]) +3 similar issues
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/bat-atsm-1/igt@kms_psr@sprite_plane_onoff.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-atsm-1:         NOTRUN -> [SKIP][79] ([i915#6094])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/bat-atsm-1/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-flip:
    - bat-atsm-1:         NOTRUN -> [SKIP][80] ([fdo#109295] / [i915#6078])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/bat-atsm-1/igt@prime_vgem@basic-fence-flip.html

  * igt@prime_vgem@basic-fence-mmap:
    - bat-atsm-1:         NOTRUN -> [SKIP][81] ([fdo#109295] / [i915#4077]) +1 similar issue
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/bat-atsm-1/igt@prime_vgem@basic-fence-mmap.html

  * igt@prime_vgem@basic-write:
    - bat-atsm-1:         NOTRUN -> [SKIP][82] ([fdo#109295]) +3 similar issues
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/bat-atsm-1/igt@prime_vgem@basic-write.html

  * igt@runner@aborted:
    - fi-kbl-8809g:       NOTRUN -> [FAIL][83] ([i915#4991])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/fi-kbl-8809g/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1836]: https://gitlab.freedesktop.org/drm/intel/issues/1836
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
  [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
  [i915#6077]: https://gitlab.freedesktop.org/drm/intel/issues/6077
  [i915#6078]: https://gitlab.freedesktop.org/drm/intel/issues/6078
  [i915#6093]: https://gitlab.freedesktop.org/drm/intel/issues/6093
  [i915#6094]: https://gitlab.freedesktop.org/drm/intel/issues/6094
  [i915#6166]: https://gitlab.freedesktop.org/drm/intel/issues/6166
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
  [i915#7357]: https://gitlab.freedesktop.org/drm/intel/issues/7357
  [i915#7714]: https://gitlab.freedesktop.org/drm/intel/issues/7714
  [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913


Build changes
-------------

  * Linux: CI_DRM_12751 -> Patchwork_114112v1

  CI-20190529: 20190529
  CI_DRM_12751: b6ba15d59cdc7e7d488646370f9ca6b0a36f9db5 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7161: 5574f110ae838031eef6db5236bad02e8c2d2dee @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_114112v1: b6ba15d59cdc7e7d488646370f9ca6b0a36f9db5 @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

9c52b95c13e6 drm/i915/dmc: allocate dmc structure dynamically
4fc8483fa066 drm/i915/dmc: add i915_to_dmc() and dmc->i915 and use them
5119bf472b69 drm/i915/power: move dc state members to struct i915_power_domains

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114112v1/index.html

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