From: Jani Nikula <jani.nikula@linux.intel.com>
To: Matt Roper <matthew.d.roper@intel.com>,
Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v7 1/4] drm/i915: Remove skl_ddl_allocation struct
Date: Fri, 13 Dec 2019 08:28:39 +0200 [thread overview]
Message-ID: <87wob020yw.fsf@intel.com> (raw)
In-Reply-To: <20191213042213.GW85422@mdroper-desk1.amr.corp.intel.com>
On Thu, 12 Dec 2019, Matt Roper <matthew.d.roper@intel.com> wrote:
> On Fri, Nov 29, 2019 at 03:37:06PM +0200, Stanislav Lisovskiy wrote:
>> struct skl_wm_level {
>> @@ -1215,6 +1210,8 @@ struct drm_i915_private {
>> bool distrust_bios_wm;
>> } wm;
>>
>> + u8 enabled_slices; /* GEN11 has configurable 2 slices */
>
> Intel hardware has long used the terms "slice" and "subslice" for the
> way EUs are grouped on the GT side. Now that this is pulled out from
> the substructs that gave it additional context, I think we need to
> rename this to something like 'enabled_dbuf_slices' to avoid confusion
> with the more widespread meaning of the word 'slice.' Same for
> intel_atomic_state farther up.
Agreed.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
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next prev parent reply other threads:[~2019-12-13 6:28 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-29 13:37 [PATCH v7 0/4] Enable second DBuf slice for ICL and TGL Stanislav Lisovskiy
2019-11-29 13:37 ` [Intel-gfx] " Stanislav Lisovskiy
2019-11-29 13:37 ` [PATCH v7 1/4] drm/i915: Remove skl_ddl_allocation struct Stanislav Lisovskiy
2019-11-29 13:37 ` [Intel-gfx] " Stanislav Lisovskiy
2019-12-13 4:22 ` Matt Roper
2019-12-13 6:28 ` Jani Nikula [this message]
2019-12-13 8:27 ` Lisovskiy, Stanislav
2019-11-29 13:37 ` [PATCH v7 2/4] drm/i915: Move dbuf slice update to proper place Stanislav Lisovskiy
2019-11-29 13:37 ` [Intel-gfx] " Stanislav Lisovskiy
2019-12-13 4:22 ` Matt Roper
2019-11-29 13:37 ` [PATCH v7 3/4] drm/i915: Manipulate DBuf slices properly Stanislav Lisovskiy
2019-11-29 13:37 ` [Intel-gfx] " Stanislav Lisovskiy
2019-11-29 13:37 ` [PATCH v7 4/4] drm/i915: Correctly map DBUF slices to pipes Stanislav Lisovskiy
2019-11-29 13:37 ` [Intel-gfx] " Stanislav Lisovskiy
2019-11-29 21:10 ` ✓ Fi.CI.BAT: success for Enable second DBuf slice for ICL and TGL (rev3) Patchwork
2019-11-29 21:10 ` [Intel-gfx] " Patchwork
2019-11-30 23:00 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-11-30 23:00 ` [Intel-gfx] " Patchwork
2019-12-03 0:20 ` ✗ Fi.CI.BAT: failure for Enable second DBuf slice for ICL and TGL (rev4) Patchwork
2019-12-03 0:20 ` [Intel-gfx] " Patchwork
2019-12-03 9:22 ` Lisovskiy, Stanislav
2019-12-05 14:34 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Enable second DBuf slice for ICL and TGL (rev5) Patchwork
2019-12-05 18:40 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2019-12-09 7:55 ` Lisovskiy, Stanislav
2019-12-09 8:11 ` Vudum, Lakshminarayana
2019-12-09 8:40 ` Lisovskiy, Stanislav
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