Re: [PATCH v4 6/7] MIPS: mobileye: eyeq5: add two Cadence GEM Ethernet controllers

[Gregory CLEMENT <gregory.clement@bootlin.com>]

Hello Thomas,

> Add both MACB/GEM instances found in the Mobileye EyeQ5 SoC.
>
> Acked-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

Can you confirm that you will include this patch and the following one
in your mips-next branch?

As you gave your Acked-by on it, I believe this will be the case, but I
want to be sure they aren't forgotten.

Thanks!

Gregory

> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
> ---
>  arch/mips/boot/dts/mobileye/eyeq5.dtsi | 45 ++++++++++++++++++++++++++++++++++
>  1 file changed, 45 insertions(+)
>
> diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi
> index 36a73e8a63a1..cec5ad875228 100644
> --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi
> +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi
> @@ -77,6 +77,8 @@ aliases {
>  		serial0 = &uart0;
>  		serial1 = &uart1;
>  		serial2 = &uart2;
> +		ethernet0 = &macb0;
> +		ethernet1 = &macb1;
>  	};
>  
>  	cpu_intc: interrupt-controller {
> @@ -231,6 +233,7 @@ olb: system-controller@e00000 {
>  			#clock-cells = <1>;
>  			clocks = <&xtal>;
>  			clock-names = "ref";
> +			#phy-cells = <1>;
>  		};
>  
>  		gic: interrupt-controller@140000 {
> @@ -305,6 +308,48 @@ gpio1: gpio@1500000 {
>  			#interrupt-cells = <2>;
>  			resets = <&olb 0 26>;
>  		};
> +
> +		iocu-bus {
> +			compatible = "simple-bus";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			ranges;
> +			dma-coherent;
> +			dma-ranges = <0x10 0x00000000 0x0 0x0 0x10 0>;
> +
> +			macb0: ethernet@2a00000 {
> +				compatible = "mobileye,eyeq5-gem";
> +				reg = <0x0 0x02a00000 0x0 0x4000>;
> +				interrupt-parent = <&gic>;
> +				/* One interrupt per queue */
> +				interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>,
> +					     <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>,
> +					     <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>,
> +					     <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
> +				clock-names = "pclk", "hclk", "tsu_clk";
> +				clocks = <&pclk>, <&pclk>, <&tsu_clk>;
> +				nvmem-cells = <&eth0_mac>;
> +				nvmem-cell-names = "mac-address";
> +				phys = <&olb 0>;
> +			};
> +
> +			macb1: ethernet@2b00000 {
> +				compatible = "mobileye,eyeq5-gem";
> +				reg = <0x0 0x02b00000 0x0 0x4000>;
> +				interrupt-parent = <&gic>;
> +				/* One interrupt per queue */
> +				interrupts = <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
> +					     <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
> +					     <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
> +					     <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
> +				clock-names = "pclk", "hclk", "tsu_clk";
> +				clocks = <&pclk>, <&pclk>, <&tsu_clk>;
> +				nvmem-cells = <&eth1_mac>;
> +				nvmem-cell-names = "mac-address";
> +				phys = <&olb 1>;
> +			};
> +		};
> +
>  	};
>  };
>  
>
> -- 
> 2.51.2
>

-- 
Grégory CLEMENT, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com