[PATCH v5 00/12] Add Support for RZ/G3E ICU

[PATCH v5 00/12] Add Support for RZ/G3E ICU

[Biju Das]

The ICU block on the RZ/G3E SoC is almost identical to the one found on
the RZ/V2H SoC, with the following differences:
 - The TINT register base offset is 0x800 instead of zero.
 - The number of supported GPIO interrupts for TINT selection is 141
   instead of 86.
 - The pin index and TINT selection index are not in the 1:1 map
 - The number of TSSR registers is 16 instead of 8
 - Each TSSR register can program 2 TINTs instead of 4 TINTs

Add support for the RZ/G3E ICU driver.

Note:
  The SoC dtsi patch is dropped from series as it is queued for
  renesas-devel.

v4->v5:
 * Collected tags from Geert.
 * Added a new patch for fixing wrong variable usage in
   rzv2h_tint_set_type().
 * Shortened tssr calculation in rzv2h_tint_irq_endisable().
 * Added tssr_shift_factor variable for optimizing the calculation
   in rzv2h_tint_set_type().
 * Dropped unnecessary parenthesis for calculating tssr in
   rzv2h_tint_set_type().
v3->v4:
 * Updated typo in commit description register offset->register
   base offset.
 * Update typo 15->16 for the number of TSSR registers in RZ/G3E
 * Collected tags.
 * Fixed the typo varable->variable.
 * Started using field_width to handle the SoC differences ad dropped the
   variables tien, tssel_mask,tssel_shift and tssr_k.
 * Dropped RZG3E_* macros from SoC dtsi.
v2->v3:
 * Added a new patch for cleanup using devm_add_action_or_reset() for
   calling put_device() in error path of rzv2h_icu_init() to simplify
   the code by using recently added devm_*helpers.
 * Replaced 'goto put_dev' by 'return xxx' as put_dev() called by
   devm_add_action_or_reset()
v1->v2:
 * Collected tags
 * Split the simplification patch into two.
 * Updated commit header and description for patch#4.
 * Replaced devm_reset_control_get_optional_exclusive_deasserted()->
   devm_reset_control_get_exclusive_deasserted().
 * Moved simplification using devm_pm_runtime_enable() to patch#5.
 * Aligned kernel doc, struct members and struct initializers in
   a tabular fashion.
 * Renamed the macro ICU_PB5_TINT->ICU_RZV2H_TSSEL_MAX_VAL.
 * Replaced hexa decimal constant with ICU_RZV2H_TSSEL_MAX_VAL in struct
   rzv2h_hw_params.
 * Introduced ICU_RZG3E_{TSSEL_MAX_VAL,TINT_OFFSET} macros and used these
   macros in struct rzv2h_hw_params rather than using the hex constants.

Biju Das (12):
  dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/G3E
    SoC
  irqchip/renesas-rzv2h: Fix wrong variable usage in
    rzv2h_tint_set_type()
  irqchip/renesas-rzv2h: Drop irqchip from struct rzv2h_icu_priv
  irqchip/renesas-rzv2h: Simplify rzv2h_icu_init()
  irqchip/renesas-rzv2h: Use
    devm_reset_control_get_exclusive_deasserted()
  irqchip/renesas-rzv2h: Use devm_pm_runtime_enable()
  irqchip/renesas-rzv2h: Add struct rzv2h_hw_info with t_offs variable
  irqchip/renesas-rzv2h: Add max_tssel variable to struct rzv2h_hw_info
  irqchip/renesas-rzv2h: Add field_width variable to struct
    rzv2h_hw_info
  irqchip/renesas-rzv2h: Drop TSSR_TIEN macro
  irqchip/renesas-rzv2h: Drop macros ICU_TSSR_TSSEL_{MASK,PREP}
  irqchip/renesas-rzv2h: Add RZ/G3E support

 .../renesas,rzv2h-icu.yaml                    |   6 +-
 drivers/irqchip/irq-renesas-rzv2h.c           | 189 ++++++++++++------
 2 files changed, 133 insertions(+), 62 deletions(-)

-- 
2.43.0

[PATCH v5 01/12] dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/G3E SoC

[Biju Das]

Document RZ/G3E (R9A09G047) ICU bindings. The ICU block on the RZ/G3E
SoC is almost identical to the one found on the RZ/V2H SoC, with the
following differences:
 - The TINT register base offset is 0x800 instead of zero.
 - The number of supported GPIO interrupts for TINT selection is 141
   instead of 86.
 - The pin index and TINT selection index are not in the 1:1 map
 - The number of TSSR registers is 16 instead of 8
 - Each TSSR register can program 2 TINTs instead of 4 TINTs

Hence new compatible string "renesas,r9a09g047-icu" is added for RZ/G3E
SoC.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v4->v5:
 * No change.
v3->v4:
 * Updated typo in commit description offset->base offset.
 * Update typo 15->16 for the number of TSSR registers in RZ/G3E
 * Collected tags.
v2->v3:
 * No change.
v1->v2:
 * Collected tags.
---
 .../bindings/interrupt-controller/renesas,rzv2h-icu.yaml    | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml
index d7ef4f1323a7..3f99c8645767 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml
@@ -4,7 +4,7 @@
 $id: http://devicetree.org/schemas/interrupt-controller/renesas,rzv2h-icu.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Renesas RZ/V2H(P) Interrupt Control Unit
+title: Renesas RZ/{G3E,V2H(P)} Interrupt Control Unit
 
 maintainers:
   - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
@@ -20,7 +20,9 @@ description:
 
 properties:
   compatible:
-    const: renesas,r9a09g057-icu # RZ/V2H(P)
+    enum:
+      - renesas,r9a09g047-icu # RZ/G3E
+      - renesas,r9a09g057-icu # RZ/V2H(P)
 
   '#interrupt-cells':
     description: The first cell is the SPI number of the NMI or the
-- 
2.43.0

[PATCH v5 02/12] irqchip/renesas-rzv2h: Fix wrong variable usage in rzv2h_tint_set_type()

[Biju Das]

The variable tssel_n is used for selecting TINT source and titsel_n for
setting the interrupt type. The variable titsel_n is wrongly used for
enabling the TINT interrupt in rzv2h_tint_set_type(). Fix this issue by
using the correct variable tssel_n.

While at it, move the tien variable assignment near to tssr.

Fixes: 0d7605e75ac2 ("irqchip: Add RZ/V2H(P) Interrupt Control Unit (ICU) driver")
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v5:
 * New patch
---
 drivers/irqchip/irq-renesas-rzv2h.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
index fe2d29e91026..f6363246a71a 100644
--- a/drivers/irqchip/irq-renesas-rzv2h.c
+++ b/drivers/irqchip/irq-renesas-rzv2h.c
@@ -301,10 +301,10 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
 
 	tssr_k = ICU_TSSR_K(tint_nr);
 	tssel_n = ICU_TSSR_TSSEL_N(tint_nr);
+	tien = ICU_TSSR_TIEN(tssel_n);
 
 	titsr_k = ICU_TITSR_K(tint_nr);
 	titsel_n = ICU_TITSR_TITSEL_N(tint_nr);
-	tien = ICU_TSSR_TIEN(titsel_n);
 
 	guard(raw_spinlock)(&priv->lock);
 
-- 
2.43.0

[PATCH v5 03/12] irqchip/renesas-rzv2h: Drop irqchip from struct rzv2h_icu_priv

[Biju Das]

Use rzv2h_icu_chip directly on irq_domain_set_hwirq_and_chip() and drop
the global variable irqchip from struct rzv2h_icu_priv.

Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v4->v5:
 * No change.
v3->v4:
 * Collected tag from Geert.
v2->v3:
 * No change.
v1->v2:
 * Collected tags.
---
 drivers/irqchip/irq-renesas-rzv2h.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
index f6363246a71a..0573062c89c4 100644
--- a/drivers/irqchip/irq-renesas-rzv2h.c
+++ b/drivers/irqchip/irq-renesas-rzv2h.c
@@ -83,13 +83,11 @@
 /**
  * struct rzv2h_icu_priv - Interrupt Control Unit controller private data structure.
  * @base:	Controller's base address
- * @irqchip:	Pointer to struct irq_chip
  * @fwspec:	IRQ firmware specific data
  * @lock:	Lock to serialize access to hardware registers
  */
 struct rzv2h_icu_priv {
 	void __iomem			*base;
-	const struct irq_chip		*irqchip;
 	struct irq_fwspec		fwspec[ICU_NUM_IRQ];
 	raw_spinlock_t			lock;
 };
@@ -390,7 +388,7 @@ static int rzv2h_icu_alloc(struct irq_domain *domain, unsigned int virq, unsigne
 	if (hwirq > (ICU_NUM_IRQ - 1))
 		return -EINVAL;
 
-	ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, priv->irqchip,
+	ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &rzv2h_icu_chip,
 					    (void *)(uintptr_t)tint);
 	if (ret)
 		return ret;
@@ -446,8 +444,6 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
 		goto put_dev;
 	}
 
-	rzv2h_icu_data->irqchip = &rzv2h_icu_chip;
-
 	rzv2h_icu_data->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
 	if (IS_ERR(rzv2h_icu_data->base)) {
 		ret = PTR_ERR(rzv2h_icu_data->base);
-- 
2.43.0

[PATCH v5 04/12] irqchip/renesas-rzv2h: Simplify rzv2h_icu_init()

[Biju Das]

Use devm_add_action_or_reset() for calling put_device in error path
of rzv2h_icu_init() to simplify the code by using recently added devm_*
helpers.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v4->v5:
 * No change.
v3->v4:
 * Collected the tags.
v3:
 * New patch 
---
 drivers/irqchip/irq-renesas-rzv2h.c | 37 +++++++++++++++--------------
 1 file changed, 19 insertions(+), 18 deletions(-)

diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
index 0573062c89c4..d724f32dde8f 100644
--- a/drivers/irqchip/irq-renesas-rzv2h.c
+++ b/drivers/irqchip/irq-renesas-rzv2h.c
@@ -419,6 +419,11 @@ static int rzv2h_icu_parse_interrupts(struct rzv2h_icu_priv *priv, struct device
 	return 0;
 }
 
+static void rzv2h_icu_put_device(void *data)
+{
+	put_device(data);
+}
+
 static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
 {
 	struct irq_domain *irq_domain, *parent_domain;
@@ -431,41 +436,39 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
 	if (!pdev)
 		return -ENODEV;
 
+	ret = devm_add_action_or_reset(&pdev->dev, rzv2h_icu_put_device,
+				       &pdev->dev);
+	if (ret < 0)
+		return ret;
+
 	parent_domain = irq_find_host(parent);
 	if (!parent_domain) {
 		dev_err(&pdev->dev, "cannot find parent domain\n");
-		ret = -ENODEV;
-		goto put_dev;
+		return -ENODEV;
 	}
 
 	rzv2h_icu_data = devm_kzalloc(&pdev->dev, sizeof(*rzv2h_icu_data), GFP_KERNEL);
-	if (!rzv2h_icu_data) {
-		ret = -ENOMEM;
-		goto put_dev;
-	}
+	if (!rzv2h_icu_data)
+		return -ENOMEM;
 
 	rzv2h_icu_data->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
-	if (IS_ERR(rzv2h_icu_data->base)) {
-		ret = PTR_ERR(rzv2h_icu_data->base);
-		goto put_dev;
-	}
+	if (IS_ERR(rzv2h_icu_data->base))
+		return PTR_ERR(rzv2h_icu_data->base);
 
 	ret = rzv2h_icu_parse_interrupts(rzv2h_icu_data, node);
 	if (ret) {
 		dev_err(&pdev->dev, "cannot parse interrupts: %d\n", ret);
-		goto put_dev;
+		return ret;
 	}
 
 	resetn = devm_reset_control_get_exclusive(&pdev->dev, NULL);
-	if (IS_ERR(resetn)) {
-		ret = PTR_ERR(resetn);
-		goto put_dev;
-	}
+	if (IS_ERR(resetn))
+		return PTR_ERR(resetn);
 
 	ret = reset_control_deassert(resetn);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to deassert resetn pin, %d\n", ret);
-		goto put_dev;
+		return ret;
 	}
 
 	pm_runtime_enable(&pdev->dev);
@@ -496,8 +499,6 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
 pm_disable:
 	pm_runtime_disable(&pdev->dev);
 	reset_control_assert(resetn);
-put_dev:
-	put_device(&pdev->dev);
 
 	return ret;
 }
-- 
2.43.0

[PATCH v5 05/12] irqchip/renesas-rzv2h: Use devm_reset_control_get_exclusive_deasserted()

[Biju Das]

Use devm_reset_control_get_exclusive_deasserted() to simplify
rzv2h_icu_init().

Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v4->v5:
 * No change.
v3->v4:
 * Collected tags.
v2->v3:
 * Replaced 'goto put_dev' by 'return xxx' as put_device() called by
   devm_add_action_or_reset().
v1->v2:
 * Split the simplification patch into two.
 * Updated commit header and description.
 * Replaced devm_reset_control_get_optional_exclusive_deasserted()->
   devm_reset_control_get_exclusive_deasserted().
 * Moved simplification using devm_pm_runtime_enable() to next patch.
---
 drivers/irqchip/irq-renesas-rzv2h.c | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
index d724f32dde8f..edae54f9f5da 100644
--- a/drivers/irqchip/irq-renesas-rzv2h.c
+++ b/drivers/irqchip/irq-renesas-rzv2h.c
@@ -461,13 +461,10 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
 		return ret;
 	}
 
-	resetn = devm_reset_control_get_exclusive(&pdev->dev, NULL);
-	if (IS_ERR(resetn))
-		return PTR_ERR(resetn);
-
-	ret = reset_control_deassert(resetn);
-	if (ret) {
-		dev_err(&pdev->dev, "failed to deassert resetn pin, %d\n", ret);
+	resetn = devm_reset_control_get_exclusive_deasserted(&pdev->dev, NULL);
+	if (IS_ERR(resetn)) {
+		ret = PTR_ERR(resetn);
+		dev_err(&pdev->dev, "failed to acquire deasserted reset: %d\n", ret);
 		return ret;
 	}
 
@@ -498,7 +495,6 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
 	pm_runtime_put(&pdev->dev);
 pm_disable:
 	pm_runtime_disable(&pdev->dev);
-	reset_control_assert(resetn);
 
 	return ret;
 }
-- 
2.43.0

[PATCH v5 06/12] irqchip/renesas-rzv2h: Use devm_pm_runtime_enable()

[Biju Das]

Simplify rzv2h_icu_init() by using devm_pm_runtime_enable().

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v4->v5:
 * No change.
v3->v4:
 * Collected tags.
v2->v3:
 * Updated commit header.
 * Replaced 'goto put_dev' by 'return ret' as put_device() called by
   devm_add_action_or_reset().
v2:
 * New patch.
---
 drivers/irqchip/irq-renesas-rzv2h.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
index edae54f9f5da..10b9b63a1f09 100644
--- a/drivers/irqchip/irq-renesas-rzv2h.c
+++ b/drivers/irqchip/irq-renesas-rzv2h.c
@@ -468,11 +468,16 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
 		return ret;
 	}
 
-	pm_runtime_enable(&pdev->dev);
+	ret = devm_pm_runtime_enable(&pdev->dev);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "devm_pm_runtime_enable failed, %d\n", ret);
+		return ret;
+	}
+
 	ret = pm_runtime_resume_and_get(&pdev->dev);
 	if (ret < 0) {
 		dev_err(&pdev->dev, "pm_runtime_resume_and_get failed: %d\n", ret);
-		goto pm_disable;
+		return ret;
 	}
 
 	raw_spin_lock_init(&rzv2h_icu_data->lock);
@@ -493,8 +498,6 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
 
 pm_put:
 	pm_runtime_put(&pdev->dev);
-pm_disable:
-	pm_runtime_disable(&pdev->dev);
 
 	return ret;
 }
-- 
2.43.0

[PATCH v5 07/12] irqchip/renesas-rzv2h: Add struct rzv2h_hw_info with t_offs variable

[Biju Das]

The ICU block on the RZ/G3E SoC is almost identical to the one found on
the RZ/V2H SoC, with the following differences:
 - The TINT register base offset is 0x800 instead of zero.
 - The number of GPIO interrupts for TINT selection is 141 instead of 86.
 - The pin index and TINT selection index are not in the 1:1 map
 - The number of TSSR registers is 16 instead of 8
 - Each TSSR register can program 2 TINTs instead of 4 TINTs

Introduce struct rzv2h_hw_info to handle these differences and add t_offs
variable to take care of the TINT register offset difference between
RZ/G3E and RZ/V2H.

Refactor the code by moving rzv2h_icu_init() into rzv2h_icu_init_common()
and pass the variable containing hw difference to support both these SoCs.

Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v4->v5:
 * No change.
v3->v4:
 * Updated commit description with register offset->register base offset
 * Fixed typo 15->16 for the number of TSSR register for RZ/G3E.
 * Fixed the typo varable->variable.
 * Collected tag from Geert.
v2->v3:
 * No change.
v1->v2:
 * Collected tags
 * Started aligning kernel doc, struct members and struct initializers in
   a tabular fashion.
---
 drivers/irqchip/irq-renesas-rzv2h.c | 46 +++++++++++++++++++++--------
 1 file changed, 34 insertions(+), 12 deletions(-)

diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
index 10b9b63a1f09..43b805b6df94 100644
--- a/drivers/irqchip/irq-renesas-rzv2h.c
+++ b/drivers/irqchip/irq-renesas-rzv2h.c
@@ -80,16 +80,26 @@
 #define ICU_TINT_EXTRACT_GPIOINT(x)		FIELD_GET(GENMASK(31, 16), (x))
 #define ICU_PB5_TINT				0x55
 
+/**
+ * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure.
+ * @t_offs:		TINT offset
+ */
+struct rzv2h_hw_info {
+	u16		t_offs;
+};
+
 /**
  * struct rzv2h_icu_priv - Interrupt Control Unit controller private data structure.
  * @base:	Controller's base address
  * @fwspec:	IRQ firmware specific data
  * @lock:	Lock to serialize access to hardware registers
+ * @info:	Pointer to struct rzv2h_hw_info
  */
 struct rzv2h_icu_priv {
 	void __iomem			*base;
 	struct irq_fwspec		fwspec[ICU_NUM_IRQ];
 	raw_spinlock_t			lock;
+	const struct rzv2h_hw_info	*info;
 };
 
 static inline struct rzv2h_icu_priv *irq_data_to_priv(struct irq_data *data)
@@ -109,7 +119,7 @@ static void rzv2h_icu_eoi(struct irq_data *d)
 			tintirq_nr = hw_irq - ICU_TINT_START;
 			bit = BIT(tintirq_nr);
 			if (!irqd_is_level_type(d))
-				writel_relaxed(bit, priv->base + ICU_TSCLR);
+				writel_relaxed(bit, priv->base + priv->info->t_offs + ICU_TSCLR);
 		} else if (hw_irq >= ICU_IRQ_START) {
 			tintirq_nr = hw_irq - ICU_IRQ_START;
 			bit = BIT(tintirq_nr);
@@ -137,12 +147,12 @@ static void rzv2h_tint_irq_endisable(struct irq_data *d, bool enable)
 	tssel_n = ICU_TSSR_TSSEL_N(tint_nr);
 
 	guard(raw_spinlock)(&priv->lock);
-	tssr = readl_relaxed(priv->base + ICU_TSSR(k));
+	tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(k));
 	if (enable)
 		tssr |= ICU_TSSR_TIEN(tssel_n);
 	else
 		tssr &= ~ICU_TSSR_TIEN(tssel_n);
-	writel_relaxed(tssr, priv->base + ICU_TSSR(k));
+	writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(k));
 }
 
 static void rzv2h_icu_irq_disable(struct irq_data *d)
@@ -245,8 +255,8 @@ static void rzv2h_clear_tint_int(struct rzv2h_icu_priv *priv, unsigned int hwirq
 	u32 bit = BIT(tint_nr);
 	int k = tint_nr / 16;
 
-	tsctr = readl_relaxed(priv->base + ICU_TSCTR);
-	titsr = readl_relaxed(priv->base + ICU_TITSR(k));
+	tsctr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSCTR);
+	titsr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TITSR(k));
 	titsel = ICU_TITSR_TITSEL_GET(titsr, titsel_n);
 
 	/*
@@ -255,7 +265,7 @@ static void rzv2h_clear_tint_int(struct rzv2h_icu_priv *priv, unsigned int hwirq
 	 */
 	if ((tsctr & bit) && ((titsel == ICU_TINT_EDGE_RISING) ||
 			      (titsel == ICU_TINT_EDGE_FALLING)))
-		writel_relaxed(bit, priv->base + ICU_TSCLR);
+		writel_relaxed(bit, priv->base + priv->info->t_offs + ICU_TSCLR);
 }
 
 static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
@@ -306,21 +316,21 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
 
 	guard(raw_spinlock)(&priv->lock);
 
-	tssr = readl_relaxed(priv->base + ICU_TSSR(tssr_k));
+	tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(tssr_k));
 	tssr &= ~(ICU_TSSR_TSSEL_MASK(tssel_n) | tien);
 	tssr |= ICU_TSSR_TSSEL_PREP(tint, tssel_n);
 
-	writel_relaxed(tssr, priv->base + ICU_TSSR(tssr_k));
+	writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(tssr_k));
 
-	titsr = readl_relaxed(priv->base + ICU_TITSR(titsr_k));
+	titsr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TITSR(titsr_k));
 	titsr &= ~ICU_TITSR_TITSEL_MASK(titsel_n);
 	titsr |= ICU_TITSR_TITSEL_PREP(sense, titsel_n);
 
-	writel_relaxed(titsr, priv->base + ICU_TITSR(titsr_k));
+	writel_relaxed(titsr, priv->base + priv->info->t_offs + ICU_TITSR(titsr_k));
 
 	rzv2h_clear_tint_int(priv, hwirq);
 
-	writel_relaxed(tssr | tien, priv->base + ICU_TSSR(tssr_k));
+	writel_relaxed(tssr | tien, priv->base + priv->info->t_offs + ICU_TSSR(tssr_k));
 
 	return 0;
 }
@@ -424,7 +434,8 @@ static void rzv2h_icu_put_device(void *data)
 	put_device(data);
 }
 
-static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
+static int rzv2h_icu_init_common(struct device_node *node, struct device_node *parent,
+				 const struct rzv2h_hw_info *hw_info)
 {
 	struct irq_domain *irq_domain, *parent_domain;
 	struct rzv2h_icu_priv *rzv2h_icu_data;
@@ -490,6 +501,8 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
 		goto pm_put;
 	}
 
+	rzv2h_icu_data->info = hw_info;
+
 	/*
 	 * coccicheck complains about a missing put_device call before returning, but it's a false
 	 * positive. We still need &pdev->dev after successfully returning from this function.
@@ -502,6 +515,15 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
 	return ret;
 }
 
+static const struct rzv2h_hw_info rzv2h_hw_params = {
+	.t_offs		= 0,
+};
+
+static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
+{
+	return rzv2h_icu_init_common(node, parent, &rzv2h_hw_params);
+}
+
 IRQCHIP_PLATFORM_DRIVER_BEGIN(rzv2h_icu)
 IRQCHIP_MATCH("renesas,r9a09g057-icu", rzv2h_icu_init)
 IRQCHIP_PLATFORM_DRIVER_END(rzv2h_icu)
-- 
2.43.0

[PATCH v5 08/12] irqchip/renesas-rzv2h: Add max_tssel variable to struct rzv2h_hw_info

[Biju Das]

The number of GPIO interrupts on RZ/G3E for TINT selection is 141 compared
to 86 on RZ/V2H. Rename the macro ICU_PB5_TINT->ICU_RZV2H_TSSEL_MAX_VAL to
hold this difference for RZ/V2H.

Add max_tssel variable to struct rzv2h_hw_info to handle this difference.

Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v4->v5:
 * No change.
v3->v4:
 * Collected tag from Geert.
v2->v3:
 * No change.
v1->v2:
 * Renamed the macro ICU_PB5_TINT->ICU_RZV2H_TSSEL_MAX_VAL.
 * Replaced hexa decimal constant with ICU_RZV2H_TSSEL_MAX_VAL in struct
   rzv2h_hw_params.
---
 drivers/irqchip/irq-renesas-rzv2h.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
index 43b805b6df94..2fae3274c015 100644
--- a/drivers/irqchip/irq-renesas-rzv2h.c
+++ b/drivers/irqchip/irq-renesas-rzv2h.c
@@ -78,14 +78,16 @@
 
 #define ICU_TINT_EXTRACT_HWIRQ(x)		FIELD_GET(GENMASK(15, 0), (x))
 #define ICU_TINT_EXTRACT_GPIOINT(x)		FIELD_GET(GENMASK(31, 16), (x))
-#define ICU_PB5_TINT				0x55
+#define ICU_RZV2H_TSSEL_MAX_VAL			0x55
 
 /**
  * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure.
  * @t_offs:		TINT offset
+ * @max_tssel:		TSSEL max value
  */
 struct rzv2h_hw_info {
 	u16		t_offs;
+	u8		max_tssel;
 };
 
 /**
@@ -298,13 +300,12 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
 		return -EINVAL;
 	}
 
+	priv = irq_data_to_priv(d);
 	tint = (u32)(uintptr_t)irq_data_get_irq_chip_data(d);
-	if (tint > ICU_PB5_TINT)
+	if (tint > priv->info->max_tssel)
 		return -EINVAL;
 
-	priv = irq_data_to_priv(d);
 	hwirq = irqd_to_hwirq(d);
-
 	tint_nr = hwirq - ICU_TINT_START;
 
 	tssr_k = ICU_TSSR_K(tint_nr);
@@ -517,6 +518,7 @@ static int rzv2h_icu_init_common(struct device_node *node, struct device_node *p
 
 static const struct rzv2h_hw_info rzv2h_hw_params = {
 	.t_offs		= 0,
+	.max_tssel	= ICU_RZV2H_TSSEL_MAX_VAL,
 };
 
 static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
-- 
2.43.0

[PATCH v5 09/12] irqchip/renesas-rzv2h: Add field_width variable to struct rzv2h_hw_info

[Biju Das]

On RZ/G3E the field width for TSSR register for a TINT is 16 compared to 8
on the RZ/V2H. Add field_width variable to struct rzv2h_hw_info to handle
this difference and drop the macros ICU_TSSR_K and ICU_TSSR_TSSEL_N as
(32 / field_width) provides the number of tints in TSSR register.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v4->v5:
 * Added Rb tag from Geert.
v4:
 New patch using field_width to handle the differences.
---
 drivers/irqchip/irq-renesas-rzv2h.c | 17 +++++++++++------
 1 file changed, 11 insertions(+), 6 deletions(-)

diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
index 2fae3274c015..98a6a7cd3611 100644
--- a/drivers/irqchip/irq-renesas-rzv2h.c
+++ b/drivers/irqchip/irq-renesas-rzv2h.c
@@ -64,8 +64,6 @@
 #define ICU_TINT_LEVEL_HIGH			2
 #define ICU_TINT_LEVEL_LOW			3
 
-#define ICU_TSSR_K(tint_nr)			((tint_nr) / 4)
-#define ICU_TSSR_TSSEL_N(tint_nr)		((tint_nr) % 4)
 #define ICU_TSSR_TSSEL_PREP(tssel, n)		((tssel) << ((n) * 8))
 #define ICU_TSSR_TSSEL_MASK(n)			ICU_TSSR_TSSEL_PREP(0x7F, n)
 #define ICU_TSSR_TIEN(n)			(BIT(7) << ((n) * 8))
@@ -84,10 +82,12 @@
  * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure.
  * @t_offs:		TINT offset
  * @max_tssel:		TSSEL max value
+ * @field_width:	TSSR field width
  */
 struct rzv2h_hw_info {
 	u16		t_offs;
 	u8		max_tssel;
+	u8		field_width;
 };
 
 /**
@@ -140,13 +140,15 @@ static void rzv2h_tint_irq_endisable(struct irq_data *d, bool enable)
 	struct rzv2h_icu_priv *priv = irq_data_to_priv(d);
 	unsigned int hw_irq = irqd_to_hwirq(d);
 	u32 tint_nr, tssel_n, k, tssr;
+	u8 nr_tint;
 
 	if (hw_irq < ICU_TINT_START)
 		return;
 
 	tint_nr = hw_irq - ICU_TINT_START;
-	k = ICU_TSSR_K(tint_nr);
-	tssel_n = ICU_TSSR_TSSEL_N(tint_nr);
+	nr_tint = 32 / priv->info->field_width;
+	k = tint_nr / nr_tint;
+	tssel_n = tint_nr % nr_tint;
 
 	guard(raw_spinlock)(&priv->lock);
 	tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(k));
@@ -278,6 +280,7 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
 	unsigned int hwirq;
 	u32 tint, sense;
 	int tint_nr;
+	u8 nr_tint;
 
 	switch (type & IRQ_TYPE_SENSE_MASK) {
 	case IRQ_TYPE_LEVEL_LOW:
@@ -308,8 +311,9 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
 	hwirq = irqd_to_hwirq(d);
 	tint_nr = hwirq - ICU_TINT_START;
 
-	tssr_k = ICU_TSSR_K(tint_nr);
-	tssel_n = ICU_TSSR_TSSEL_N(tint_nr);
+	nr_tint = 32 / priv->info->field_width;
+	tssr_k = tint_nr / nr_tint;
+	tssel_n = tint_nr % nr_tint;
 	tien = ICU_TSSR_TIEN(tssel_n);
 
 	titsr_k = ICU_TITSR_K(tint_nr);
@@ -519,6 +523,7 @@ static int rzv2h_icu_init_common(struct device_node *node, struct device_node *p
 static const struct rzv2h_hw_info rzv2h_hw_params = {
 	.t_offs		= 0,
 	.max_tssel	= ICU_RZV2H_TSSEL_MAX_VAL,
+	.field_width	= 8,
 };
 
 static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
-- 
2.43.0

[PATCH v5 10/12] irqchip/renesas-rzv2h: Drop TSSR_TIEN macro

[Biju Das]

On RZ/G3E, TIEN bit position is at 15 compared to 7 on RZ/V2H. The macro
ICU_TSSR_TIEN(n) can be replaced with the inline logic
BIT(field_width - 1) << (n * fieldwidth) for supporting both SoCs.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v4->v5:
 * Shortened tssr calculation in rzv2h_tint_irq_endisable().
 * Added tssr_shift_factor variable for optimizing the calculation
   in rzv2h_tint_set_type() as the next patch uses the same factor.
v4:
 * New patch
---
 drivers/irqchip/irq-renesas-rzv2h.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
index 98a6a7cd3611..3635597ae4c1 100644
--- a/drivers/irqchip/irq-renesas-rzv2h.c
+++ b/drivers/irqchip/irq-renesas-rzv2h.c
@@ -66,7 +66,6 @@
 
 #define ICU_TSSR_TSSEL_PREP(tssel, n)		((tssel) << ((n) * 8))
 #define ICU_TSSR_TSSEL_MASK(n)			ICU_TSSR_TSSEL_PREP(0x7F, n)
-#define ICU_TSSR_TIEN(n)			(BIT(7) << ((n) * 8))
 
 #define ICU_TITSR_K(tint_nr)			((tint_nr) / 16)
 #define ICU_TITSR_TITSEL_N(tint_nr)		((tint_nr) % 16)
@@ -153,9 +152,9 @@ static void rzv2h_tint_irq_endisable(struct irq_data *d, bool enable)
 	guard(raw_spinlock)(&priv->lock);
 	tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(k));
 	if (enable)
-		tssr |= ICU_TSSR_TIEN(tssel_n);
+		tssr |= BIT((tssel_n + 1) * priv->info->field_width - 1);
 	else
-		tssr &= ~ICU_TSSR_TIEN(tssel_n);
+		tssr &= ~(BIT((tssel_n + 1) * priv->info->field_width - 1));
 	writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(k));
 }
 
@@ -277,6 +276,7 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
 	u32 titsr, titsr_k, titsel_n, tien;
 	struct rzv2h_icu_priv *priv;
 	u32 tssr, tssr_k, tssel_n;
+	u32 tssr_shift_factor;
 	unsigned int hwirq;
 	u32 tint, sense;
 	int tint_nr;
@@ -314,7 +314,8 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
 	nr_tint = 32 / priv->info->field_width;
 	tssr_k = tint_nr / nr_tint;
 	tssel_n = tint_nr % nr_tint;
-	tien = ICU_TSSR_TIEN(tssel_n);
+	tssr_shift_factor = tssel_n * priv->info->field_width;
+	tien = BIT(priv->info->field_width - 1) << tssr_shift_factor;
 
 	titsr_k = ICU_TITSR_K(tint_nr);
 	titsel_n = ICU_TITSR_TITSEL_N(tint_nr);
-- 
2.43.0

[PATCH v5 11/12] irqchip/renesas-rzv2h: Drop macros ICU_TSSR_TSSEL_{MASK,PREP}

[Biju Das]

On RZ/G3E, TSSEL register field is 8 bits wide compared to 7 on RZ/V2H.
Also bits 8..14 is reserved on RZ/G3E and any writes on these reserved
bits is ignored. Use the bitmask GENMASK(field_width - 2, 0) on both SoCs
for extracting TSSEL and we can drop the macros ICU_TSSR_TSSEL_PREP and
ICU_TSSR_TSSEL_MASK.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v4->v5:
 * Used tssr_shift_factor in rzv2h_tint_set_type to optimize the
   calculation.
 * Dropped unnecessary parenthesis for calculating tssr.
 * Added Rb tag from Geert.
v4:
 * New patch
---
 drivers/irqchip/irq-renesas-rzv2h.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
index 3635597ae4c1..6cfa7f663ce0 100644
--- a/drivers/irqchip/irq-renesas-rzv2h.c
+++ b/drivers/irqchip/irq-renesas-rzv2h.c
@@ -64,9 +64,6 @@
 #define ICU_TINT_LEVEL_HIGH			2
 #define ICU_TINT_LEVEL_LOW			3
 
-#define ICU_TSSR_TSSEL_PREP(tssel, n)		((tssel) << ((n) * 8))
-#define ICU_TSSR_TSSEL_MASK(n)			ICU_TSSR_TSSEL_PREP(0x7F, n)
-
 #define ICU_TITSR_K(tint_nr)			((tint_nr) / 16)
 #define ICU_TITSR_TITSEL_N(tint_nr)		((tint_nr) % 16)
 #define ICU_TITSR_TITSEL_PREP(titsel, n)	ICU_IITSR_IITSEL_PREP(titsel, n)
@@ -323,8 +320,8 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
 	guard(raw_spinlock)(&priv->lock);
 
 	tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(tssr_k));
-	tssr &= ~(ICU_TSSR_TSSEL_MASK(tssel_n) | tien);
-	tssr |= ICU_TSSR_TSSEL_PREP(tint, tssel_n);
+	tssr &= ~((GENMASK(priv->info->field_width - 2, 0) << tssr_shift_factor) | tien);
+	tssr |= tint << tssr_shift_factor;
 
 	writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(tssr_k));
 
-- 
2.43.0

[PATCH v5 12/12] irqchip/renesas-rzv2h: Add RZ/G3E support

[Biju Das]

The ICU block on the RZ/G3E SoC is almost identical to the one found on
the RZ/V2H SoC, with the following differences:
 - The TINT register base offset is 0x800 instead of zero.
 - The number of GPIO interrupts for TINT selection is 141 instead of 86.
 - The pin index and TINT selection index are not in the 1:1 map.
 - The number of TSSR registers is 16 instead of 8.
 - Each TSSR register can program 2 TINTs instead of 4 TINTs.

Add support for the RZ/G3E driver by filling the rzv2h_hw_info table and
adding LUT for mapping between pin index and TINT selection index.

Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v4->v5:
 * Added Rb tag from Geert.
v3->v4:
 * Updated commit description fixing typos
 * Updated rzg3e_hw_params with .field_width and dropped .tien,
  .tssel_mask,.tssel_shift, .tssr_k as it can be derived from former.
v2->v3:
 * No change.
v1->v2:
 * Introduced ICU_RZG3E_{TSSEL_MAX_VAL,TINT_OFFSET} macros and used these
   macros in struct rzv2h_hw_params rather than using the hex constants.
---
 drivers/irqchip/irq-renesas-rzv2h.c | 46 +++++++++++++++++++++++++++++
 1 file changed, 46 insertions(+)

diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
index 6cfa7f663ce0..9b64acc22adc 100644
--- a/drivers/irqchip/irq-renesas-rzv2h.c
+++ b/drivers/irqchip/irq-renesas-rzv2h.c
@@ -72,15 +72,19 @@
 
 #define ICU_TINT_EXTRACT_HWIRQ(x)		FIELD_GET(GENMASK(15, 0), (x))
 #define ICU_TINT_EXTRACT_GPIOINT(x)		FIELD_GET(GENMASK(31, 16), (x))
+#define ICU_RZG3E_TINT_OFFSET			0x800
+#define ICU_RZG3E_TSSEL_MAX_VAL			0x8c
 #define ICU_RZV2H_TSSEL_MAX_VAL			0x55
 
 /**
  * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure.
+ * @tssel_lut:		TINT lookup table
  * @t_offs:		TINT offset
  * @max_tssel:		TSSEL max value
  * @field_width:	TSSR field width
  */
 struct rzv2h_hw_info {
+	const u8	*tssel_lut;
 	u16		t_offs;
 	u8		max_tssel;
 	u8		field_width;
@@ -305,6 +309,9 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
 	if (tint > priv->info->max_tssel)
 		return -EINVAL;
 
+	if (priv->info->tssel_lut)
+		tint = priv->info->tssel_lut[tint];
+
 	hwirq = irqd_to_hwirq(d);
 	tint_nr = hwirq - ICU_TINT_START;
 
@@ -518,18 +525,57 @@ static int rzv2h_icu_init_common(struct device_node *node, struct device_node *p
 	return ret;
 }
 
+/* Mapping based on port index on Table 4.2-6 and TSSEL bits on Table 4.6-4 */
+static const u8 rzg3e_tssel_lut[] = {
+	81, 82, 83, 84, 85, 86, 87, 88,		/* P00-P07 */
+	89, 90, 91, 92, 93, 94, 95, 96,		/* P10-P17 */
+	111, 112,				/* P20-P21 */
+	97, 98, 99, 100, 101, 102, 103, 104,	/* P30-P37 */
+	105, 106, 107, 108, 109, 110,		/* P40-P45 */
+	113, 114, 115, 116, 117, 118, 119,	/* P50-P56 */
+	120, 121, 122, 123, 124, 125, 126,	/* P60-P66 */
+	127, 128, 129, 130, 131, 132, 133, 134,	/* P70-P77 */
+	135, 136, 137, 138, 139, 140,		/* P80-P85 */
+	43, 44, 45, 46, 47, 48, 49, 50,		/* PA0-PA7 */
+	51, 52, 53, 54, 55, 56, 57, 58,		/* PB0-PB7 */
+	59, 60,	61,				/* PC0-PC2 */
+	62, 63, 64, 65, 66, 67, 68, 69,		/* PD0-PD7 */
+	70, 71, 72, 73, 74, 75, 76, 77,		/* PE0-PE7 */
+	78, 79, 80,				/* PF0-PF2 */
+	25, 26, 27, 28, 29, 30, 31, 32,		/* PG0-PG7 */
+	33, 34, 35, 36, 37, 38,			/* PH0-PH5 */
+	4, 5, 6, 7, 8,				/* PJ0-PJ4 */
+	39, 40, 41, 42,				/* PK0-PK3 */
+	9, 10, 11, 12, 21, 22, 23, 24,		/* PL0-PL7 */
+	13, 14, 15, 16, 17, 18, 19, 20,		/* PM0-PM7 */
+	0, 1, 2, 3				/* PS0-PS3 */
+};
+
+static const struct rzv2h_hw_info rzg3e_hw_params = {
+	.tssel_lut	= rzg3e_tssel_lut,
+	.t_offs		= ICU_RZG3E_TINT_OFFSET,
+	.max_tssel	= ICU_RZG3E_TSSEL_MAX_VAL,
+	.field_width	= 16,
+};
+
 static const struct rzv2h_hw_info rzv2h_hw_params = {
 	.t_offs		= 0,
 	.max_tssel	= ICU_RZV2H_TSSEL_MAX_VAL,
 	.field_width	= 8,
 };
 
+static int rzg3e_icu_init(struct device_node *node, struct device_node *parent)
+{
+	return rzv2h_icu_init_common(node, parent, &rzg3e_hw_params);
+}
+
 static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
 {
 	return rzv2h_icu_init_common(node, parent, &rzv2h_hw_params);
 }
 
 IRQCHIP_PLATFORM_DRIVER_BEGIN(rzv2h_icu)
+IRQCHIP_MATCH("renesas,r9a09g047-icu", rzg3e_icu_init)
 IRQCHIP_MATCH("renesas,r9a09g057-icu", rzv2h_icu_init)
 IRQCHIP_PLATFORM_DRIVER_END(rzv2h_icu)
 MODULE_AUTHOR("Fabrizio Castro <fabrizio.castro.jz@renesas.com>");
-- 
2.43.0

Re: [PATCH v5 02/12] irqchip/renesas-rzv2h: Fix wrong variable usage in rzv2h_tint_set_type()

[Geert Uytterhoeven]

On Wed, 12 Feb 2025 at 12:12, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> The variable tssel_n is used for selecting TINT source and titsel_n for
> setting the interrupt type. The variable titsel_n is wrongly used for
> enabling the TINT interrupt in rzv2h_tint_set_type(). Fix this issue by
> using the correct variable tssel_n.
>
> While at it, move the tien variable assignment near to tssr.
>
> Fixes: 0d7605e75ac2 ("irqchip: Add RZ/V2H(P) Interrupt Control Unit (ICU) driver")
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
Closes: https://lore.kernel.org/CAMuHMdU3xJpz-jh=j7t4JreBat2of2ksP_OR3+nKAoZBr4pSxg@mail.gmail.com

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH v5 10/12] irqchip/renesas-rzv2h: Drop TSSR_TIEN macro

[Biju Das]

Hi Thomas Gleixner, Geert,

> -----Original Message-----
> From: Biju Das <biju.das.jz@bp.renesas.com>
> Sent: 12 February 2025 11:12
> Subject: [PATCH v5 10/12] irqchip/renesas-rzv2h: Drop TSSR_TIEN macro
> 
> On RZ/G3E, TIEN bit position is at 15 compared to 7 on RZ/V2H. The macro
> ICU_TSSR_TIEN(n) can be replaced with the inline logic BIT(field_width - 1) << (n * fieldwidth) for
> supporting both SoCs.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v4->v5:
>  * Shortened tssr calculation in rzv2h_tint_irq_endisable().
>  * Added tssr_shift_factor variable for optimizing the calculation
>    in rzv2h_tint_set_type() as the next patch uses the same factor.
> v4:
>  * New patch
> ---
>  drivers/irqchip/irq-renesas-rzv2h.c | 9 +++++----
>  1 file changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
> index 98a6a7cd3611..3635597ae4c1 100644
> --- a/drivers/irqchip/irq-renesas-rzv2h.c
> +++ b/drivers/irqchip/irq-renesas-rzv2h.c
> @@ -66,7 +66,6 @@
> 
>  #define ICU_TSSR_TSSEL_PREP(tssel, n)		((tssel) << ((n) * 8))
>  #define ICU_TSSR_TSSEL_MASK(n)			ICU_TSSR_TSSEL_PREP(0x7F, n)
> -#define ICU_TSSR_TIEN(n)			(BIT(7) << ((n) * 8))


Please let me know, instead I should retain this macro with[1] and see changes below inlined??

#define ICU_TSSR_TIEN(mask, n, shift) ((mask) << ((n) * (shift)))

> 
>  #define ICU_TITSR_K(tint_nr)			((tint_nr) / 16)
>  #define ICU_TITSR_TITSEL_N(tint_nr)		((tint_nr) % 16)
> @@ -153,9 +152,9 @@ static void rzv2h_tint_irq_endisable(struct irq_data *d, bool enable)
>  	guard(raw_spinlock)(&priv->lock);
>  	tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(k));
>  	if (enable)
> -		tssr |= ICU_TSSR_TIEN(tssel_n);
> +		tssr |= BIT((tssel_n + 1) * priv->info->field_width - 1);
		tssr |= ICU_TSSR_TIEN(priv->info->field_width - 1, tssel_n, priv->info->field_width);
>  	else
> -		tssr &= ~ICU_TSSR_TIEN(tssel_n);
> +		tssr &= ~(BIT((tssel_n + 1) * priv->info->field_width - 1));
		tssr &= ~ICU_TSSR_TIEN(priv->info->field_width - 1, tssel_n, priv->info->field_width);

>  	writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(k));  }
> 
> @@ -277,6 +276,7 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
>  	u32 titsr, titsr_k, titsel_n, tien;
>  	struct rzv2h_icu_priv *priv;
>  	u32 tssr, tssr_k, tssel_n;
> +	u32 tssr_shift_factor;
>  	unsigned int hwirq;
>  	u32 tint, sense;
>  	int tint_nr;
> @@ -314,7 +314,8 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
>  	nr_tint = 32 / priv->info->field_width;
>  	tssr_k = tint_nr / nr_tint;
>  	tssel_n = tint_nr % nr_tint;
> -	tien = ICU_TSSR_TIEN(tssel_n);

tien = ICU_TSSR_TIEN(priv->info->field_width - 1, tssel_n, priv->info->field_width);

Cheers,
Biju

Re: [PATCH v5 10/12] irqchip/renesas-rzv2h: Drop TSSR_TIEN macro

[Geert Uytterhoeven]

Hi Biju,

On Mon, 17 Feb 2025 at 10:36, Biju Das <biju.das.jz@bp.renesas.com> wrote:

> > -----Original Message-----
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> > Sent: 12 February 2025 11:12
> > Subject: [PATCH v5 10/12] irqchip/renesas-rzv2h: Drop TSSR_TIEN macro
> >
> > On RZ/G3E, TIEN bit position is at 15 compared to 7 on RZ/V2H. The macro
> > ICU_TSSR_TIEN(n) can be replaced with the inline logic BIT(field_width - 1) << (n * fieldwidth) for
> > supporting both SoCs.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > v4->v5:
> >  * Shortened tssr calculation in rzv2h_tint_irq_endisable().
> >  * Added tssr_shift_factor variable for optimizing the calculation
> >    in rzv2h_tint_set_type() as the next patch uses the same factor.
> > v4:
> >  * New patch
> > ---
> >  drivers/irqchip/irq-renesas-rzv2h.c | 9 +++++----
> >  1 file changed, 5 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
> > index 98a6a7cd3611..3635597ae4c1 100644
> > --- a/drivers/irqchip/irq-renesas-rzv2h.c
> > +++ b/drivers/irqchip/irq-renesas-rzv2h.c
> > @@ -66,7 +66,6 @@
> >
> >  #define ICU_TSSR_TSSEL_PREP(tssel, n)                ((tssel) << ((n) * 8))
> >  #define ICU_TSSR_TSSEL_MASK(n)                       ICU_TSSR_TSSEL_PREP(0x7F, n)
> > -#define ICU_TSSR_TIEN(n)                     (BIT(7) << ((n) * 8))
>
>
> Please let me know, instead I should retain this macro with[1] and see changes below inlined??

What does [1] refer to?

> #define ICU_TSSR_TIEN(mask, n, shift) ((mask) << ((n) * (shift)))

Isn't "mask" always "BIT(shift -1)"?

"shift" is not the shift value (that is "n * shift"), but the field width.

> >  #define ICU_TITSR_K(tint_nr)                 ((tint_nr) / 16)
> >  #define ICU_TITSR_TITSEL_N(tint_nr)          ((tint_nr) % 16)
> > @@ -153,9 +152,9 @@ static void rzv2h_tint_irq_endisable(struct irq_data *d, bool enable)
> >       guard(raw_spinlock)(&priv->lock);
> >       tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(k));
> >       if (enable)
> > -             tssr |= ICU_TSSR_TIEN(tssel_n);
> > +             tssr |= BIT((tssel_n + 1) * priv->info->field_width - 1);
>                 tssr |= ICU_TSSR_TIEN(priv->info->field_width - 1, tssel_n, priv->info->field_width);

Missing BIT()?

> >       else
> > -             tssr &= ~ICU_TSSR_TIEN(tssel_n);
> > +             tssr &= ~(BIT((tssel_n + 1) * priv->info->field_width - 1));
>                 tssr &= ~ICU_TSSR_TIEN(priv->info->field_width - 1, tssel_n, priv->info->field_width);

Likewise?

>
> >       writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(k));  }
> >
> > @@ -277,6 +276,7 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
> >       u32 titsr, titsr_k, titsel_n, tien;
> >       struct rzv2h_icu_priv *priv;
> >       u32 tssr, tssr_k, tssel_n;
> > +     u32 tssr_shift_factor;
> >       unsigned int hwirq;
> >       u32 tint, sense;
> >       int tint_nr;
> > @@ -314,7 +314,8 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
> >       nr_tint = 32 / priv->info->field_width;
> >       tssr_k = tint_nr / nr_tint;
> >       tssel_n = tint_nr % nr_tint;
> > -     tien = ICU_TSSR_TIEN(tssel_n);
>
> tien = ICU_TSSR_TIEN(priv->info->field_width - 1, tssel_n, priv->info->field_width);

Likewise?

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH v5 10/12] irqchip/renesas-rzv2h: Drop TSSR_TIEN macro

[Biju Das]

Hi Geert,

Thanks for the feedback.

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: 17 February 2025 10:47
> Subject: Re: [PATCH v5 10/12] irqchip/renesas-rzv2h: Drop TSSR_TIEN macro
> 
> Hi Biju,
> 
> On Mon, 17 Feb 2025 at 10:36, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> 
> > > -----Original Message-----
> > > From: Biju Das <biju.das.jz@bp.renesas.com>
> > > Sent: 12 February 2025 11:12
> > > Subject: [PATCH v5 10/12] irqchip/renesas-rzv2h: Drop TSSR_TIEN
> > > macro
> > >
> > > On RZ/G3E, TIEN bit position is at 15 compared to 7 on RZ/V2H. The
> > > macro
> > > ICU_TSSR_TIEN(n) can be replaced with the inline logic
> > > BIT(field_width - 1) << (n * fieldwidth) for supporting both SoCs.
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > ---
> > > v4->v5:
> > >  * Shortened tssr calculation in rzv2h_tint_irq_endisable().
> > >  * Added tssr_shift_factor variable for optimizing the calculation
> > >    in rzv2h_tint_set_type() as the next patch uses the same factor.
> > > v4:
> > >  * New patch
> > > ---
> > >  drivers/irqchip/irq-renesas-rzv2h.c | 9 +++++----
> > >  1 file changed, 5 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/irqchip/irq-renesas-rzv2h.c
> > > b/drivers/irqchip/irq-renesas-rzv2h.c
> > > index 98a6a7cd3611..3635597ae4c1 100644
> > > --- a/drivers/irqchip/irq-renesas-rzv2h.c
> > > +++ b/drivers/irqchip/irq-renesas-rzv2h.c
> > > @@ -66,7 +66,6 @@
> > >
> > >  #define ICU_TSSR_TSSEL_PREP(tssel, n)                ((tssel) << ((n) * 8))
> > >  #define ICU_TSSR_TSSEL_MASK(n)                       ICU_TSSR_TSSEL_PREP(0x7F, n)
> > > -#define ICU_TSSR_TIEN(n)                     (BIT(7) << ((n) * 8))
> >
> >
> > Please let me know, instead I should retain this macro with[1] and see changes below inlined??
> 
> What does [1] refer to?

Oops [1] refers to

[1]

#define ICU_TSSR_TIEN(mask, n, shift) ((mask) << ((n) * (shift)))


> 
> > #define ICU_TSSR_TIEN(mask, n, shift) ((mask) << ((n) * (shift)))
> 
> Isn't "mask" always "BIT(shift -1)"?

That is correct.

> 
> "shift" is not the shift value (that is "n * shift"), but the field width.

Ok, Good point, now it can be shortened as 
 
#define ICU_TSSR_TIEN(field_width, n) (BIT((field_width) - 1) << ((n) * (field_width) - 1))


> 
> > >  #define ICU_TITSR_K(tint_nr)                 ((tint_nr) / 16)
> > >  #define ICU_TITSR_TITSEL_N(tint_nr)          ((tint_nr) % 16)
> > > @@ -153,9 +152,9 @@ static void rzv2h_tint_irq_endisable(struct irq_data *d, bool enable)
> > >       guard(raw_spinlock)(&priv->lock);
> > >       tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(k));
> > >       if (enable)
> > > -             tssr |= ICU_TSSR_TIEN(tssel_n);
> > > +             tssr |= BIT((tssel_n + 1) * priv->info->field_width -
> > > + 1);
> >                 tssr |= ICU_TSSR_TIEN(priv->info->field_width - 1,
> > tssel_n, priv->info->field_width);
> 
> Missing BIT()?

OK, now corrected as 

ICU_TSSR_TIEN(priv->info->field_width, tssel_n);

Cheers,
Biju

RE: [PATCH v5 10/12] irqchip/renesas-rzv2h: Drop TSSR_TIEN macro

[Biju Das]

> -----Original Message-----
> From: Biju Das
> Sent: 17 February 2025 11:03
> Subject: RE: [PATCH v5 10/12] irqchip/renesas-rzv2h: Drop TSSR_TIEN macro
> 
> Hi Geert,
> 
> Thanks for the feedback.
> 
> > -----Original Message-----
> > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > Sent: 17 February 2025 10:47
> > Subject: Re: [PATCH v5 10/12] irqchip/renesas-rzv2h: Drop TSSR_TIEN
> > macro
> >
> > Hi Biju,
> >
> > On Mon, 17 Feb 2025 at 10:36, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> >
> > > > -----Original Message-----
> > > > From: Biju Das <biju.das.jz@bp.renesas.com>
> > > > Sent: 12 February 2025 11:12
> > > > Subject: [PATCH v5 10/12] irqchip/renesas-rzv2h: Drop TSSR_TIEN
> > > > macro
> > > >
> > > > On RZ/G3E, TIEN bit position is at 15 compared to 7 on RZ/V2H. The
> > > > macro
> > > > ICU_TSSR_TIEN(n) can be replaced with the inline logic
> > > > BIT(field_width - 1) << (n * fieldwidth) for supporting both SoCs.
> > > >
> > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > ---
> > > > v4->v5:
> > > >  * Shortened tssr calculation in rzv2h_tint_irq_endisable().
> > > >  * Added tssr_shift_factor variable for optimizing the calculation
> > > >    in rzv2h_tint_set_type() as the next patch uses the same factor.
> > > > v4:
> > > >  * New patch
> > > > ---
> > > >  drivers/irqchip/irq-renesas-rzv2h.c | 9 +++++----
> > > >  1 file changed, 5 insertions(+), 4 deletions(-)
> > > >
> > > > diff --git a/drivers/irqchip/irq-renesas-rzv2h.c
> > > > b/drivers/irqchip/irq-renesas-rzv2h.c
> > > > index 98a6a7cd3611..3635597ae4c1 100644
> > > > --- a/drivers/irqchip/irq-renesas-rzv2h.c
> > > > +++ b/drivers/irqchip/irq-renesas-rzv2h.c
> > > > @@ -66,7 +66,6 @@
> > > >
> > > >  #define ICU_TSSR_TSSEL_PREP(tssel, n)                ((tssel) << ((n) * 8))
> > > >  #define ICU_TSSR_TSSEL_MASK(n)                       ICU_TSSR_TSSEL_PREP(0x7F, n)
> > > > -#define ICU_TSSR_TIEN(n)                     (BIT(7) << ((n) * 8))
> > >
> > >
> > > Please let me know, instead I should retain this macro with[1] and see changes below inlined??
> >
> > What does [1] refer to?
> 
> Oops [1] refers to
> 
> [1]
> 
> #define ICU_TSSR_TIEN(mask, n, shift) ((mask) << ((n) * (shift)))
> 
> 
> >
> > > #define ICU_TSSR_TIEN(mask, n, shift) ((mask) << ((n) * (shift)))
> >
> > Isn't "mask" always "BIT(shift -1)"?
> 
> That is correct.
> 
> >
> > "shift" is not the shift value (that is "n * shift"), but the field width.
> 
> Ok, Good point, now it can be shortened as
> 
> #define ICU_TSSR_TIEN(field_width, n) (BIT((field_width) - 1) << ((n) * (field_width) - 1))

Typo. Correct one is

#define ICU_TSSR_TIEN(field_width, n) (BIT((field_width) - 1) << ((n) * (field_width))

Cheers,
Biju

RE: [PATCH v5 10/12] irqchip/renesas-rzv2h: Drop TSSR_TIEN macro

[Biju Das]

Hi Geert,

> -----Original Message-----
> From: Biju Das
> Sent: 17 February 2025 11:08
> Subject: RE: [PATCH v5 10/12] irqchip/renesas-rzv2h: Drop TSSR_TIEN macro
> 
> 
> 
> > -----Original Message-----
> > From: Biju Das
> > Sent: 17 February 2025 11:03
> > Subject: RE: [PATCH v5 10/12] irqchip/renesas-rzv2h: Drop TSSR_TIEN
> > macro
> >
> > Hi Geert,
> >
> > Thanks for the feedback.
> >
> > > -----Original Message-----
> > > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > > Sent: 17 February 2025 10:47
> > > Subject: Re: [PATCH v5 10/12] irqchip/renesas-rzv2h: Drop TSSR_TIEN
> > > macro
> > >
> > > Hi Biju,
> > >
> > > On Mon, 17 Feb 2025 at 10:36, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > >
> > > > > -----Original Message-----
> > > > > From: Biju Das <biju.das.jz@bp.renesas.com>
> > > > > Sent: 12 February 2025 11:12
> > > > > Subject: [PATCH v5 10/12] irqchip/renesas-rzv2h: Drop TSSR_TIEN
> > > > > macro
> > > > >
> > > > > On RZ/G3E, TIEN bit position is at 15 compared to 7 on RZ/V2H.
> > > > > The macro
> > > > > ICU_TSSR_TIEN(n) can be replaced with the inline logic
> > > > > BIT(field_width - 1) << (n * fieldwidth) for supporting both SoCs.
> > > > >
> > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > > ---
> > > > > v4->v5:
> > > > >  * Shortened tssr calculation in rzv2h_tint_irq_endisable().
> > > > >  * Added tssr_shift_factor variable for optimizing the calculation
> > > > >    in rzv2h_tint_set_type() as the next patch uses the same factor.
> > > > > v4:
> > > > >  * New patch
> > > > > ---
> > > > >  drivers/irqchip/irq-renesas-rzv2h.c | 9 +++++----
> > > > >  1 file changed, 5 insertions(+), 4 deletions(-)
> > > > >
> > > > > diff --git a/drivers/irqchip/irq-renesas-rzv2h.c
> > > > > b/drivers/irqchip/irq-renesas-rzv2h.c
> > > > > index 98a6a7cd3611..3635597ae4c1 100644
> > > > > --- a/drivers/irqchip/irq-renesas-rzv2h.c
> > > > > +++ b/drivers/irqchip/irq-renesas-rzv2h.c
> > > > > @@ -66,7 +66,6 @@
> > > > >
> > > > >  #define ICU_TSSR_TSSEL_PREP(tssel, n)                ((tssel) << ((n) * 8))
> > > > >  #define ICU_TSSR_TSSEL_MASK(n)                       ICU_TSSR_TSSEL_PREP(0x7F, n)
> > > > > -#define ICU_TSSR_TIEN(n)                     (BIT(7) << ((n) * 8))
> > > >
> > > >
> > > > Please let me know, instead I should retain this macro with[1] and see changes below inlined??
> > >
> > > What does [1] refer to?
> >
> > Oops [1] refers to
> >
> > [1]
> >
> > #define ICU_TSSR_TIEN(mask, n, shift) ((mask) << ((n) * (shift)))
> >
> >
> > >
> > > > #define ICU_TSSR_TIEN(mask, n, shift) ((mask) << ((n) * (shift)))
> > >
> > > Isn't "mask" always "BIT(shift -1)"?
> >
> > That is correct.
> >
> > >
> > > "shift" is not the shift value (that is "n * shift"), but the field width.
> >
> > Ok, Good point, now it can be shortened as
> >
> > #define ICU_TSSR_TIEN(field_width, n) (BIT((field_width) - 1) << ((n)
> > * (field_width) - 1))
> 
> Typo. Correct one is
> 
> #define ICU_TSSR_TIEN(field_width, n) (BIT((field_width) - 1) << ((n) * (field_width))

Finally corrected this macro as below to fix the Warnings/error [2]

#define ICU_TSSR_TIEN(_field_width, n)	\
({\
		typeof(_field_width) (field_width) = (_field_width); \
		BIT((field_width) - 1) << ((n) * (field_width)); \
})

[2]
ERROR: Macros with complex values should be enclosed in parentheses
#24: FILE: drivers/irqchip/irq-renesas-rzv2h.c:69:
+#define ICU_TSSR_TIEN(f_width, n)		BIT((f_width) - 1) << ((n) * (f_width))

CHECK: Macro argument reuse 'f_width' - possible side-effects?
#24: FILE: drivers/irqchip/irq-renesas-rzv2h.c:69:
+#define ICU_TSSR_TIEN(f_width, n)		BIT((f_width) - 1) << ((n) * (f_width))

total: 1 errors, 0 warnings, 1 checks, 27 lines checked

Cheers,
Biju

RE: [PATCH v5 00/12] Add Support for RZ/G3E ICU

[Biju Das]

Hi Thomas,

> -----Original Message-----
> From: Biju Das <biju.das.jz@bp.renesas.com>
> Sent: 12 February 2025 11:12
> Subject: [PATCH v5 00/12] Add Support for RZ/G3E ICU
> 
> The ICU block on the RZ/G3E SoC is almost identical to the one found on the RZ/V2H SoC, with the
> following differences:
>  - The TINT register base offset is 0x800 instead of zero.
>  - The number of supported GPIO interrupts for TINT selection is 141
>    instead of 86.
>  - The pin index and TINT selection index are not in the 1:1 map
>  - The number of TSSR registers is 16 instead of 8
>  - Each TSSR register can program 2 TINTs instead of 4 TINTs
> 
> Add support for the RZ/G3E ICU driver.
> 
> Note:
>   The SoC dtsi patch is dropped from series as it is queued for
>   renesas-devel.
> 
> v4->v5:
>  * Collected tags from Geert.
>  * Added a new patch for fixing wrong variable usage in
>    rzv2h_tint_set_type().
>  * Shortened tssr calculation in rzv2h_tint_irq_endisable().
>  * Added tssr_shift_factor variable for optimizing the calculation
>    in rzv2h_tint_set_type().
>  * Dropped unnecessary parenthesis for calculating tssr in
>    rzv2h_tint_set_type().
> v3->v4:
>  * Updated typo in commit description register offset->register
>    base offset.
>  * Update typo 15->16 for the number of TSSR registers in RZ/G3E
>  * Collected tags.
>  * Fixed the typo varable->variable.
>  * Started using field_width to handle the SoC differences ad dropped the
>    variables tien, tssel_mask,tssel_shift and tssr_k.
>  * Dropped RZG3E_* macros from SoC dtsi.
> v2->v3:
>  * Added a new patch for cleanup using devm_add_action_or_reset() for
>    calling put_device() in error path of rzv2h_icu_init() to simplify
>    the code by using recently added devm_*helpers.
>  * Replaced 'goto put_dev' by 'return xxx' as put_dev() called by
>    devm_add_action_or_reset()
> v1->v2:
>  * Collected tags
>  * Split the simplification patch into two.
>  * Updated commit header and description for patch#4.
>  * Replaced devm_reset_control_get_optional_exclusive_deasserted()->
>    devm_reset_control_get_exclusive_deasserted().
>  * Moved simplification using devm_pm_runtime_enable() to patch#5.
>  * Aligned kernel doc, struct members and struct initializers in
>    a tabular fashion.
>  * Renamed the macro ICU_PB5_TINT->ICU_RZV2H_TSSEL_MAX_VAL.
>  * Replaced hexa decimal constant with ICU_RZV2H_TSSEL_MAX_VAL in struct
>    rzv2h_hw_params.
>  * Introduced ICU_RZG3E_{TSSEL_MAX_VAL,TINT_OFFSET} macros and used these
>    macros in struct rzv2h_hw_params rather than using the hex constants.
> 
> Biju Das (12):
>   dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/G3E
>     SoC
>   irqchip/renesas-rzv2h: Fix wrong variable usage in
>     rzv2h_tint_set_type()
>   irqchip/renesas-rzv2h: Drop irqchip from struct rzv2h_icu_priv
>   irqchip/renesas-rzv2h: Simplify rzv2h_icu_init()
>   irqchip/renesas-rzv2h: Use
>     devm_reset_control_get_exclusive_deasserted()
>   irqchip/renesas-rzv2h: Use devm_pm_runtime_enable()
>   irqchip/renesas-rzv2h: Add struct rzv2h_hw_info with t_offs variable
>   irqchip/renesas-rzv2h: Add max_tssel variable to struct rzv2h_hw_info
>   irqchip/renesas-rzv2h: Add field_width variable to struct
>     rzv2h_hw_info
>   irqchip/renesas-rzv2h: Drop TSSR_TIEN macro
>   irqchip/renesas-rzv2h: Drop macros ICU_TSSR_TSSEL_{MASK,PREP}
>   irqchip/renesas-rzv2h: Add RZ/G3E support
> 
>  .../renesas,rzv2h-icu.yaml                    |   6 +-
>  drivers/irqchip/irq-renesas-rzv2h.c           | 189 ++++++++++++------
>  2 files changed, 133 insertions(+), 62 deletions(-)
> 

Gentle ping. Should I rebase to [1] and resend.
Please let me know.

[1] https://lore.kernel.org/all/20250220150110.738619-5-fabrizio.castro.jz@renesas.com/

Cheers,
Biju

RE: [PATCH v5 00/12] Add Support for RZ/G3E ICU

[Thomas Gleixner]

On Mon, Feb 24 2025 at 10:48, Biju Das wrote:
> Gentle ping. Should I rebase to [1] and resend.
> Please let me know.
>
> [1] https://lore.kernel.org/all/20250220150110.738619-5-fabrizio.castro.jz@renesas.com/

Yes. I've marked this series obsolete due to the discussion about patch
10.

Please rebase on top of tip irq/drivers.

Thanks,

        tglx

RE: [PATCH v5 00/12] Add Support for RZ/G3E ICU

[Biju Das]

Hi Thomas,

Thanks for the feedback.

> -----Original Message-----
> From: Thomas Gleixner <tglx@linutronix.de>
> Sent: 24 February 2025 11:22
> Subject: RE: [PATCH v5 00/12] Add Support for RZ/G3E ICU
> 
> On Mon, Feb 24 2025 at 10:48, Biju Das wrote:
> > Gentle ping. Should I rebase to [1] and resend.
> > Please let me know.
> >
> > [1]
> > https://lore.kernel.org/all/20250220150110.738619-5-fabrizio.castro.jz
> > @renesas.com/
> 
> Yes. I've marked this series obsolete due to the discussion about patch 10.
> 
> Please rebase on top of tip irq/drivers.

OK, will send next version retaining the macros by adding field_width
parameter to it.

Cheers,
Biju