All of lore.kernel.org
 help / color / mirror / Atom feed
From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
	intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 18/18] drm/i915: Suck snps/cx0 PLL states into dpll_hw_state
Date: Mon, 15 Apr 2024 17:26:11 +0300	[thread overview]
Message-ID: <87y19e1z3w.fsf@intel.com> (raw)
In-Reply-To: <20240412182703.19916-19-ville.syrjala@linux.intel.com>

On Fri, 12 Apr 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index d0ec6196d398..f09e513ce05b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -229,6 +229,43 @@ struct icl_dpll_hw_state {
>  	u32 mg_pll_tdc_coldst_bias_mask;
>  };
>  
> +struct intel_mpllb_state {
> +	u32 clock; /* in KHz */
> +	u32 ref_control;
> +	u32 mpllb_cp;
> +	u32 mpllb_div;
> +	u32 mpllb_div2;
> +	u32 mpllb_fracn1;
> +	u32 mpllb_fracn2;
> +	u32 mpllb_sscen;
> +	u32 mpllb_sscstep;
> +};
> +
> +struct intel_c10pll_state {
> +	u32 clock; /* in KHz */
> +	u8 tx;
> +	u8 cmn;
> +	u8 pll[20];
> +};
> +
> +struct intel_c20pll_state {
> +	u32 clock; /* in kHz */
> +	u16 tx[3];
> +	u16 cmn[4];
> +	union {
> +		u16 mplla[10];
> +		u16 mpllb[11];
> +	};
> +};
> +
> +struct intel_cx0pll_state {
> +	union {
> +		struct intel_c10pll_state c10;
> +		struct intel_c20pll_state c20;
> +	};
> +	bool ssc_enabled;
> +};

IMO struct intel_cx0pll_state should be dropped in follow-up, with
ssc_enabled moved to both intel_c10pll_state and intel_c20pll_state...

> +
>  struct intel_dpll_hw_state {
>  	union {
>  		struct i9xx_dpll_hw_state i9xx;
> @@ -236,6 +273,8 @@ struct intel_dpll_hw_state {
>  		struct skl_dpll_hw_state skl;
>  		struct bxt_dpll_hw_state bxt;
>  		struct icl_dpll_hw_state icl;
> +		struct intel_mpllb_state mpllb;
> +		struct intel_cx0pll_state cx0pll;

...and both added here i.e. the union at a step higher.

BR,
Jani.

>  	};
>  };
>  

-- 
Jani Nikula, Intel

  reply	other threads:[~2024-04-15 14:26 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-04-12 18:26 [PATCH 00/18] drm/i915: PLL refactoring Ville Syrjala
2024-04-12 18:26 ` [PATCH 01/18] drm/i915: Replace hand rolled PLL state dump with intel_dpll_dump_hw_state() Ville Syrjala
2024-04-12 18:26 ` [PATCH 02/18] drm/i915: Use printer for the rest of PLL debugfs dump Ville Syrjala
2024-04-12 18:26 ` [PATCH 03/18] drm/i915: Rename PLL hw_state variables/arguments Ville Syrjala
2024-04-12 18:26 ` [PATCH 04/18] drm/i915: Introduce some local PLL state variables Ville Syrjala
2024-04-12 18:26 ` [PATCH 05/18] drm/i915: Extract ilk_fb_cb_factor() Ville Syrjala
2024-04-12 18:26 ` [PATCH 06/18] drm/i915: Extract ilk_dpll_compute_fp() Ville Syrjala
2024-04-12 18:26 ` [PATCH 07/18] drm/i915: Extract i9xx_dpll_get_hw_state() Ville Syrjala
2024-04-12 18:26 ` [PATCH 08/18] drm/i915: Pass the PLL hw_state to pll->enable() Ville Syrjala
2024-04-12 18:26 ` [PATCH 09/18] drm/i915: Extract i965_dpll_md() Ville Syrjala
2024-04-12 18:26 ` [PATCH 10/18] drm/i915: Extract {i9xx,i8xx,ilk}_dpll() Ville Syrjala
2024-04-15 14:06   ` Jani Nikula
2024-04-12 18:26 ` [PATCH 11/18] drm/i915: Inline {i9xx,ilk}_update_pll_dividers() Ville Syrjala
2024-04-12 18:26 ` [PATCH 12/18] drm/i915: Modernize i9xx_pll_refclk() Ville Syrjala
2024-04-12 18:26 ` [PATCH 13/18] drm/i915: Drop pointless 'crtc' argument from *_crtc_clock_get() Ville Syrjala
2024-04-12 18:26 ` [PATCH 14/18] drm/i915: s/pipe_config/crtc_state/ in legacy PLL code Ville Syrjala
2024-04-12 18:27 ` [PATCH 15/18] drm/i915: Add local DPLL 'hw_state' variables Ville Syrjala
2024-04-12 18:27 ` [PATCH 16/18] drm/i915: Carve up struct intel_dpll_hw_state Ville Syrjala
2024-04-12 18:27 ` [PATCH 17/18] drm/i915: Unionize dpll_hw_state Ville Syrjala
2024-04-12 18:27 ` [PATCH 18/18] drm/i915: Suck snps/cx0 PLL states into dpll_hw_state Ville Syrjala
2024-04-15 14:26   ` Jani Nikula [this message]
2024-04-15 14:26 ` [PATCH 00/18] drm/i915: PLL refactoring Jani Nikula
2024-04-15 14:54 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2024-04-15 14:54 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-04-15 15:01 ` ✓ Fi.CI.BAT: success " Patchwork
2024-04-15 19:06 ` ✓ Fi.CI.IGT: " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=87y19e1z3w.fsf@intel.com \
    --to=jani.nikula@linux.intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=ville.syrjala@linux.intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.