* [CI 1/6] drm/i915: Drop dead code for xehpsdv
2024-03-20 6:02 [CI 0/6] drm/i915: cleanup dead code Lucas De Marchi
@ 2024-03-20 6:02 ` Lucas De Marchi
2024-03-20 6:02 ` [CI 2/6] drm/i915: Remove XEHP_FWRANGES() Lucas De Marchi
` (10 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Lucas De Marchi @ 2024-03-20 6:02 UTC (permalink / raw)
To: intel-gfx
PCI IDs for XEHPSDV were never added and platform always marked with
force_probe. Drop what's not used and rename some places to either be
xehp or dg2, depending on the platform/IP checks.
The registers not used anymore are also removed.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
Documentation/gpu/rfc/i915_vm_bind.h | 11 +--
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 40 ++++----
drivers/gpu/drm/i915/gt/intel_gsc.c | 15 ---
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 20 +---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 50 ----------
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 21 ++--
drivers/gpu/drm/i915/gt/intel_lrc.c | 43 ---------
drivers/gpu/drm/i915/gt/intel_migrate.c | 18 ++--
drivers/gpu/drm/i915/gt/intel_mocs.c | 31 ------
drivers/gpu/drm/i915/gt/intel_rps.c | 2 -
drivers/gpu/drm/i915/gt/intel_workarounds.c | 95 -------------------
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +-
drivers/gpu/drm/i915/i915_drv.h | 4 -
drivers/gpu/drm/i915/i915_hwmon.c | 6 --
drivers/gpu/drm/i915/i915_pci.c | 17 ----
drivers/gpu/drm/i915/i915_perf.c | 11 +--
drivers/gpu/drm/i915/i915_reg.h | 3 +-
drivers/gpu/drm/i915/intel_clock_gating.c | 10 --
drivers/gpu/drm/i915/intel_device_info.c | 1 -
drivers/gpu/drm/i915/intel_device_info.h | 1 -
drivers/gpu/drm/i915/intel_step.c | 10 --
drivers/gpu/drm/i915/intel_uncore.c | 23 +----
drivers/gpu/drm/i915/selftests/intel_uncore.c | 1 -
| 2 -
24 files changed, 55 insertions(+), 384 deletions(-)
diff --git a/Documentation/gpu/rfc/i915_vm_bind.h b/Documentation/gpu/rfc/i915_vm_bind.h
index 8a8fcd4fceac6..bc26dc1261041 100644
--- a/Documentation/gpu/rfc/i915_vm_bind.h
+++ b/Documentation/gpu/rfc/i915_vm_bind.h
@@ -93,12 +93,11 @@ struct drm_i915_gem_timeline_fence {
* Multiple VA mappings can be created to the same section of the object
* (aliasing).
*
- * The @start, @offset and @length must be 4K page aligned. However the DG2
- * and XEHPSDV has 64K page size for device local memory and has compact page
- * table. On those platforms, for binding device local-memory objects, the
- * @start, @offset and @length must be 64K aligned. Also, UMDs should not mix
- * the local memory 64K page and the system memory 4K page bindings in the same
- * 2M range.
+ * The @start, @offset and @length must be 4K page aligned. However the DG2 has
+ * 64K page size for device local memory and has compact page table. On that
+ * platform, for binding device local-memory objects, the @start, @offset and
+ * @length must be 64K aligned. Also, UMDs should not mix the local memory 64K
+ * page and the system memory 4K page bindings in the same 2M range.
*
* Error code -EINVAL will be returned if @start, @offset and @length are not
* properly aligned. In version 1 (See I915_PARAM_VM_BIND_VERSION), error code
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index fa46d2308b0ed..1bd0e041e15c2 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -500,11 +500,11 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
}
static void
-xehpsdv_ppgtt_insert_huge(struct i915_address_space *vm,
- struct i915_vma_resource *vma_res,
- struct sgt_dma *iter,
- unsigned int pat_index,
- u32 flags)
+xehp_ppgtt_insert_huge(struct i915_address_space *vm,
+ struct i915_vma_resource *vma_res,
+ struct sgt_dma *iter,
+ unsigned int pat_index,
+ u32 flags)
{
const gen8_pte_t pte_encode = vm->pte_encode(0, pat_index, flags);
unsigned int rem = sg_dma_len(iter->sg);
@@ -741,8 +741,8 @@ static void gen8_ppgtt_insert(struct i915_address_space *vm,
struct sgt_dma iter = sgt_dma(vma_res);
if (vma_res->bi.page_sizes.sg > I915_GTT_PAGE_SIZE) {
- if (GRAPHICS_VER_FULL(vm->i915) >= IP_VER(12, 50))
- xehpsdv_ppgtt_insert_huge(vm, vma_res, &iter, pat_index, flags);
+ if (GRAPHICS_VER_FULL(vm->i915) >= IP_VER(12, 55))
+ xehp_ppgtt_insert_huge(vm, vma_res, &iter, pat_index, flags);
else
gen8_ppgtt_insert_huge(vm, vma_res, &iter, pat_index, flags);
} else {
@@ -781,11 +781,11 @@ static void gen8_ppgtt_insert_entry(struct i915_address_space *vm,
drm_clflush_virt_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr));
}
-static void __xehpsdv_ppgtt_insert_entry_lm(struct i915_address_space *vm,
- dma_addr_t addr,
- u64 offset,
- unsigned int pat_index,
- u32 flags)
+static void xehp_ppgtt_insert_entry_lm(struct i915_address_space *vm,
+ dma_addr_t addr,
+ u64 offset,
+ unsigned int pat_index,
+ u32 flags)
{
u64 idx = offset >> GEN8_PTE_SHIFT;
struct i915_page_directory * const pdp =
@@ -810,15 +810,15 @@ static void __xehpsdv_ppgtt_insert_entry_lm(struct i915_address_space *vm,
vaddr[gen8_pd_index(idx, 0) / 16] = vm->pte_encode(addr, pat_index, flags);
}
-static void xehpsdv_ppgtt_insert_entry(struct i915_address_space *vm,
- dma_addr_t addr,
- u64 offset,
- unsigned int pat_index,
- u32 flags)
+static void xehp_ppgtt_insert_entry(struct i915_address_space *vm,
+ dma_addr_t addr,
+ u64 offset,
+ unsigned int pat_index,
+ u32 flags)
{
if (flags & PTE_LM)
- return __xehpsdv_ppgtt_insert_entry_lm(vm, addr, offset,
- pat_index, flags);
+ return xehp_ppgtt_insert_entry_lm(vm, addr, offset,
+ pat_index, flags);
return gen8_ppgtt_insert_entry(vm, addr, offset, pat_index, flags);
}
@@ -1042,7 +1042,7 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
ppgtt->vm.bind_async_flags = I915_VMA_LOCAL_BIND;
ppgtt->vm.insert_entries = gen8_ppgtt_insert;
if (HAS_64K_PAGES(gt->i915))
- ppgtt->vm.insert_page = xehpsdv_ppgtt_insert_entry;
+ ppgtt->vm.insert_page = xehp_ppgtt_insert_entry;
else
ppgtt->vm.insert_page = gen8_ppgtt_insert_entry;
ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc;
diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/intel_gsc.c
index 6d440de8ba017..1e925c75fb080 100644
--- a/drivers/gpu/drm/i915/gt/intel_gsc.c
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
@@ -103,19 +103,6 @@ static const struct gsc_def gsc_def_dg1[] = {
}
};
-static const struct gsc_def gsc_def_xehpsdv[] = {
- {
- /* HECI1 not enabled on the device. */
- },
- {
- .name = "mei-gscfi",
- .bar = DG1_GSC_HECI2_BASE,
- .bar_size = GSC_BAR_LENGTH,
- .use_polling = true,
- .slow_firmware = true,
- }
-};
-
static const struct gsc_def gsc_def_dg2[] = {
{
.name = "mei-gsc",
@@ -188,8 +175,6 @@ static void gsc_init_one(struct drm_i915_private *i915, struct intel_gsc *gsc,
if (IS_DG1(i915)) {
def = &gsc_def_dg1[intf_id];
- } else if (IS_XEHPSDV(i915)) {
- def = &gsc_def_xehpsdv[intf_id];
} else if (IS_DG2(i915)) {
def = &gsc_def_dg2[intf_id];
} else {
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index e253750a51c56..5a2bd8de155a8 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -57,24 +57,12 @@ static const struct intel_mmio_range icl_l3bank_steering_table[] = {
* are of a "GAM" subclass that has special rules. Thus we use a separate
* GAM table farther down for those.
*/
-static const struct intel_mmio_range xehpsdv_mslice_steering_table[] = {
+static const struct intel_mmio_range dg2_mslice_steering_table[] = {
{ 0x00DD00, 0x00DDFF },
{ 0x00E900, 0x00FFFF }, /* 0xEA00 - OxEFFF is unused */
{},
};
-static const struct intel_mmio_range xehpsdv_gam_steering_table[] = {
- { 0x004000, 0x004AFF },
- { 0x00C800, 0x00CFFF },
- {},
-};
-
-static const struct intel_mmio_range xehpsdv_lncf_steering_table[] = {
- { 0x00B000, 0x00B0FF },
- { 0x00D800, 0x00D8FF },
- {},
-};
-
static const struct intel_mmio_range dg2_lncf_steering_table[] = {
{ 0x00B000, 0x00B0FF },
{ 0x00D880, 0x00D8FF },
@@ -188,17 +176,13 @@ void intel_gt_mcr_init(struct intel_gt *gt)
} else if (IS_PONTEVECCHIO(i915)) {
gt->steering_table[INSTANCE0] = pvc_instance0_steering_table;
} else if (IS_DG2(i915)) {
- gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
+ gt->steering_table[MSLICE] = dg2_mslice_steering_table;
gt->steering_table[LNCF] = dg2_lncf_steering_table;
/*
* No need to hook up the GAM table since it has a dedicated
* steering control register on DG2 and can use implicit
* steering.
*/
- } else if (IS_XEHPSDV(i915)) {
- gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
- gt->steering_table[LNCF] = xehpsdv_lncf_steering_table;
- gt->steering_table[GAM] = xehpsdv_gam_steering_table;
} else if (GRAPHICS_VER(i915) >= 11 &&
GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) {
gt->steering_table[L3BANK] = icl_l3bank_steering_table;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 50962cfd1353a..919c079037677 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -718,44 +718,11 @@
#define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)
#define VFUNIT_CLKGATE_DIS REG_BIT(20)
-#define TSGUNIT_CLKGATE_DIS REG_BIT(17) /* XEHPSDV */
#define CG3DDISCFEG_CLKGATE_DIS REG_BIT(17) /* DG2 */
#define GAMEDIA_CLKGATE_DIS REG_BIT(11)
#define HSUNIT_CLKGATE_DIS REG_BIT(8)
#define VSUNIT_CLKGATE_DIS REG_BIT(3)
-#define UNSLCGCTL9440 _MMIO(0x9440)
-#define GAMTLBOACS_CLKGATE_DIS REG_BIT(28)
-#define GAMTLBVDBOX5_CLKGATE_DIS REG_BIT(27)
-#define GAMTLBVDBOX6_CLKGATE_DIS REG_BIT(26)
-#define GAMTLBVDBOX3_CLKGATE_DIS REG_BIT(24)
-#define GAMTLBVDBOX4_CLKGATE_DIS REG_BIT(23)
-#define GAMTLBVDBOX7_CLKGATE_DIS REG_BIT(22)
-#define GAMTLBVDBOX2_CLKGATE_DIS REG_BIT(21)
-#define GAMTLBVDBOX0_CLKGATE_DIS REG_BIT(17)
-#define GAMTLBKCR_CLKGATE_DIS REG_BIT(16)
-#define GAMTLBGUC_CLKGATE_DIS REG_BIT(15)
-#define GAMTLBBLT_CLKGATE_DIS REG_BIT(14)
-#define GAMTLBVDBOX1_CLKGATE_DIS REG_BIT(6)
-
-#define UNSLCGCTL9444 _MMIO(0x9444)
-#define GAMTLBGFXA0_CLKGATE_DIS REG_BIT(30)
-#define GAMTLBGFXA1_CLKGATE_DIS REG_BIT(29)
-#define GAMTLBCOMPA0_CLKGATE_DIS REG_BIT(28)
-#define GAMTLBCOMPA1_CLKGATE_DIS REG_BIT(27)
-#define GAMTLBCOMPB0_CLKGATE_DIS REG_BIT(26)
-#define GAMTLBCOMPB1_CLKGATE_DIS REG_BIT(25)
-#define GAMTLBCOMPC0_CLKGATE_DIS REG_BIT(24)
-#define GAMTLBCOMPC1_CLKGATE_DIS REG_BIT(23)
-#define GAMTLBCOMPD0_CLKGATE_DIS REG_BIT(22)
-#define GAMTLBCOMPD1_CLKGATE_DIS REG_BIT(21)
-#define GAMTLBMERT_CLKGATE_DIS REG_BIT(20)
-#define GAMTLBVEBOX3_CLKGATE_DIS REG_BIT(19)
-#define GAMTLBVEBOX2_CLKGATE_DIS REG_BIT(18)
-#define GAMTLBVEBOX1_CLKGATE_DIS REG_BIT(17)
-#define GAMTLBVEBOX0_CLKGATE_DIS REG_BIT(16)
-#define LTCDD_CLKGATE_DIS REG_BIT(10)
-
#define GEN11_SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
#define XEHP_SLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x94d4)
#define SARBUNIT_CLKGATE_DIS (1 << 5)
@@ -765,9 +732,6 @@
#define L3_CLKGATE_DIS REG_BIT(16)
#define L3_CR2X_CLKGATE_DIS REG_BIT(17)
-#define SCCGCTL94DC MCR_REG(0x94dc)
-#define CG3DDISURB REG_BIT(14)
-
#define UNSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x94e4)
#define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19)
#define PSDUNIT_CLKGATE_DIS REG_BIT(5)
@@ -1046,9 +1010,6 @@
#define XEHP_L3SQCREG5 MCR_REG(0xb158)
#define L3_PWM_TIMER_INIT_VAL_MASK REG_GENMASK(9, 0)
-#define MLTICTXCTL MCR_REG(0xb170)
-#define TDONRENDER REG_BIT(2)
-
#define XEHP_L3SCQREG7 MCR_REG(0xb188)
#define BLEND_FILL_CACHING_OPT_DIS REG_BIT(3)
@@ -1057,9 +1018,6 @@
#define SCRUB_RATE_PER_BANK_MASK REG_GENMASK(2, 0)
#define SCRUB_RATE_4B_PER_CLK REG_FIELD_PREP(SCRUB_RATE_PER_BANK_MASK, 0x6)
-#define L3SQCREG1_CCS0 MCR_REG(0xb200)
-#define FLUSHALLNONCOH REG_BIT(5)
-
#define GEN11_GLBLINVL _MMIO(0xb404)
#define GEN11_BANK_HASH_ADDR_EXCL_MASK (0x7f << 5)
#define GEN11_BANK_HASH_ADDR_EXCL_BIT0 (1 << 5)
@@ -1109,7 +1067,6 @@
#define XEHP_COMPCTX_TLB_INV_CR MCR_REG(0xcf04)
#define XELPMP_GSC_TLB_INV_CR _MMIO(0xcf04) /* media GT only */
-#define XEHP_MERT_MOD_CTRL MCR_REG(0xcf28)
#define RENDER_MOD_CTRL MCR_REG(0xcf2c)
#define COMP_MOD_CTRL MCR_REG(0xcf30)
#define XELPMP_GSC_MOD_CTRL _MMIO(0xcf30) /* media GT only */
@@ -1185,7 +1142,6 @@
#define EU_PERF_CNTL4 PERF_REG(0xe45c)
#define GEN9_ROW_CHICKEN4 MCR_REG(0xe48c)
-#define GEN12_DISABLE_GRF_CLEAR REG_BIT(13)
#define XEHP_DIS_BBL_SYSPIPE REG_BIT(11)
#define GEN12_DISABLE_TDL_PUSH REG_BIT(9)
#define GEN11_DIS_PICK_2ND_EU REG_BIT(7)
@@ -1202,7 +1158,6 @@
#define FLOW_CONTROL_ENABLE REG_BIT(15)
#define UGM_BACKUP_MODE REG_BIT(13)
#define MDQ_ARBITRATION_MODE REG_BIT(12)
-#define SYSTOLIC_DOP_CLOCK_GATING_DIS REG_BIT(10)
#define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE REG_BIT(8)
#define STALL_DOP_GATING_DISABLE REG_BIT(5)
#define THROTTLE_12_5 REG_GENMASK(4, 2)
@@ -1679,11 +1634,6 @@
#define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000)
-#define GT0_PACKAGE_ENERGY_STATUS _MMIO(0x250004)
-#define GT0_PACKAGE_RAPL_LIMIT _MMIO(0x250008)
-#define GT0_PACKAGE_POWER_SKU_UNIT _MMIO(0x250068)
-#define GT0_PLATFORM_ENERGY_STATUS _MMIO(0x25006c)
-
/*
* Standalone Media's non-engine GT registers are located at their regular GT
* offsets plus 0x380000. This extra offset is stored inside the intel_uncore
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
index eca4a6a65556b..d7784650e4d93 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
@@ -573,7 +573,6 @@ static ssize_t media_freq_factor_show(struct kobject *kobj,
char *buff)
{
struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
- struct intel_guc_slpc *slpc = >_to_guc(gt)->slpc;
intel_wakeref_t wakeref;
u32 mode;
@@ -581,20 +580,12 @@ static ssize_t media_freq_factor_show(struct kobject *kobj,
* Retrieve media_ratio_mode from GEN6_RPNSWREQ bit 13 set by
* GuC. GEN6_RPNSWREQ:13 value 0 represents 1:2 and 1 represents 1:1
*/
- if (IS_XEHPSDV(gt->i915) &&
- slpc->media_ratio_mode == SLPC_MEDIA_RATIO_MODE_DYNAMIC_CONTROL) {
- /*
- * For XEHPSDV dynamic mode GEN6_RPNSWREQ:13 does not contain
- * the media_ratio_mode, just return the cached media ratio
- */
- mode = slpc->media_ratio_mode;
- } else {
- with_intel_runtime_pm(gt->uncore->rpm, wakeref)
- mode = intel_uncore_read(gt->uncore, GEN6_RPNSWREQ);
- mode = REG_FIELD_GET(GEN12_MEDIA_FREQ_RATIO, mode) ?
- SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_ONE :
- SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO;
- }
+ with_intel_runtime_pm(gt->uncore->rpm, wakeref)
+ mode = intel_uncore_read(gt->uncore, GEN6_RPNSWREQ);
+
+ mode = REG_FIELD_GET(GEN12_MEDIA_FREQ_RATIO, mode) ?
+ SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_ONE :
+ SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO;
return sysfs_emit(buff, "%u\n", media_ratio_mode_to_factor(mode));
}
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 7c367ba8d9dcf..7f1b00cb9924c 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -546,47 +546,6 @@ static const u8 gen12_rcs_offsets[] = {
END
};
-static const u8 xehp_rcs_offsets[] = {
- NOP(1),
- LRI(13, POSTED),
- REG16(0x244),
- REG(0x034),
- REG(0x030),
- REG(0x038),
- REG(0x03c),
- REG(0x168),
- REG(0x140),
- REG(0x110),
- REG(0x1c0),
- REG(0x1c4),
- REG(0x1c8),
- REG(0x180),
- REG16(0x2b4),
-
- NOP(5),
- LRI(9, POSTED),
- REG16(0x3a8),
- REG16(0x28c),
- REG16(0x288),
- REG16(0x284),
- REG16(0x280),
- REG16(0x27c),
- REG16(0x278),
- REG16(0x274),
- REG16(0x270),
-
- LRI(3, POSTED),
- REG(0x1b0),
- REG16(0x5a8),
- REG16(0x5ac),
-
- NOP(6),
- LRI(1, 0),
- REG(0x0c8),
-
- END
-};
-
static const u8 dg2_rcs_offsets[] = {
NOP(1),
LRI(15, POSTED),
@@ -695,8 +654,6 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
return mtl_rcs_offsets;
else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
return dg2_rcs_offsets;
- else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
- return xehp_rcs_offsets;
else if (GRAPHICS_VER(engine->i915) >= 12)
return gen12_rcs_offsets;
else if (GRAPHICS_VER(engine->i915) >= 11)
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
index 576e5ef0289ba..86ba2f2e485c5 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -35,9 +35,9 @@ static bool engine_supports_migration(struct intel_engine_cs *engine)
return true;
}
-static void xehpsdv_toggle_pdes(struct i915_address_space *vm,
- struct i915_page_table *pt,
- void *data)
+static void xehp_toggle_pdes(struct i915_address_space *vm,
+ struct i915_page_table *pt,
+ void *data)
{
struct insert_pte_data *d = data;
@@ -52,9 +52,9 @@ static void xehpsdv_toggle_pdes(struct i915_address_space *vm,
d->offset += SZ_2M;
}
-static void xehpsdv_insert_pte(struct i915_address_space *vm,
- struct i915_page_table *pt,
- void *data)
+static void xehp_insert_pte(struct i915_address_space *vm,
+ struct i915_page_table *pt,
+ void *data)
{
struct insert_pte_data *d = data;
@@ -120,7 +120,7 @@ static struct i915_address_space *migrate_vm(struct intel_gt *gt)
* 512 entry layout using 4K GTT pages. The other two windows just map
* lmem pages and must use the new compact 32 entry layout using 64K GTT
* pages, which ensures we can address any lmem object that the user
- * throws at us. We then also use the xehpsdv_toggle_pdes as a way of
+ * throws at us. We then also use the xehp_toggle_pdes as a way of
* just toggling the PDE bit(GEN12_PDE_64K) for us, to enable the
* compact layout for each of these page-tables, that fall within the
* [CHUNK_SIZE, 3 * CHUNK_SIZE) range.
@@ -209,12 +209,12 @@ static struct i915_address_space *migrate_vm(struct intel_gt *gt)
/* Now allow the GPU to rewrite the PTE via its own ppGTT */
if (HAS_64K_PAGES(gt->i915)) {
vm->vm.foreach(&vm->vm, base, d.offset - base,
- xehpsdv_insert_pte, &d);
+ xehp_insert_pte, &d);
d.offset = base + CHUNK_SZ;
vm->vm.foreach(&vm->vm,
d.offset,
2 * CHUNK_SZ,
- xehpsdv_toggle_pdes, &d);
+ xehp_toggle_pdes, &d);
} else {
vm->vm.foreach(&vm->vm, base, d.offset - base,
insert_pte, &d);
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 25c1023eb5f9f..c931c56945bde 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -367,31 +367,6 @@ static const struct drm_i915_mocs_entry gen12_mocs_table[] = {
L3_3_WB),
};
-static const struct drm_i915_mocs_entry xehpsdv_mocs_table[] = {
- /* wa_1608975824 */
- MOCS_ENTRY(0, 0, L3_3_WB | L3_LKUP(1)),
-
- /* UC - Coherent; GO:L3 */
- MOCS_ENTRY(1, 0, L3_1_UC | L3_LKUP(1)),
- /* UC - Coherent; GO:Memory */
- MOCS_ENTRY(2, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)),
- /* UC - Non-Coherent; GO:Memory */
- MOCS_ENTRY(3, 0, L3_1_UC | L3_GLBGO(1)),
- /* UC - Non-Coherent; GO:L3 */
- MOCS_ENTRY(4, 0, L3_1_UC),
-
- /* WB */
- MOCS_ENTRY(5, 0, L3_3_WB | L3_LKUP(1)),
-
- /* HW Reserved - SW program but never use. */
- MOCS_ENTRY(48, 0, L3_3_WB | L3_LKUP(1)),
- MOCS_ENTRY(49, 0, L3_1_UC | L3_LKUP(1)),
- MOCS_ENTRY(60, 0, L3_1_UC),
- MOCS_ENTRY(61, 0, L3_1_UC),
- MOCS_ENTRY(62, 0, L3_1_UC),
- MOCS_ENTRY(63, 0, L3_1_UC),
-};
-
static const struct drm_i915_mocs_entry dg2_mocs_table[] = {
/* UC - Coherent; GO:L3 */
MOCS_ENTRY(0, 0, L3_1_UC | L3_LKUP(1)),
@@ -514,12 +489,6 @@ static unsigned int get_mocs_settings(struct drm_i915_private *i915,
table->uc_index = 1;
table->n_entries = GEN9_NUM_MOCS_ENTRIES;
table->unused_entries_index = 3;
- } else if (IS_XEHPSDV(i915)) {
- table->size = ARRAY_SIZE(xehpsdv_mocs_table);
- table->table = xehpsdv_mocs_table;
- table->uc_index = 2;
- table->n_entries = GEN9_NUM_MOCS_ENTRIES;
- table->unused_entries_index = 5;
} else if (IS_DG1(i915)) {
table->size = ARRAY_SIZE(dg1_mocs_table);
table->table = dg1_mocs_table;
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index a929aa6e3c85a..1788db4376e50 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -1092,8 +1092,6 @@ static u32 intel_rps_read_state_cap(struct intel_rps *rps)
if (IS_PONTEVECCHIO(i915))
return intel_uncore_read(uncore, PVC_RP_STATE_CAP);
- else if (IS_XEHPSDV(i915))
- return intel_uncore_read(uncore, XEHPSDV_RP_STATE_CAP);
else if (IS_GEN9_LP(i915))
return intel_uncore_read(uncore, BXT_RP_STATE_CAP);
else
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index b079cbbc1897e..cfe2f4b64f040 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -922,8 +922,6 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
; /* noop; none at this time */
else if (IS_DG2(i915))
dg2_ctx_workarounds_init(engine, wal);
- else if (IS_XEHPSDV(i915))
- ; /* noop; none at this time */
else if (IS_DG1(i915))
dg1_ctx_workarounds_init(engine, wal);
else if (GRAPHICS_VER(i915) == 12)
@@ -1350,9 +1348,6 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
gt->steering_table[MSLICE] = NULL;
}
- if (IS_XEHPSDV(gt->i915) && slice_mask & BIT(0))
- gt->steering_table[GAM] = NULL;
-
slice = __ffs(slice_mask);
subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice) %
GEN_DSS_PER_GSLICE;
@@ -1519,76 +1514,6 @@ dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE_DIS_TGL);
}
-static void
-xehpsdv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
-{
- struct drm_i915_private *i915 = gt->i915;
-
- xehp_init_mcr(gt, wal);
-
- /* Wa_1409757795:xehpsdv */
- wa_mcr_write_or(wal, SCCGCTL94DC, CG3DDISURB);
-
- /* Wa_18011725039:xehpsdv */
- if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_B0)) {
- wa_mcr_masked_dis(wal, MLTICTXCTL, TDONRENDER);
- wa_mcr_write_or(wal, L3SQCREG1_CCS0, FLUSHALLNONCOH);
- }
-
- /* Wa_16011155590:xehpsdv */
- if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
- wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE,
- TSGUNIT_CLKGATE_DIS);
-
- /* Wa_14011780169:xehpsdv */
- if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER)) {
- wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS |
- GAMTLBVDBOX7_CLKGATE_DIS |
- GAMTLBVDBOX6_CLKGATE_DIS |
- GAMTLBVDBOX5_CLKGATE_DIS |
- GAMTLBVDBOX4_CLKGATE_DIS |
- GAMTLBVDBOX3_CLKGATE_DIS |
- GAMTLBVDBOX2_CLKGATE_DIS |
- GAMTLBVDBOX1_CLKGATE_DIS |
- GAMTLBVDBOX0_CLKGATE_DIS |
- GAMTLBKCR_CLKGATE_DIS |
- GAMTLBGUC_CLKGATE_DIS |
- GAMTLBBLT_CLKGATE_DIS);
- wa_write_or(wal, UNSLCGCTL9444, GAMTLBGFXA0_CLKGATE_DIS |
- GAMTLBGFXA1_CLKGATE_DIS |
- GAMTLBCOMPA0_CLKGATE_DIS |
- GAMTLBCOMPA1_CLKGATE_DIS |
- GAMTLBCOMPB0_CLKGATE_DIS |
- GAMTLBCOMPB1_CLKGATE_DIS |
- GAMTLBCOMPC0_CLKGATE_DIS |
- GAMTLBCOMPC1_CLKGATE_DIS |
- GAMTLBCOMPD0_CLKGATE_DIS |
- GAMTLBCOMPD1_CLKGATE_DIS |
- GAMTLBMERT_CLKGATE_DIS |
- GAMTLBVEBOX3_CLKGATE_DIS |
- GAMTLBVEBOX2_CLKGATE_DIS |
- GAMTLBVEBOX1_CLKGATE_DIS |
- GAMTLBVEBOX0_CLKGATE_DIS);
- }
-
- /* Wa_16012725990:xehpsdv */
- if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_FOREVER))
- wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, VFUNIT_CLKGATE_DIS);
-
- /* Wa_14011060649:xehpsdv */
- wa_14011060649(gt, wal);
-
- /* Wa_14012362059:xehpsdv */
- wa_mcr_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB);
-
- /* Wa_14014368820:xehpsdv */
- wa_mcr_write_or(wal, XEHP_GAMCNTRL_CTRL,
- INVALIDATION_BROADCAST_MODE_DIS | GLOBAL_INVALIDATION_MODE);
-
- /* Wa_14010670810:xehpsdv */
- wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE);
-}
-
static void
dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
{
@@ -1759,8 +1684,6 @@ gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
pvc_gt_workarounds_init(gt, wal);
else if (IS_DG2(i915))
dg2_gt_workarounds_init(gt, wal);
- else if (IS_XEHPSDV(i915))
- xehpsdv_gt_workarounds_init(gt, wal);
else if (IS_DG1(i915))
dg1_gt_workarounds_init(gt, wal);
else if (GRAPHICS_VER(i915) == 12)
@@ -2232,8 +2155,6 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
pvc_whitelist_build(engine);
else if (IS_DG2(i915))
dg2_whitelist_build(engine);
- else if (IS_XEHPSDV(i915))
- ; /* none needed */
else if (GRAPHICS_VER(i915) == 12)
tgl_whitelist_build(engine);
else if (GRAPHICS_VER(i915) == 11)
@@ -2969,22 +2890,6 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
0 /* write-only, so skip validation */,
true);
}
-
- if (IS_XEHPSDV(i915)) {
- /* Wa_1409954639 */
- wa_mcr_masked_en(wal,
- GEN8_ROW_CHICKEN,
- SYSTOLIC_DOP_CLOCK_GATING_DIS);
-
- /* Wa_1607196519 */
- wa_mcr_masked_en(wal,
- GEN9_ROW_CHICKEN4,
- GEN12_DISABLE_GRF_CLEAR);
-
- /* Wa_14010449647:xehpsdv */
- wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
- GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
- }
}
static void
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 6dfe5d9456c69..28277321d9ca9 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -51,8 +51,8 @@ static void uc_expand_default_options(struct intel_uc *uc)
/* Default: enable HuC authentication and GuC submission */
i915->params.enable_guc = ENABLE_GUC_LOAD_HUC | ENABLE_GUC_SUBMISSION;
- /* XEHPSDV and PVC do not use HuC */
- if (IS_XEHPSDV(i915) || IS_PONTEVECCHIO(i915))
+ /* PVC does not use HuC */
+ if (IS_PONTEVECCHIO(i915))
i915->params.enable_guc &= ~ENABLE_GUC_LOAD_HUC;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e81b3b2858acc..dff056587459f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -544,7 +544,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_DG1(i915) IS_PLATFORM(i915, INTEL_DG1)
#define IS_ALDERLAKE_S(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_S)
#define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P)
-#define IS_XEHPSDV(i915) IS_PLATFORM(i915, INTEL_XEHPSDV)
#define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2)
#define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO)
#define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)
@@ -621,9 +620,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_TIGERLAKE_UY(i915) \
IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
-#define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
- (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
-
#define IS_PVC_BD_STEP(__i915, since, until) \
(IS_PONTEVECCHIO(__i915) && \
IS_BASEDIE_STEP(__i915, since, until))
diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c
index b758fd110c204..c9169e56b9a18 100644
--- a/drivers/gpu/drm/i915/i915_hwmon.c
+++ b/drivers/gpu/drm/i915/i915_hwmon.c
@@ -739,12 +739,6 @@ hwm_get_preregistration_info(struct drm_i915_private *i915)
hwmon->rg.pkg_rapl_limit = PCU_PACKAGE_RAPL_LIMIT;
hwmon->rg.energy_status_all = PCU_PACKAGE_ENERGY_STATUS;
hwmon->rg.energy_status_tile = INVALID_MMIO_REG;
- } else if (IS_XEHPSDV(i915)) {
- hwmon->rg.pkg_power_sku_unit = GT0_PACKAGE_POWER_SKU_UNIT;
- hwmon->rg.pkg_power_sku = INVALID_MMIO_REG;
- hwmon->rg.pkg_rapl_limit = GT0_PACKAGE_RAPL_LIMIT;
- hwmon->rg.energy_status_all = GT0_PLATFORM_ENERGY_STATUS;
- hwmon->rg.energy_status_tile = GT0_PACKAGE_ENERGY_STATUS;
} else {
hwmon->rg.pkg_power_sku_unit = INVALID_MMIO_REG;
hwmon->rg.pkg_power_sku = INVALID_MMIO_REG;
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 8b4fdeabb12a5..b318b7c6bf737 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -734,23 +734,6 @@ static const struct intel_device_info adl_p_info = {
.__runtime.media.ip.ver = 12, \
.__runtime.media.ip.rel = 50
-__maybe_unused
-static const struct intel_device_info xehpsdv_info = {
- XE_HP_FEATURES,
- XE_HPM_FEATURES,
- DGFX_FEATURES,
- PLATFORM(INTEL_XEHPSDV),
- .has_64k_pages = 1,
- .has_media_ratio_mode = 1,
- .platform_engine_mask =
- BIT(RCS0) | BIT(BCS0) |
- BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
- BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) |
- BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7) |
- BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
- .require_force_probe = 1,
-};
-
#define DG2_FEATURES \
XE_HP_FEATURES, \
XE_HPM_FEATURES, \
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index bd9d812b1afa7..9052889dc0dc8 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2881,11 +2881,11 @@ gen12_enable_metric_set(struct i915_perf_stream *stream,
int ret;
/*
- * Wa_1508761755:xehpsdv, dg2
+ * Wa_1508761755
* EU NOA signals behave incorrectly if EU clock gating is enabled.
* Disable thread stall DOP gating and EU DOP gating.
*/
- if (IS_XEHPSDV(i915) || IS_DG2(i915)) {
+ if (IS_DG2(i915)) {
intel_gt_mcr_multicast_write(uncore->gt, GEN8_ROW_CHICKEN,
_MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
intel_uncore_write(uncore, GEN7_ROW_CHICKEN2,
@@ -2911,7 +2911,7 @@ gen12_enable_metric_set(struct i915_perf_stream *stream,
/*
* Initialize Super Queue Internal Cnt Register
* Set PMON Enable in order to collect valid metrics.
- * Enable byets per clock reporting in OA for XEHPSDV onward.
+ * Enable bytes per clock reporting in OA.
*/
sqcnt1 = GEN12_SQCNT1_PMON_ENABLE |
(HAS_OA_BPC_REPORTING(i915) ? GEN12_SQCNT1_OABPC : 0);
@@ -2971,10 +2971,9 @@ static void gen12_disable_metric_set(struct i915_perf_stream *stream)
u32 sqcnt1;
/*
- * Wa_1508761755:xehpsdv, dg2
- * Enable thread stall DOP gating and EU DOP gating.
+ * Wa_1508761755: Enable thread stall DOP gating and EU DOP gating.
*/
- if (IS_XEHPSDV(i915) || IS_DG2(i915)) {
+ if (IS_DG2(i915)) {
intel_gt_mcr_multicast_write(uncore->gt, GEN8_ROW_CHICKEN,
_MASKED_BIT_DISABLE(STALL_DOP_GATING_DISABLE));
intel_uncore_write(uncore, GEN7_ROW_CHICKEN2,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d6193c858a74f..7a84eb31818cc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1750,7 +1750,6 @@
#define BXT_RP_STATE_CAP _MMIO(0x138170)
#define GEN9_RP_STATE_LIMITS _MMIO(0x138148)
-#define XEHPSDV_RP_STATE_CAP _MMIO(0x250014)
#define PVC_RP_STATE_CAP _MMIO(0x281014)
#define MTL_RP_STATE_CAP _MMIO(0x138000)
@@ -5401,7 +5400,7 @@
#define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */
#define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
-#define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* xehpsdv, pvc */
+#define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* pvc */
/* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
#define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0
#define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index 39f23288e8a80..e34e1aabe6f86 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -343,13 +343,6 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *i915,
intel_uncore_write(&i915->uncore, GEN7_MISCCPCTL, misccpctl);
}
-static void xehpsdv_init_clock_gating(struct drm_i915_private *i915)
-{
- /* Wa_22010146351:xehpsdv */
- if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
- intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0, SGR_DIS);
-}
-
static void dg2_init_clock_gating(struct drm_i915_private *i915)
{
/* Wa_22010954014:dg2 */
@@ -731,7 +724,6 @@ static const struct drm_i915_clock_gating_funcs platform##_clock_gating_funcs =
CG_FUNCS(pvc);
CG_FUNCS(dg2);
-CG_FUNCS(xehpsdv);
CG_FUNCS(cfl);
CG_FUNCS(skl);
CG_FUNCS(kbl);
@@ -768,8 +760,6 @@ void intel_clock_gating_hooks_init(struct drm_i915_private *i915)
i915->clock_gating_funcs = &pvc_clock_gating_funcs;
else if (IS_DG2(i915))
i915->clock_gating_funcs = &dg2_clock_gating_funcs;
- else if (IS_XEHPSDV(i915))
- i915->clock_gating_funcs = &xehpsdv_clock_gating_funcs;
else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
i915->clock_gating_funcs = &cfl_clock_gating_funcs;
else if (IS_SKYLAKE(i915))
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 59bea1398c911..de28cbe758f7e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -70,7 +70,6 @@ static const char * const platform_names[] = {
PLATFORM_NAME(DG1),
PLATFORM_NAME(ALDERLAKE_S),
PLATFORM_NAME(ALDERLAKE_P),
- PLATFORM_NAME(XEHPSDV),
PLATFORM_NAME(DG2),
PLATFORM_NAME(PONTEVECCHIO),
PLATFORM_NAME(METEORLAKE),
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index eba2f0b919c87..2299327e59f0a 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -87,7 +87,6 @@ enum intel_platform {
INTEL_DG1,
INTEL_ALDERLAKE_S,
INTEL_ALDERLAKE_P,
- INTEL_XEHPSDV,
INTEL_DG2,
INTEL_PONTEVECCHIO,
INTEL_METEORLAKE,
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index b4162f1be7651..d524bfe17c270 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -102,13 +102,6 @@ static const struct intel_step_info adlp_revids[] = {
[0xC] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_D0 },
};
-static const struct intel_step_info xehpsdv_revids[] = {
- [0x0] = { COMMON_GT_MEDIA_STEP(A0) },
- [0x1] = { COMMON_GT_MEDIA_STEP(A1) },
- [0x4] = { COMMON_GT_MEDIA_STEP(B0) },
- [0x8] = { COMMON_GT_MEDIA_STEP(C0) },
-};
-
static const struct intel_step_info dg2_g10_revid_step_tbl[] = {
[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_A0 },
[0x1] = { COMMON_GT_MEDIA_STEP(A1), .display_step = STEP_A0 },
@@ -190,9 +183,6 @@ void intel_step_init(struct drm_i915_private *i915)
} else if (IS_DG2_G12(i915)) {
revids = dg2_g12_revid_step_tbl;
size = ARRAY_SIZE(dg2_g12_revid_step_tbl);
- } else if (IS_XEHPSDV(i915)) {
- revids = xehpsdv_revids;
- size = ARRAY_SIZE(xehpsdv_revids);
} else if (IS_ALDERLAKE_P_N(i915)) {
revids = adlp_n_revids;
size = ARRAY_SIZE(adlp_n_revids);
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 76400e9c40f05..7695bb946fff4 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1533,21 +1533,16 @@ static const struct intel_forcewake_range __gen12_fw_ranges[] = {
0x12000 - 0x127ff: always on \
0x12800 - 0x12fff: reserved */ \
GEN_FW_RANGE(0x13000, 0x131ff, FORCEWAKE_MEDIA_VDBOX0), /* DG2 only */ \
- GEN_FW_RANGE(0x13200, 0x13fff, FORCEWAKE_MEDIA_VDBOX2), /* \
+ GEN_FW_RANGE(0x13200, 0x147ff, FORCEWAKE_MEDIA_VDBOX2), /* \
0x13200 - 0x133ff: VD2 (DG2 only) \
- 0x13400 - 0x13fff: reserved */ \
- GEN_FW_RANGE(0x14000, 0x141ff, FORCEWAKE_MEDIA_VDBOX0), /* XEHPSDV only */ \
- GEN_FW_RANGE(0x14200, 0x143ff, FORCEWAKE_MEDIA_VDBOX2), /* XEHPSDV only */ \
- GEN_FW_RANGE(0x14400, 0x145ff, FORCEWAKE_MEDIA_VDBOX4), /* XEHPSDV only */ \
- GEN_FW_RANGE(0x14600, 0x147ff, FORCEWAKE_MEDIA_VDBOX6), /* XEHPSDV only */ \
+ 0x13400 - 0x147ff: reserved */ \
GEN_FW_RANGE(0x14800, 0x14fff, FORCEWAKE_RENDER), \
GEN_FW_RANGE(0x15000, 0x16dff, FORCEWAKE_GT), /* \
0x15000 - 0x15fff: gt (DG2 only) \
0x16000 - 0x16dff: reserved */ \
- GEN_FW_RANGE(0x16e00, 0x1ffff, FORCEWAKE_RENDER), \
- GEN_FW_RANGE(0x20000, 0x21fff, FORCEWAKE_MEDIA_VDBOX0), /* \
- 0x20000 - 0x20fff: VD0 (XEHPSDV only) \
- 0x21000 - 0x21fff: reserved */ \
+ GEN_FW_RANGE(0x16e00, 0x21fff, FORCEWAKE_RENDER), /* \
+ 0x16e00 - 0x1ffff: render \
+ 0x20000 - 0x21fff: reserved */ \
GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT), \
GEN_FW_RANGE(0x24000, 0x2417f, 0), /* \
0x24000 - 0x2407f: always on \
@@ -1627,10 +1622,6 @@ static const struct intel_forcewake_range __gen12_fw_ranges[] = {
0x1f6e00 - 0x1f7fff: reserved */ \
GEN_FW_RANGE(0x1f8000, 0x1fa0ff, FORCEWAKE_MEDIA_VEBOX3),
-static const struct intel_forcewake_range __xehp_fw_ranges[] = {
- XEHP_FWRANGES(FORCEWAKE_GT)
-};
-
static const struct intel_forcewake_range __dg2_fw_ranges[] = {
XEHP_FWRANGES(FORCEWAKE_RENDER)
};
@@ -2584,10 +2575,6 @@ static int uncore_forcewake_init(struct intel_uncore *uncore)
ASSIGN_FW_DOMAINS_TABLE(uncore, __dg2_fw_ranges);
ASSIGN_SHADOW_TABLE(uncore, dg2_shadowed_regs);
ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
- } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
- ASSIGN_FW_DOMAINS_TABLE(uncore, __xehp_fw_ranges);
- ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs);
- ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
} else if (GRAPHICS_VER(i915) >= 12) {
ASSIGN_FW_DOMAINS_TABLE(uncore, __gen12_fw_ranges);
ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs);
diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c
index 4f98aa8a861ea..502bcadc5f396 100644
--- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
+++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
@@ -119,7 +119,6 @@ int intel_uncore_mock_selftests(void)
{ __gen9_fw_ranges, ARRAY_SIZE(__gen9_fw_ranges), true },
{ __gen11_fw_ranges, ARRAY_SIZE(__gen11_fw_ranges), true },
{ __gen12_fw_ranges, ARRAY_SIZE(__gen12_fw_ranges), true },
- { __xehp_fw_ranges, ARRAY_SIZE(__xehp_fw_ranges), true },
{ __pvc_fw_ranges, ARRAY_SIZE(__pvc_fw_ranges), true },
{ __mtl_fw_ranges, ARRAY_SIZE(__mtl_fw_ranges), true },
{ __xelpmp_fw_ranges, ARRAY_SIZE(__xelpmp_fw_ranges), true },
--git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
index fef969112b1dc..a7e7ec3b5db92 100644
--- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
+++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
@@ -85,7 +85,6 @@ static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
#define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, XE_DG1)
#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, XE_ALDERLAKE_S)
#define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, XE_ALDERLAKE_P)
-#define IS_XEHPSDV(dev_priv) (dev_priv && 0)
#define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, XE_DG2)
#define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, XE_PVC)
#define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_METEORLAKE)
@@ -130,7 +129,6 @@ static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
#define IS_DG2_GRAPHICS_STEP(xe, variant, first, last) \
((xe)->info.subplatform == XE_SUBPLATFORM_DG2_ ## variant && \
IS_GRAPHICS_STEP(xe, first, last))
-#define IS_XEHPSDV_GRAPHICS_STEP(xe, first, last) (IS_XEHPSDV(xe) && IS_GRAPHICS_STEP(xe, first, last))
/* XXX: No basedie stepping support yet */
#define IS_PVC_BD_STEP(xe, first, last) (!WARN_ON(1) && IS_PONTEVECCHIO(xe))
--
2.43.0
^ permalink raw reply related [flat|nested] 15+ messages in thread* [CI 2/6] drm/i915: Remove XEHP_FWRANGES()
2024-03-20 6:02 [CI 0/6] drm/i915: cleanup dead code Lucas De Marchi
2024-03-20 6:02 ` [CI 1/6] drm/i915: Drop dead code for xehpsdv Lucas De Marchi
@ 2024-03-20 6:02 ` Lucas De Marchi
2024-03-20 6:03 ` [CI 3/6] drm/i915: Stop inheriting IP_VER(12, 50) Lucas De Marchi
` (9 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Lucas De Marchi @ 2024-03-20 6:02 UTC (permalink / raw)
To: intel-gfx
Now that DG2 is the only user of this forcewake table, remove the macro
and use FORCEWAKE_RENDER explicitly for range 0xd800 - 0xd87f.
Suggested-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 297 ++++++++++++++--------------
1 file changed, 145 insertions(+), 152 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 7695bb946fff4..b525318dbd53b 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1471,159 +1471,152 @@ static const struct intel_forcewake_range __gen12_fw_ranges[] = {
0x1d3f00 - 0x1d3fff: VD2 */
};
-/*
- * Graphics IP version 12.55 brings a slight change to the 0xd800 range,
- * switching it from the GT domain to the render domain.
- */
-#define XEHP_FWRANGES(FW_RANGE_D800) \
- GEN_FW_RANGE(0x0, 0x1fff, 0), /* \
- 0x0 - 0xaff: reserved \
- 0xb00 - 0x1fff: always on */ \
- GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), \
- GEN_FW_RANGE(0x2700, 0x4aff, FORCEWAKE_GT), \
- GEN_FW_RANGE(0x4b00, 0x51ff, 0), /* \
- 0x4b00 - 0x4fff: reserved \
- 0x5000 - 0x51ff: always on */ \
- GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), \
- GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT), \
- GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), \
- GEN_FW_RANGE(0x8160, 0x81ff, 0), /* \
- 0x8160 - 0x817f: reserved \
- 0x8180 - 0x81ff: always on */ \
- GEN_FW_RANGE(0x8200, 0x82ff, FORCEWAKE_GT), \
- GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), \
- GEN_FW_RANGE(0x8500, 0x8cff, FORCEWAKE_GT), /* \
- 0x8500 - 0x87ff: gt \
- 0x8800 - 0x8c7f: reserved \
- 0x8c80 - 0x8cff: gt (DG2 only) */ \
- GEN_FW_RANGE(0x8d00, 0x8fff, FORCEWAKE_RENDER), /* \
- 0x8d00 - 0x8dff: render (DG2 only) \
- 0x8e00 - 0x8fff: reserved */ \
- GEN_FW_RANGE(0x9000, 0x94cf, FORCEWAKE_GT), /* \
- 0x9000 - 0x947f: gt \
- 0x9480 - 0x94cf: reserved */ \
- GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER), \
- GEN_FW_RANGE(0x9560, 0x967f, 0), /* \
- 0x9560 - 0x95ff: always on \
- 0x9600 - 0x967f: reserved */ \
- GEN_FW_RANGE(0x9680, 0x97ff, FORCEWAKE_RENDER), /* \
- 0x9680 - 0x96ff: render (DG2 only) \
- 0x9700 - 0x97ff: reserved */ \
- GEN_FW_RANGE(0x9800, 0xcfff, FORCEWAKE_GT), /* \
- 0x9800 - 0xb4ff: gt \
- 0xb500 - 0xbfff: reserved \
- 0xc000 - 0xcfff: gt */ \
- GEN_FW_RANGE(0xd000, 0xd7ff, 0), \
- GEN_FW_RANGE(0xd800, 0xd87f, FW_RANGE_D800), \
- GEN_FW_RANGE(0xd880, 0xdbff, FORCEWAKE_GT), \
- GEN_FW_RANGE(0xdc00, 0xdcff, FORCEWAKE_RENDER), \
- GEN_FW_RANGE(0xdd00, 0xde7f, FORCEWAKE_GT), /* \
- 0xdd00 - 0xddff: gt \
- 0xde00 - 0xde7f: reserved */ \
- GEN_FW_RANGE(0xde80, 0xe8ff, FORCEWAKE_RENDER), /* \
- 0xde80 - 0xdfff: render \
- 0xe000 - 0xe0ff: reserved \
- 0xe100 - 0xe8ff: render */ \
- GEN_FW_RANGE(0xe900, 0xffff, FORCEWAKE_GT), /* \
- 0xe900 - 0xe9ff: gt \
- 0xea00 - 0xefff: reserved \
- 0xf000 - 0xffff: gt */ \
- GEN_FW_RANGE(0x10000, 0x12fff, 0), /* \
- 0x10000 - 0x11fff: reserved \
- 0x12000 - 0x127ff: always on \
- 0x12800 - 0x12fff: reserved */ \
- GEN_FW_RANGE(0x13000, 0x131ff, FORCEWAKE_MEDIA_VDBOX0), /* DG2 only */ \
- GEN_FW_RANGE(0x13200, 0x147ff, FORCEWAKE_MEDIA_VDBOX2), /* \
- 0x13200 - 0x133ff: VD2 (DG2 only) \
- 0x13400 - 0x147ff: reserved */ \
- GEN_FW_RANGE(0x14800, 0x14fff, FORCEWAKE_RENDER), \
- GEN_FW_RANGE(0x15000, 0x16dff, FORCEWAKE_GT), /* \
- 0x15000 - 0x15fff: gt (DG2 only) \
- 0x16000 - 0x16dff: reserved */ \
- GEN_FW_RANGE(0x16e00, 0x21fff, FORCEWAKE_RENDER), /* \
- 0x16e00 - 0x1ffff: render \
- 0x20000 - 0x21fff: reserved */ \
- GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT), \
- GEN_FW_RANGE(0x24000, 0x2417f, 0), /* \
- 0x24000 - 0x2407f: always on \
- 0x24080 - 0x2417f: reserved */ \
- GEN_FW_RANGE(0x24180, 0x249ff, FORCEWAKE_GT), /* \
- 0x24180 - 0x241ff: gt \
- 0x24200 - 0x249ff: reserved */ \
- GEN_FW_RANGE(0x24a00, 0x251ff, FORCEWAKE_RENDER), /* \
- 0x24a00 - 0x24a7f: render \
- 0x24a80 - 0x251ff: reserved */ \
- GEN_FW_RANGE(0x25200, 0x25fff, FORCEWAKE_GT), /* \
- 0x25200 - 0x252ff: gt \
- 0x25300 - 0x25fff: reserved */ \
- GEN_FW_RANGE(0x26000, 0x2ffff, FORCEWAKE_RENDER), /* \
- 0x26000 - 0x27fff: render \
- 0x28000 - 0x29fff: reserved \
- 0x2a000 - 0x2ffff: undocumented */ \
- GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_GT), \
- GEN_FW_RANGE(0x40000, 0x1bffff, 0), \
- GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /* \
- 0x1c0000 - 0x1c2bff: VD0 \
- 0x1c2c00 - 0x1c2cff: reserved \
- 0x1c2d00 - 0x1c2dff: VD0 \
- 0x1c2e00 - 0x1c3eff: VD0 (DG2 only) \
- 0x1c3f00 - 0x1c3fff: VD0 */ \
- GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1), /* \
- 0x1c4000 - 0x1c6bff: VD1 \
- 0x1c6c00 - 0x1c6cff: reserved \
- 0x1c6d00 - 0x1c6dff: VD1 \
- 0x1c6e00 - 0x1c7fff: reserved */ \
- GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), /* \
- 0x1c8000 - 0x1ca0ff: VE0 \
- 0x1ca100 - 0x1cbfff: reserved */ \
- GEN_FW_RANGE(0x1cc000, 0x1ccfff, FORCEWAKE_MEDIA_VDBOX0), \
- GEN_FW_RANGE(0x1cd000, 0x1cdfff, FORCEWAKE_MEDIA_VDBOX2), \
- GEN_FW_RANGE(0x1ce000, 0x1cefff, FORCEWAKE_MEDIA_VDBOX4), \
- GEN_FW_RANGE(0x1cf000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX6), \
- GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), /* \
- 0x1d0000 - 0x1d2bff: VD2 \
- 0x1d2c00 - 0x1d2cff: reserved \
- 0x1d2d00 - 0x1d2dff: VD2 \
- 0x1d2e00 - 0x1d3dff: VD2 (DG2 only) \
- 0x1d3e00 - 0x1d3eff: reserved \
- 0x1d3f00 - 0x1d3fff: VD2 */ \
- GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3), /* \
- 0x1d4000 - 0x1d6bff: VD3 \
- 0x1d6c00 - 0x1d6cff: reserved \
- 0x1d6d00 - 0x1d6dff: VD3 \
- 0x1d6e00 - 0x1d7fff: reserved */ \
- GEN_FW_RANGE(0x1d8000, 0x1dffff, FORCEWAKE_MEDIA_VEBOX1), /* \
- 0x1d8000 - 0x1da0ff: VE1 \
- 0x1da100 - 0x1dffff: reserved */ \
- GEN_FW_RANGE(0x1e0000, 0x1e3fff, FORCEWAKE_MEDIA_VDBOX4), /* \
- 0x1e0000 - 0x1e2bff: VD4 \
- 0x1e2c00 - 0x1e2cff: reserved \
- 0x1e2d00 - 0x1e2dff: VD4 \
- 0x1e2e00 - 0x1e3eff: reserved \
- 0x1e3f00 - 0x1e3fff: VD4 */ \
- GEN_FW_RANGE(0x1e4000, 0x1e7fff, FORCEWAKE_MEDIA_VDBOX5), /* \
- 0x1e4000 - 0x1e6bff: VD5 \
- 0x1e6c00 - 0x1e6cff: reserved \
- 0x1e6d00 - 0x1e6dff: VD5 \
- 0x1e6e00 - 0x1e7fff: reserved */ \
- GEN_FW_RANGE(0x1e8000, 0x1effff, FORCEWAKE_MEDIA_VEBOX2), /* \
- 0x1e8000 - 0x1ea0ff: VE2 \
- 0x1ea100 - 0x1effff: reserved */ \
- GEN_FW_RANGE(0x1f0000, 0x1f3fff, FORCEWAKE_MEDIA_VDBOX6), /* \
- 0x1f0000 - 0x1f2bff: VD6 \
- 0x1f2c00 - 0x1f2cff: reserved \
- 0x1f2d00 - 0x1f2dff: VD6 \
- 0x1f2e00 - 0x1f3eff: reserved \
- 0x1f3f00 - 0x1f3fff: VD6 */ \
- GEN_FW_RANGE(0x1f4000, 0x1f7fff, FORCEWAKE_MEDIA_VDBOX7), /* \
- 0x1f4000 - 0x1f6bff: VD7 \
- 0x1f6c00 - 0x1f6cff: reserved \
- 0x1f6d00 - 0x1f6dff: VD7 \
- 0x1f6e00 - 0x1f7fff: reserved */ \
- GEN_FW_RANGE(0x1f8000, 0x1fa0ff, FORCEWAKE_MEDIA_VEBOX3),
-
static const struct intel_forcewake_range __dg2_fw_ranges[] = {
- XEHP_FWRANGES(FORCEWAKE_RENDER)
+ GEN_FW_RANGE(0x0, 0x1fff, 0), /*
+ 0x0 - 0xaff: reserved
+ 0xb00 - 0x1fff: always on */
+ GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x2700, 0x4aff, FORCEWAKE_GT),
+ GEN_FW_RANGE(0x4b00, 0x51ff, 0), /*
+ 0x4b00 - 0x4fff: reserved
+ 0x5000 - 0x51ff: always on */
+ GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT),
+ GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x8160, 0x81ff, 0), /*
+ 0x8160 - 0x817f: reserved
+ 0x8180 - 0x81ff: always on */
+ GEN_FW_RANGE(0x8200, 0x82ff, FORCEWAKE_GT),
+ GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x8500, 0x8cff, FORCEWAKE_GT), /*
+ 0x8500 - 0x87ff: gt
+ 0x8800 - 0x8c7f: reserved
+ 0x8c80 - 0x8cff: gt (DG2 only) */
+ GEN_FW_RANGE(0x8d00, 0x8fff, FORCEWAKE_RENDER), /*
+ 0x8d00 - 0x8dff: render (DG2 only)
+ 0x8e00 - 0x8fff: reserved */
+ GEN_FW_RANGE(0x9000, 0x94cf, FORCEWAKE_GT), /*
+ 0x9000 - 0x947f: gt
+ 0x9480 - 0x94cf: reserved */
+ GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x9560, 0x967f, 0), /*
+ 0x9560 - 0x95ff: always on
+ 0x9600 - 0x967f: reserved */
+ GEN_FW_RANGE(0x9680, 0x97ff, FORCEWAKE_RENDER), /*
+ 0x9680 - 0x96ff: render
+ 0x9700 - 0x97ff: reserved */
+ GEN_FW_RANGE(0x9800, 0xcfff, FORCEWAKE_GT), /*
+ 0x9800 - 0xb4ff: gt
+ 0xb500 - 0xbfff: reserved
+ 0xc000 - 0xcfff: gt */
+ GEN_FW_RANGE(0xd000, 0xd7ff, 0),
+ GEN_FW_RANGE(0xd800, 0xd87f, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0xd880, 0xdbff, FORCEWAKE_GT),
+ GEN_FW_RANGE(0xdc00, 0xdcff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0xdd00, 0xde7f, FORCEWAKE_GT), /*
+ 0xdd00 - 0xddff: gt
+ 0xde00 - 0xde7f: reserved */
+ GEN_FW_RANGE(0xde80, 0xe8ff, FORCEWAKE_RENDER), /*
+ 0xde80 - 0xdfff: render
+ 0xe000 - 0xe0ff: reserved
+ 0xe100 - 0xe8ff: render */
+ GEN_FW_RANGE(0xe900, 0xffff, FORCEWAKE_GT), /*
+ 0xe900 - 0xe9ff: gt
+ 0xea00 - 0xefff: reserved
+ 0xf000 - 0xffff: gt */
+ GEN_FW_RANGE(0x10000, 0x12fff, 0), /*
+ 0x10000 - 0x11fff: reserved
+ 0x12000 - 0x127ff: always on
+ 0x12800 - 0x12fff: reserved */
+ GEN_FW_RANGE(0x13000, 0x131ff, FORCEWAKE_MEDIA_VDBOX0),
+ GEN_FW_RANGE(0x13200, 0x147ff, FORCEWAKE_MEDIA_VDBOX2), /*
+ 0x13200 - 0x133ff: VD2 (DG2 only)
+ 0x13400 - 0x147ff: reserved */
+ GEN_FW_RANGE(0x14800, 0x14fff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x15000, 0x16dff, FORCEWAKE_GT), /*
+ 0x15000 - 0x15fff: gt (DG2 only)
+ 0x16000 - 0x16dff: reserved */
+ GEN_FW_RANGE(0x16e00, 0x21fff, FORCEWAKE_RENDER), /*
+ 0x16e00 - 0x1ffff: render
+ 0x20000 - 0x21fff: reserved */
+ GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT),
+ GEN_FW_RANGE(0x24000, 0x2417f, 0), /*
+ 0x24000 - 0x2407f: always on
+ 0x24080 - 0x2417f: reserved */
+ GEN_FW_RANGE(0x24180, 0x249ff, FORCEWAKE_GT), /*
+ 0x24180 - 0x241ff: gt
+ 0x24200 - 0x249ff: reserved */
+ GEN_FW_RANGE(0x24a00, 0x251ff, FORCEWAKE_RENDER), /*
+ 0x24a00 - 0x24a7f: render
+ 0x24a80 - 0x251ff: reserved */
+ GEN_FW_RANGE(0x25200, 0x25fff, FORCEWAKE_GT), /*
+ 0x25200 - 0x252ff: gt
+ 0x25300 - 0x25fff: reserved */
+ GEN_FW_RANGE(0x26000, 0x2ffff, FORCEWAKE_RENDER), /*
+ 0x26000 - 0x27fff: render
+ 0x28000 - 0x29fff: reserved
+ 0x2a000 - 0x2ffff: undocumented */
+ GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_GT),
+ GEN_FW_RANGE(0x40000, 0x1bffff, 0),
+ GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /*
+ 0x1c0000 - 0x1c2bff: VD0
+ 0x1c2c00 - 0x1c2cff: reserved
+ 0x1c2d00 - 0x1c2dff: VD0
+ 0x1c2e00 - 0x1c3eff: VD0
+ 0x1c3f00 - 0x1c3fff: VD0 */
+ GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1), /*
+ 0x1c4000 - 0x1c6bff: VD1
+ 0x1c6c00 - 0x1c6cff: reserved
+ 0x1c6d00 - 0x1c6dff: VD1
+ 0x1c6e00 - 0x1c7fff: reserved */
+ GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), /*
+ 0x1c8000 - 0x1ca0ff: VE0
+ 0x1ca100 - 0x1cbfff: reserved */
+ GEN_FW_RANGE(0x1cc000, 0x1ccfff, FORCEWAKE_MEDIA_VDBOX0),
+ GEN_FW_RANGE(0x1cd000, 0x1cdfff, FORCEWAKE_MEDIA_VDBOX2),
+ GEN_FW_RANGE(0x1ce000, 0x1cefff, FORCEWAKE_MEDIA_VDBOX4),
+ GEN_FW_RANGE(0x1cf000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX6),
+ GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), /*
+ 0x1d0000 - 0x1d2bff: VD2
+ 0x1d2c00 - 0x1d2cff: reserved
+ 0x1d2d00 - 0x1d2dff: VD2
+ 0x1d2e00 - 0x1d3dff: VD2
+ 0x1d3e00 - 0x1d3eff: reserved
+ 0x1d3f00 - 0x1d3fff: VD2 */
+ GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3), /*
+ 0x1d4000 - 0x1d6bff: VD3
+ 0x1d6c00 - 0x1d6cff: reserved
+ 0x1d6d00 - 0x1d6dff: VD3
+ 0x1d6e00 - 0x1d7fff: reserved */
+ GEN_FW_RANGE(0x1d8000, 0x1dffff, FORCEWAKE_MEDIA_VEBOX1), /*
+ 0x1d8000 - 0x1da0ff: VE1
+ 0x1da100 - 0x1dffff: reserved */
+ GEN_FW_RANGE(0x1e0000, 0x1e3fff, FORCEWAKE_MEDIA_VDBOX4), /*
+ 0x1e0000 - 0x1e2bff: VD4
+ 0x1e2c00 - 0x1e2cff: reserved
+ 0x1e2d00 - 0x1e2dff: VD4
+ 0x1e2e00 - 0x1e3eff: reserved
+ 0x1e3f00 - 0x1e3fff: VD4 */
+ GEN_FW_RANGE(0x1e4000, 0x1e7fff, FORCEWAKE_MEDIA_VDBOX5), /*
+ 0x1e4000 - 0x1e6bff: VD5
+ 0x1e6c00 - 0x1e6cff: reserved
+ 0x1e6d00 - 0x1e6dff: VD5
+ 0x1e6e00 - 0x1e7fff: reserved */
+ GEN_FW_RANGE(0x1e8000, 0x1effff, FORCEWAKE_MEDIA_VEBOX2), /*
+ 0x1e8000 - 0x1ea0ff: VE2
+ 0x1ea100 - 0x1effff: reserved */
+ GEN_FW_RANGE(0x1f0000, 0x1f3fff, FORCEWAKE_MEDIA_VDBOX6), /*
+ 0x1f0000 - 0x1f2bff: VD6
+ 0x1f2c00 - 0x1f2cff: reserved
+ 0x1f2d00 - 0x1f2dff: VD6
+ 0x1f2e00 - 0x1f3eff: reserved
+ 0x1f3f00 - 0x1f3fff: VD6 */
+ GEN_FW_RANGE(0x1f4000, 0x1f7fff, FORCEWAKE_MEDIA_VDBOX7), /*
+ 0x1f4000 - 0x1f6bff: VD7
+ 0x1f6c00 - 0x1f6cff: reserved
+ 0x1f6d00 - 0x1f6dff: VD7
+ 0x1f6e00 - 0x1f7fff: reserved */
+ GEN_FW_RANGE(0x1f8000, 0x1fa0ff, FORCEWAKE_MEDIA_VEBOX3),
};
static const struct intel_forcewake_range __pvc_fw_ranges[] = {
--
2.43.0
^ permalink raw reply related [flat|nested] 15+ messages in thread* [CI 3/6] drm/i915: Stop inheriting IP_VER(12, 50)
2024-03-20 6:02 [CI 0/6] drm/i915: cleanup dead code Lucas De Marchi
2024-03-20 6:02 ` [CI 1/6] drm/i915: Drop dead code for xehpsdv Lucas De Marchi
2024-03-20 6:02 ` [CI 2/6] drm/i915: Remove XEHP_FWRANGES() Lucas De Marchi
@ 2024-03-20 6:03 ` Lucas De Marchi
2024-03-20 6:03 ` [CI 4/6] drm/i915: Update " Lucas De Marchi
` (8 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Lucas De Marchi @ 2024-03-20 6:03 UTC (permalink / raw)
To: intel-gfx
All the platforms that inherit the media/graphics version
from XE_HPM_FEATURES / XE_HP_FEATURES just override it to another
version. Just set the version directly in the respective struct
and remove the versions from the _FEATURES macros. Since that was the
only use for XE_HPM_FEATURES, remove it completely.
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 12 ++++--------
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index b318b7c6bf737..8b673fdcf178f 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -705,8 +705,6 @@ static const struct intel_device_info adl_p_info = {
I915_GTT_PAGE_SIZE_2M
#define XE_HP_FEATURES \
- .__runtime.graphics.ip.ver = 12, \
- .__runtime.graphics.ip.rel = 50, \
XE_HP_PAGE_SIZES, \
TGL_CACHELEVEL, \
.dma_mask_size = 46, \
@@ -730,15 +728,12 @@ static const struct intel_device_info adl_p_info = {
.__runtime.ppgtt_size = 48, \
.__runtime.ppgtt_type = INTEL_PPGTT_FULL
-#define XE_HPM_FEATURES \
- .__runtime.media.ip.ver = 12, \
- .__runtime.media.ip.rel = 50
-
#define DG2_FEATURES \
XE_HP_FEATURES, \
- XE_HPM_FEATURES, \
DGFX_FEATURES, \
+ .__runtime.graphics.ip.ver = 12, \
.__runtime.graphics.ip.rel = 55, \
+ .__runtime.media.ip.ver = 12, \
.__runtime.media.ip.rel = 55, \
PLATFORM(INTEL_DG2), \
.has_64k_pages = 1, \
@@ -773,9 +768,10 @@ static const struct intel_device_info ats_m_info = {
__maybe_unused
static const struct intel_device_info pvc_info = {
XE_HPC_FEATURES,
- XE_HPM_FEATURES,
DGFX_FEATURES,
+ .__runtime.graphics.ip.ver = 12,
.__runtime.graphics.ip.rel = 60,
+ .__runtime.media.ip.ver = 12,
.__runtime.media.ip.rel = 60,
PLATFORM(INTEL_PONTEVECCHIO),
.has_flat_ccs = 0,
--
2.43.0
^ permalink raw reply related [flat|nested] 15+ messages in thread* [CI 4/6] drm/i915: Update IP_VER(12, 50)
2024-03-20 6:02 [CI 0/6] drm/i915: cleanup dead code Lucas De Marchi
` (2 preceding siblings ...)
2024-03-20 6:03 ` [CI 3/6] drm/i915: Stop inheriting IP_VER(12, 50) Lucas De Marchi
@ 2024-03-20 6:03 ` Lucas De Marchi
2024-03-20 6:03 ` [CI 5/6] drm/i915: Drop dead code for pvc Lucas De Marchi
` (7 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Lucas De Marchi @ 2024-03-20 6:03 UTC (permalink / raw)
To: intel-gfx
With no platform using graphics/media IP_VER(12, 50), replace the
checks throughout the code with IP_VER(12, 55) so the code makes sense
by itself with no additional explanation of previous baggage.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 4 ++--
.../gpu/drm/i915/gem/selftests/i915_gem_client_blt.c | 8 ++++----
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 5 ++---
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 10 +++++-----
drivers/gpu/drm/i915/gt/intel_gt.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_gt_mcr.h | 2 +-
drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 8 ++++----
drivers/gpu/drm/i915/gt/intel_migrate.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_sseu.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++--
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 4 ++--
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
drivers/gpu/drm/i915/i915_getparam.c | 4 ++--
drivers/gpu/drm/i915/i915_gpu_error.c | 5 ++---
drivers/gpu/drm/i915/i915_perf.c | 8 ++++----
drivers/gpu/drm/i915/i915_query.c | 2 +-
drivers/gpu/drm/i915/intel_uncore.c | 2 +-
23 files changed, 46 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index 3ff3d8889c6cc..edb54903be0a2 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -713,7 +713,7 @@ static int igt_ppgtt_huge_fill(void *arg)
{
struct drm_i915_private *i915 = arg;
unsigned int supported = RUNTIME_INFO(i915)->page_sizes;
- bool has_pte64 = GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50);
+ bool has_pte64 = GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55);
struct i915_address_space *vm;
struct i915_gem_context *ctx;
unsigned long max_pages;
@@ -857,7 +857,7 @@ static int igt_ppgtt_huge_fill(void *arg)
static int igt_ppgtt_64K(void *arg)
{
struct drm_i915_private *i915 = arg;
- bool has_pte64 = GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50);
+ bool has_pte64 = GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55);
struct drm_i915_gem_object *obj;
struct i915_address_space *vm;
struct i915_gem_context *ctx;
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
index 10a7847f1b049..bac15196b4d24 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -117,7 +117,7 @@ static bool fastblit_supports_x_tiling(const struct drm_i915_private *i915)
if (gen < 12)
return true;
- if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 55))
return false;
return HAS_DISPLAY(i915);
@@ -166,7 +166,7 @@ static int prepare_blit(const struct tiled_blits *t,
src_pitch = t->width; /* in dwords */
if (src->tiling == CLIENT_TILING_Y) {
src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR);
- if (GRAPHICS_VER_FULL(to_i915(batch->base.dev)) >= IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(to_i915(batch->base.dev)) >= IP_VER(12, 55))
src_4t = XY_FAST_COPY_BLT_D1_SRC_TILE4;
} else if (src->tiling == CLIENT_TILING_X) {
src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(TILE_X);
@@ -177,7 +177,7 @@ static int prepare_blit(const struct tiled_blits *t,
dst_pitch = t->width; /* in dwords */
if (dst->tiling == CLIENT_TILING_Y) {
dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR);
- if (GRAPHICS_VER_FULL(to_i915(batch->base.dev)) >= IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(to_i915(batch->base.dev)) >= IP_VER(12, 55))
dst_4t = XY_FAST_COPY_BLT_D1_DST_TILE4;
} else if (dst->tiling == CLIENT_TILING_X) {
dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(TILE_X);
@@ -365,7 +365,7 @@ static u64 tiled_offset(const struct intel_gt *gt,
v += x;
swizzle = gt->ggtt->bit_6_swizzle_x;
- } else if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50)) {
+ } else if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 55)) {
/* Y-major tiling layout is Tile4 for Xe_HP and beyond */
v = linear_x_y_to_ftiled_pos(x_pos, y_pos, stride, 32);
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 8cf58b29410bc..f59914df6b5a7 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -833,7 +833,7 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
cs = gen12_emit_pipe_control(cs, 0,
PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
- if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
+ if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 55))
/* Wa_1409600907 */
flags |= PIPE_CONTROL_DEPTH_STALL;
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index f553cf4e64490..75bde8c1aa5da 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -765,14 +765,14 @@ static void engine_mask_apply_media_fuses(struct intel_gt *gt)
* and bits have disable semantices.
*/
media_fuse = intel_uncore_read(gt->uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
- if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
+ if (MEDIA_VER_FULL(i915) < IP_VER(12, 55))
media_fuse = ~media_fuse;
vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
GEN11_GT_VEBOX_DISABLE_SHIFT;
- if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
+ if (MEDIA_VER_FULL(i915) >= IP_VER(12, 55)) {
fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1);
gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
} else {
@@ -1193,7 +1193,6 @@ static int intel_engine_init_tlb_invalidation(struct intel_engine_cs *engine)
if (GRAPHICS_VER_FULL(i915) == IP_VER(12, 74) ||
GRAPHICS_VER_FULL(i915) == IP_VER(12, 71) ||
GRAPHICS_VER_FULL(i915) == IP_VER(12, 70) ||
- GRAPHICS_VER_FULL(i915) == IP_VER(12, 50) ||
GRAPHICS_VER_FULL(i915) == IP_VER(12, 55)) {
regs = xehp_regs;
num = ARRAY_SIZE(xehp_regs);
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 42aade0faf2d1..4bc6c437e7f73 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -493,7 +493,7 @@ __execlists_schedule_in(struct i915_request *rq)
/* Use a fixed tag for OA and friends */
GEM_BUG_ON(ce->tag <= BITS_PER_LONG);
ce->lrc.ccid = ce->tag;
- } else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) {
+ } else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) {
/* We don't need a strict matching tag, just different values */
unsigned int tag = ffs(READ_ONCE(engine->context_tag));
@@ -613,7 +613,7 @@ static void __execlists_schedule_out(struct i915_request * const rq,
intel_engine_add_retire(engine, ce->timeline);
ccid = ce->lrc.ccid;
- if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) {
+ if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) {
ccid >>= XEHP_SW_CTX_ID_SHIFT - 32;
ccid &= XEHP_MAX_CONTEXT_HW_ID;
} else {
@@ -1907,7 +1907,7 @@ process_csb(struct intel_engine_cs *engine, struct i915_request **inactive)
ENGINE_TRACE(engine, "csb[%d]: status=0x%08x:0x%08x\n",
head, upper_32_bits(csb), lower_32_bits(csb));
- if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
promote = xehp_csb_parse(csb);
else if (GRAPHICS_VER(engine->i915) >= 12)
promote = gen12_csb_parse(csb);
@@ -3479,7 +3479,7 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
}
}
- if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) {
+ if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) {
if (intel_engine_has_preemption(engine))
engine->emit_bb_start = xehp_emit_bb_start;
else
@@ -3582,7 +3582,7 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine)
engine->context_tag = GENMASK(BITS_PER_LONG - 2, 0);
if (GRAPHICS_VER(engine->i915) >= 11 &&
- GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 50)) {
+ GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 55)) {
execlists->ccid |= engine->instance << (GEN11_ENGINE_INSTANCE_SHIFT - 32);
execlists->ccid |= engine->class << (GEN11_ENGINE_CLASS_SHIFT - 32);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index a425db5ed3a22..2c6d31b8fc1aa 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -278,7 +278,7 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
intel_uncore_posting_read(uncore,
XELPMP_RING_FAULT_REG);
- } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
+ } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
intel_gt_mcr_multicast_rmw(gt, XEHP_RING_FAULT_REG,
RING_FAULT_VALID, 0);
intel_gt_mcr_read_any(gt, XEHP_RING_FAULT_REG);
@@ -403,7 +403,7 @@ void intel_gt_check_and_clear_faults(struct intel_gt *gt)
struct drm_i915_private *i915 = gt->i915;
/* From GEN8 onwards we only have one 'All Engine Fault Register' */
- if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
xehp_check_faults(gt);
else if (GRAPHICS_VER(i915) >= 8)
gen8_check_faults(gt);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index 5a2bd8de155a8..29443bf7c06c9 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -184,7 +184,7 @@ void intel_gt_mcr_init(struct intel_gt *gt)
* steering.
*/
} else if (GRAPHICS_VER(i915) >= 11 &&
- GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) {
+ GRAPHICS_VER_FULL(i915) < IP_VER(12, 55)) {
gt->steering_table[L3BANK] = icl_l3bank_steering_table;
gt->info.l3bank_mask =
~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
@@ -829,7 +829,7 @@ void intel_gt_mcr_get_ss_steering(struct intel_gt *gt, unsigned int dss,
if (IS_PONTEVECCHIO(gt->i915)) {
*group = dss / GEN_DSS_PER_CSLICE;
*instance = dss % GEN_DSS_PER_CSLICE;
- } else if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50)) {
+ } else if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 55)) {
*group = dss / GEN_DSS_PER_GSLICE;
*instance = dss % GEN_DSS_PER_GSLICE;
} else {
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.h b/drivers/gpu/drm/i915/gt/intel_gt_mcr.h
index 01ac565a56a4a..a67a4c35a4faf 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.h
@@ -54,7 +54,7 @@ int intel_gt_mcr_wait_for_reg(struct intel_gt *gt,
* the topology, so we lookup the DSS ID directly in "slice 0."
*/
#define _HAS_SS(ss_, gt_, group_, instance_) ( \
- GRAPHICS_VER_FULL(gt_->i915) >= IP_VER(12, 50) ? \
+ GRAPHICS_VER_FULL(gt_->i915) >= IP_VER(12, 55) ? \
intel_sseu_has_subslice(&(gt_)->info.sseu, 0, ss_) : \
intel_sseu_has_subslice(&(gt_)->info.sseu, group_, instance_))
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 7811a8c9da067..30b128b1fde7c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -680,7 +680,7 @@ void setup_private_pat(struct intel_gt *gt)
if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
xelpg_setup_private_ppat(gt);
- else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+ else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
xehp_setup_private_ppat(gt);
else if (GRAPHICS_VER(i915) >= 12)
tgl_setup_private_ppat(uncore);
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 7f1b00cb9924c..b387146ede986 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -676,7 +676,7 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)
{
- if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
return 0x70;
else if (GRAPHICS_VER(engine->i915) >= 12)
return 0x60;
@@ -690,7 +690,7 @@ static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)
static int lrc_ring_bb_offset(const struct intel_engine_cs *engine)
{
- if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
return 0x80;
else if (GRAPHICS_VER(engine->i915) >= 12)
return 0x70;
@@ -705,7 +705,7 @@ static int lrc_ring_bb_offset(const struct intel_engine_cs *engine)
static int lrc_ring_gpr0(const struct intel_engine_cs *engine)
{
- if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
return 0x84;
else if (GRAPHICS_VER(engine->i915) >= 12)
return 0x74;
@@ -752,7 +752,7 @@ static int lrc_ring_indirect_offset(const struct intel_engine_cs *engine)
static int lrc_ring_cmd_buf_cctl(const struct intel_engine_cs *engine)
{
- if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
/*
* Note that the CSFE context has a dummy slot for CMD_BUF_CCTL
* simply to match the RCS context image layout.
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
index 86ba2f2e485c5..6f7af40771353 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -925,7 +925,7 @@ static int emit_clear(struct i915_request *rq, u32 offset, int size,
GEM_BUG_ON(size >> PAGE_SHIFT > S16_MAX);
- if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
ring_sz = XY_FAST_COLOR_BLT_DW;
else if (ver >= 8)
ring_sz = 8;
@@ -936,7 +936,7 @@ static int emit_clear(struct i915_request *rq, u32 offset, int size,
if (IS_ERR(cs))
return PTR_ERR(cs);
- if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
*cs++ = XY_FAST_COLOR_BLT_CMD | XY_FAST_COLOR_BLT_DEPTH_32 |
(XY_FAST_COLOR_BLT_DW - 2);
*cs++ = FIELD_PREP(XY_FAST_COLOR_BLT_MOCS_MASK, mocs) |
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index c931c56945bde..9fac5e2318e2b 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -639,7 +639,7 @@ static void init_l3cc_table(struct intel_gt *gt,
intel_gt_mcr_lock(gt, &flags);
for_each_l3cc(l3cc, table, i)
- if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 55))
intel_gt_mcr_multicast_write_fw(gt, XEHP_LNCFCMOCS(i), l3cc);
else
intel_uncore_write_fw(gt->uncore, GEN9_LNCFCMOCS(i), l3cc);
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 6a3246240e81d..5eec9cd6199f4 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -642,7 +642,7 @@ void intel_sseu_info_init(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
- if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
xehp_sseu_info_init(gt);
else if (GRAPHICS_VER(i915) >= 12)
gen12_sseu_info_init(gt);
@@ -851,7 +851,7 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
{
if (sseu->max_slices == 0)
drm_printf(p, "Unavailable\n");
- else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+ else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
sseu_print_xehp_topology(sseu, p);
else
sseu_print_hsw_topology(sseu, p);
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index cfe2f4b64f040..ba502c0be9b10 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2771,7 +2771,7 @@ add_render_compute_tuning_settings(struct intel_gt *gt,
wa_mcr_masked_field_set(wal, GEN9_ROW_CHICKEN4, THREAD_EX_ARB_MODE,
THREAD_EX_ARB_MODE_RR_AFTER_DEP);
- if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
+ if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 55))
wa_write_clr(wal, GEN8_GARBCNTL, GEN12_BUS_HASH_CTL_BIT_EXC);
}
@@ -2970,7 +2970,7 @@ static bool mcr_range(struct drm_i915_private *i915, u32 offset)
const struct i915_range *mcr_ranges;
int i;
- if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
mcr_ranges = mcr_ranges_xehp;
else if (GRAPHICS_VER(i915) >= 12)
mcr_ranges = mcr_ranges_gen12;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index a6440cfe4b985..217277329546c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -286,7 +286,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
/* Wa_22012773006:gen11,gen12 < XeHP */
if (GRAPHICS_VER(gt->i915) >= 11 &&
- GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 50))
+ GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 55))
flags |= GUC_WA_POLLCS;
/* Wa_14014475959 */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 5c9908b56616e..c606bb5e3b7b0 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -412,7 +412,7 @@ static int guc_mmio_regset_init(struct temp_regset *regset,
/* add in local MOCS registers */
for (i = 0; i < LNCFCMOCS_REG_COUNT; i++)
- if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
ret |= GUC_MCR_REG_ADD(gt, regset, XEHP_LNCFCMOCS(i), false);
else
ret |= GUC_MMIO_REG_ADD(gt, regset, GEN9_LNCFCMOCS(i), false);
@@ -522,7 +522,7 @@ static void fill_engine_enable_masks(struct intel_gt *gt,
#define LR_HW_CONTEXT_SIZE (80 * sizeof(u32))
#define XEHP_LR_HW_CONTEXT_SIZE (96 * sizeof(u32))
-#define LR_HW_CONTEXT_SZ(i915) (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50) ? \
+#define LR_HW_CONTEXT_SZ(i915) (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55) ? \
XEHP_LR_HW_CONTEXT_SIZE : \
LR_HW_CONTEXT_SIZE)
#define LRC_SKIP_SIZE(i915) (LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SZ(i915))
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
index 0a37c426cde4d..23f54c84cbab2 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -26,7 +26,7 @@ static void guc_prepare_xfer(struct intel_gt *gt)
GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |
GUC_ENABLE_MIA_CLOCK_GATING;
- if (GRAPHICS_VER_FULL(uncore->i915) < IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(uncore->i915) < IP_VER(12, 55))
shim_flags |= GUC_DISABLE_SRAM_INIT_TO_ZEROES |
GUC_ENABLE_MIA_CACHING;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 01d0ec1b30f2b..16640d6dd0589 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -4519,7 +4519,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
*/
engine->emit_bb_start = gen8_emit_bb_start;
- if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
engine->emit_bb_start = xehp_emit_bb_start;
}
diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
index 95c58805b2a4a..a62405787e774 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -166,7 +166,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
break;
case I915_PARAM_SLICE_MASK:
/* Not supported from Xe_HP onward; use topology queries */
- if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
return -EINVAL;
value = sseu->slice_mask;
@@ -175,7 +175,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
break;
case I915_PARAM_SUBSLICE_MASK:
/* Not supported from Xe_HP onward; use topology queries */
- if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
return -EINVAL;
/* Only copy bits from the first slice */
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index a0b784ebaddda..2594eb10c5594 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1245,8 +1245,7 @@ static void engine_record_registers(struct intel_engine_coredump *ee)
if (MEDIA_VER(i915) >= 13 && engine->gt->type == GT_MEDIA)
ee->fault_reg = intel_uncore_read(engine->uncore,
XELPMP_RING_FAULT_REG);
-
- else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+ else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
ee->fault_reg = intel_gt_mcr_read_any(engine->gt,
XEHP_RING_FAULT_REG);
else if (GRAPHICS_VER(i915) >= 12)
@@ -1852,7 +1851,7 @@ static void gt_record_global_regs(struct intel_gt_coredump *gt)
if (GRAPHICS_VER(i915) == 7)
gt->err_int = intel_uncore_read(uncore, GEN7_ERR_INT);
- if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
gt->fault_data0 = intel_gt_mcr_read_any((struct intel_gt *)gt->_gt,
XEHP_FAULT_TLB_DATA0);
gt->fault_data1 = intel_gt_mcr_read_any((struct intel_gt *)gt->_gt,
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 9052889dc0dc8..0b1cd4c7a525f 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -292,7 +292,7 @@ static u32 i915_perf_stream_paranoid = true;
#define OAREPORT_REASON_CTX_SWITCH (1<<3)
#define OAREPORT_REASON_CLK_RATIO (1<<5)
-#define HAS_MI_SET_PREDICATE(i915) (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+#define HAS_MI_SET_PREDICATE(i915) (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
/* For sysctl proc_dointvec_minmax of i915_oa_max_sample_rate
*
@@ -817,7 +817,7 @@ static int gen8_append_oa_reports(struct i915_perf_stream *stream,
*/
if (oa_report_ctx_invalid(stream, report) &&
- GRAPHICS_VER_FULL(stream->engine->i915) < IP_VER(12, 50)) {
+ GRAPHICS_VER_FULL(stream->engine->i915) < IP_VER(12, 55)) {
ctx_id = INVALID_CTX_ID;
oa_context_id_squash(stream, report32);
}
@@ -1419,7 +1419,7 @@ static int gen12_get_render_context_id(struct i915_perf_stream *stream)
mask = ((1U << GEN12_GUC_SW_CTX_ID_WIDTH) - 1) <<
(GEN12_GUC_SW_CTX_ID_SHIFT - 32);
- } else if (GRAPHICS_VER_FULL(stream->engine->i915) >= IP_VER(12, 50)) {
+ } else if (GRAPHICS_VER_FULL(stream->engine->i915) >= IP_VER(12, 55)) {
ctx_id = (XEHP_MAX_CONTEXT_HW_ID - 1) <<
(XEHP_SW_CTX_ID_SHIFT - 32);
@@ -4122,7 +4122,7 @@ static int read_properties_unlocked(struct i915_perf *perf,
props->hold_preemption = !!value;
break;
case DRM_I915_PERF_PROP_GLOBAL_SSEU: {
- if (GRAPHICS_VER_FULL(perf->i915) >= IP_VER(12, 50)) {
+ if (GRAPHICS_VER_FULL(perf->i915) >= IP_VER(12, 55)) {
drm_dbg(&perf->i915->drm,
"SSEU config not supported on gfx %x\n",
GRAPHICS_VER_FULL(perf->i915));
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index 3baa2f54a86ed..14d9ec0ed7771 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -105,7 +105,7 @@ static int query_geometry_subslices(struct drm_i915_private *i915,
struct intel_engine_cs *engine;
struct i915_engine_class_instance classinstance;
- if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 55))
return -ENODEV;
classinstance = *((struct i915_engine_class_instance *)&query_item->flags);
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index b525318dbd53b..4d2b15dbe9acd 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -2714,7 +2714,7 @@ void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore,
* the forcewake domain if any of the other engines
* in the same media slice are present.
*/
- if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 50) && i % 2 == 0) {
+ if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 55) && i % 2 == 0) {
if ((i + 1 < I915_MAX_VCS) && HAS_ENGINE(gt, _VCS(i + 1)))
continue;
--
2.43.0
^ permalink raw reply related [flat|nested] 15+ messages in thread* [CI 5/6] drm/i915: Drop dead code for pvc
2024-03-20 6:02 [CI 0/6] drm/i915: cleanup dead code Lucas De Marchi
` (3 preceding siblings ...)
2024-03-20 6:03 ` [CI 4/6] drm/i915: Update " Lucas De Marchi
@ 2024-03-20 6:03 ` Lucas De Marchi
2024-03-20 6:03 ` [CI 6/6] drm/i915: Remove special handling for !RCS_MASK() Lucas De Marchi
` (6 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Lucas De Marchi @ 2024-03-20 6:03 UTC (permalink / raw)
To: intel-gfx
PCI IDs for PVC were never added and platform always marked with
force_probe. Drop what's not used and rename some places as needed.
The registers not used anymore are also removed.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 2 +-
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 3 -
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 33 ----
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 30 +---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 9 --
drivers/gpu/drm/i915/gt/intel_mocs.c | 19 ---
drivers/gpu/drm/i915/gt/intel_rps.c | 4 +-
drivers/gpu/drm/i915/gt/intel_sseu.c | 9 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 82 +---------
.../gpu/drm/i915/gt/intel_workarounds.c.rej | 18 +++
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 -
drivers/gpu/drm/i915/i915_debugfs.c | 12 --
drivers/gpu/drm/i915/i915_drv.h | 9 --
drivers/gpu/drm/i915/i915_pci.c | 36 -----
drivers/gpu/drm/i915/i915_reg.h | 1 -
drivers/gpu/drm/i915/intel_clock_gating.c | 16 +-
drivers/gpu/drm/i915/intel_device_info.c | 1 -
drivers/gpu/drm/i915/intel_device_info.h | 1 -
drivers/gpu/drm/i915/intel_step.c | 70 +--------
drivers/gpu/drm/i915/intel_uncore.c | 142 ------------------
drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 -
| 4 -
22 files changed, 27 insertions(+), 480 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_workarounds.c.rej
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 0c5cdab278b69..1495b60744928 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -386,7 +386,7 @@ struct drm_i915_gem_object {
* and kernel mode driver for caching policy control after GEN12.
* In the meantime platform specific tables are created to translate
* i915_cache_level into pat index, for more details check the macros
- * defined i915/i915_pci.c, e.g. PVC_CACHELEVEL.
+ * defined i915/i915_pci.c, e.g. TGL_CACHELEVEL.
* For backward compatibility, this field contains values exactly match
* the entries of enum i915_cache_level for pre-GEN12 platforms (See
* LEGACY_CACHELEVEL), so that the PTE encode functions for these
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index f59914df6b5a7..e9f65f27b53fb 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -189,9 +189,6 @@ static bool gen12_needs_ccs_aux_inv(struct intel_engine_cs *engine)
{
i915_reg_t reg = gen12_get_aux_inv_reg(engine);
- if (IS_PONTEVECCHIO(engine->i915))
- return false;
-
/*
* So far platforms supported by i915 having flat ccs do not require
* AUX invalidation. Check also whether the engine requires it.
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 75bde8c1aa5da..396f5fe993c3f 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -839,38 +839,6 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
}
}
-static void engine_mask_apply_copy_fuses(struct intel_gt *gt)
-{
- struct drm_i915_private *i915 = gt->i915;
- struct intel_gt_info *info = >->info;
- unsigned long meml3_mask;
- unsigned long quad;
-
- if (!(GRAPHICS_VER_FULL(i915) >= IP_VER(12, 60) &&
- GRAPHICS_VER_FULL(i915) < IP_VER(12, 70)))
- return;
-
- meml3_mask = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3);
- meml3_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK, meml3_mask);
-
- /*
- * Link Copy engines may be fused off according to meml3_mask. Each
- * bit is a quad that houses 2 Link Copy and two Sub Copy engines.
- */
- for_each_clear_bit(quad, &meml3_mask, GEN12_MAX_MSLICES) {
- unsigned int instance = quad * 2 + 1;
- intel_engine_mask_t mask = GENMASK(_BCS(instance + 1),
- _BCS(instance));
-
- if (mask & info->engine_mask) {
- gt_dbg(gt, "bcs%u fused off\n", instance);
- gt_dbg(gt, "bcs%u fused off\n", instance + 1);
-
- info->engine_mask &= ~mask;
- }
- }
-}
-
/*
* Determine which engines are fused off in our particular hardware.
* Note that we have a catch-22 situation where we need to be able to access
@@ -889,7 +857,6 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
engine_mask_apply_media_fuses(gt);
engine_mask_apply_compute_fuses(gt);
- engine_mask_apply_copy_fuses(gt);
/*
* The only use of the GSC CS is to load and communicate with the GSC
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index 29443bf7c06c9..b8912bd6c08ed 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -69,27 +69,6 @@ static const struct intel_mmio_range dg2_lncf_steering_table[] = {
{},
};
-/*
- * We have several types of MCR registers on PVC where steering to (0,0)
- * will always provide us with a non-terminated value. We'll stick them
- * all in the same table for simplicity.
- */
-static const struct intel_mmio_range pvc_instance0_steering_table[] = {
- { 0x004000, 0x004AFF }, /* HALF-BSLICE */
- { 0x008800, 0x00887F }, /* CC */
- { 0x008A80, 0x008AFF }, /* TILEPSMI */
- { 0x00B000, 0x00B0FF }, /* HALF-BSLICE */
- { 0x00B100, 0x00B3FF }, /* L3BANK */
- { 0x00C800, 0x00CFFF }, /* HALF-BSLICE */
- { 0x00D800, 0x00D8FF }, /* HALF-BSLICE */
- { 0x00DD00, 0x00DDFF }, /* BSLICE */
- { 0x00E900, 0x00E9FF }, /* HALF-BSLICE */
- { 0x00EC00, 0x00EEFF }, /* HALF-BSLICE */
- { 0x00F000, 0x00FFFF }, /* HALF-BSLICE */
- { 0x024180, 0x0241FF }, /* HALF-BSLICE */
- {},
-};
-
static const struct intel_mmio_range xelpg_instance0_steering_table[] = {
{ 0x000B00, 0x000BFF }, /* SQIDI */
{ 0x001000, 0x001FFF }, /* SQIDI */
@@ -173,8 +152,6 @@ void intel_gt_mcr_init(struct intel_gt *gt)
gt->steering_table[INSTANCE0] = xelpg_instance0_steering_table;
gt->steering_table[L3BANK] = xelpg_l3bank_steering_table;
gt->steering_table[DSS] = xelpg_dss_steering_table;
- } else if (IS_PONTEVECCHIO(i915)) {
- gt->steering_table[INSTANCE0] = pvc_instance0_steering_table;
} else if (IS_DG2(i915)) {
gt->steering_table[MSLICE] = dg2_mslice_steering_table;
gt->steering_table[LNCF] = dg2_lncf_steering_table;
@@ -805,8 +782,6 @@ void intel_gt_mcr_report_steering(struct drm_printer *p, struct intel_gt *gt,
for (int i = 0; i < NUM_STEERING_TYPES; i++)
if (gt->steering_table[i])
report_steering_type(p, gt, i, dump_table);
- } else if (IS_PONTEVECCHIO(gt->i915)) {
- report_steering_type(p, gt, INSTANCE0, dump_table);
} else if (HAS_MSLICE_STEERING(gt->i915)) {
report_steering_type(p, gt, MSLICE, dump_table);
report_steering_type(p, gt, LNCF, dump_table);
@@ -826,10 +801,7 @@ void intel_gt_mcr_report_steering(struct drm_printer *p, struct intel_gt *gt,
void intel_gt_mcr_get_ss_steering(struct intel_gt *gt, unsigned int dss,
unsigned int *group, unsigned int *instance)
{
- if (IS_PONTEVECCHIO(gt->i915)) {
- *group = dss / GEN_DSS_PER_CSLICE;
- *instance = dss % GEN_DSS_PER_CSLICE;
- } else if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 55)) {
+ if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 55)) {
*group = dss / GEN_DSS_PER_GSLICE;
*instance = dss % GEN_DSS_PER_GSLICE;
} else {
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 919c079037677..8d8d781b44b6b 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -953,10 +953,6 @@
#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
#define GEN7_L3AGDIS (1 << 19)
-#define XEHPC_LNCFMISCCFGREG0 MCR_REG(0xb01c)
-#define XEHPC_HOSTCACHEEN REG_BIT(1)
-#define XEHPC_OVRLSCCC REG_BIT(0)
-
#define GEN7_L3CNTLREG2 _MMIO(0xb020)
/* MOCS (Memory Object Control State) registers */
@@ -1013,11 +1009,6 @@
#define XEHP_L3SCQREG7 MCR_REG(0xb188)
#define BLEND_FILL_CACHING_OPT_DIS REG_BIT(3)
-#define XEHPC_L3SCRUB MCR_REG(0xb18c)
-#define SCRUB_CL_DWNGRADE_SHARED REG_BIT(12)
-#define SCRUB_RATE_PER_BANK_MASK REG_GENMASK(2, 0)
-#define SCRUB_RATE_4B_PER_CLK REG_FIELD_PREP(SCRUB_RATE_PER_BANK_MASK, 0x6)
-
#define GEN11_GLBLINVL _MMIO(0xb404)
#define GEN11_BANK_HASH_ADDR_EXCL_MASK (0x7f << 5)
#define GEN11_BANK_HASH_ADDR_EXCL_BIT0 (1 << 5)
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 9fac5e2318e2b..d791d63d49b49 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -53,7 +53,6 @@ struct drm_i915_mocs_table {
/* Helper defines */
#define GEN9_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
-#define PVC_NUM_MOCS_ENTRIES 3
#define MTL_NUM_MOCS_ENTRIES 16
/* (e)LLC caching options */
@@ -379,17 +378,6 @@ static const struct drm_i915_mocs_entry dg2_mocs_table[] = {
MOCS_ENTRY(3, 0, L3_3_WB | L3_LKUP(1)),
};
-static const struct drm_i915_mocs_entry pvc_mocs_table[] = {
- /* Error */
- MOCS_ENTRY(0, 0, L3_3_WB),
-
- /* UC */
- MOCS_ENTRY(1, 0, L3_1_UC),
-
- /* WB */
- MOCS_ENTRY(2, 0, L3_3_WB),
-};
-
static const struct drm_i915_mocs_entry mtl_mocs_table[] = {
/* Error - Reserved for Non-Use */
MOCS_ENTRY(0,
@@ -476,13 +464,6 @@ static unsigned int get_mocs_settings(struct drm_i915_private *i915,
table->n_entries = MTL_NUM_MOCS_ENTRIES;
table->uc_index = 9;
table->unused_entries_index = 1;
- } else if (IS_PONTEVECCHIO(i915)) {
- table->size = ARRAY_SIZE(pvc_mocs_table);
- table->table = pvc_mocs_table;
- table->n_entries = PVC_NUM_MOCS_ENTRIES;
- table->uc_index = 1;
- table->wb_index = 2;
- table->unused_entries_index = 2;
} else if (IS_DG2(i915)) {
table->size = ARRAY_SIZE(dg2_mocs_table);
table->table = dg2_mocs_table;
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index 1788db4376e50..c9cb2a3919423 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -1090,9 +1090,7 @@ static u32 intel_rps_read_state_cap(struct intel_rps *rps)
struct drm_i915_private *i915 = rps_to_i915(rps);
struct intel_uncore *uncore = rps_to_uncore(rps);
- if (IS_PONTEVECCHIO(i915))
- return intel_uncore_read(uncore, PVC_RP_STATE_CAP);
- else if (IS_GEN9_LP(i915))
+ if (IS_GEN9_LP(i915))
return intel_uncore_read(uncore, BXT_RP_STATE_CAP);
else
return intel_uncore_read(uncore, GEN6_RP_STATE_CAP);
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 5eec9cd6199f4..c8fadf58d8361 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -214,13 +214,8 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
int num_compute_regs, num_geometry_regs;
int eu;
- if (IS_PONTEVECCHIO(gt->i915)) {
- num_geometry_regs = 0;
- num_compute_regs = 2;
- } else {
- num_geometry_regs = 1;
- num_compute_regs = 1;
- }
+ num_geometry_regs = 1;
+ num_compute_regs = 1;
/*
* The concept of slice has been removed in Xe_HP. To be compatible
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index ba502c0be9b10..8a1adc8aadddf 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -257,12 +257,6 @@ wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
wa_write_clr_set(wal, reg, ~0, set);
}
-static void
-wa_mcr_write(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 set)
-{
- wa_mcr_write_clr_set(wal, reg, ~0, set);
-}
-
static void
wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
{
@@ -918,8 +912,6 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 74)))
xelpg_ctx_workarounds_init(engine, wal);
- else if (IS_PONTEVECCHIO(i915))
- ; /* noop; none at this time */
else if (IS_DG2(i915))
dg2_ctx_workarounds_init(engine, wal);
else if (IS_DG1(i915))
@@ -1374,20 +1366,6 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
__set_mcr_steering(wal, GAM_MCR_SELECTOR, 1, 0);
}
-static void
-pvc_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
-{
- unsigned int dss;
-
- /*
- * Setup implicit steering for COMPUTE and DSS ranges to the first
- * non-fused-off DSS. All other types of MCR registers will be
- * explicitly steered.
- */
- dss = intel_sseu_find_first_xehp_dss(>->info.sseu, 0, 0);
- __add_mcr_wa(gt, wal, dss / GEN_DSS_PER_CSLICE, dss % GEN_DSS_PER_CSLICE);
-}
-
static void
icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
{
@@ -1556,24 +1534,6 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE);
}
-static void
-pvc_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
-{
- pvc_init_mcr(gt, wal);
-
- /* Wa_14015795083 */
- wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
-
- /* Wa_18018781329 */
- wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
- wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
- wa_mcr_write_or(wal, XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB);
- wa_mcr_write_or(wal, XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB);
-
- /* Wa_16016694945 */
- wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC);
-}
-
static void
xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
{
@@ -1650,12 +1610,6 @@ static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal)
wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
}
- if (IS_PONTEVECCHIO(gt->i915)) {
- wa_mcr_write(wal, XEHPC_L3SCRUB,
- SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK);
- wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_HOSTCACHEEN);
- }
-
if (IS_DG2(gt->i915)) {
wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
@@ -1680,8 +1634,6 @@ gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)))
xelpg_gt_workarounds_init(gt, wal);
- else if (IS_PONTEVECCHIO(i915))
- pvc_gt_workarounds_init(gt, wal);
else if (IS_DG2(i915))
dg2_gt_workarounds_init(gt, wal);
else if (IS_DG1(i915))
@@ -2101,30 +2053,6 @@ static void dg2_whitelist_build(struct intel_engine_cs *engine)
}
}
-static void blacklist_trtt(struct intel_engine_cs *engine)
-{
- struct i915_wa_list *w = &engine->whitelist;
-
- /*
- * Prevent read/write access to [0x4400, 0x4600) which covers
- * the TRTT range across all engines. Note that normally userspace
- * cannot access the other engines' trtt control, but for simplicity
- * we cover the entire range on each engine.
- */
- whitelist_reg_ext(w, _MMIO(0x4400),
- RING_FORCE_TO_NONPRIV_DENY |
- RING_FORCE_TO_NONPRIV_RANGE_64);
- whitelist_reg_ext(w, _MMIO(0x4500),
- RING_FORCE_TO_NONPRIV_DENY |
- RING_FORCE_TO_NONPRIV_RANGE_64);
-}
-
-static void pvc_whitelist_build(struct intel_engine_cs *engine)
-{
- /* Wa_16014440446:pvc */
- blacklist_trtt(engine);
-}
-
static void xelpg_whitelist_build(struct intel_engine_cs *engine)
{
struct i915_wa_list *w = &engine->whitelist;
@@ -2151,8 +2079,6 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
; /* none yet */
else if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 74)))
xelpg_whitelist_build(engine);
- else if (IS_PONTEVECCHIO(i915))
- pvc_whitelist_build(engine);
else if (IS_DG2(i915))
dg2_whitelist_build(engine);
else if (GRAPHICS_VER(i915) == 12)
@@ -2735,10 +2661,7 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
static void
ccs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
{
- if (IS_PVC_CT_STEP(engine->i915, STEP_A0, STEP_C0)) {
- /* Wa_14014999345:pvc */
- wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS, DISABLE_ECC);
- }
+ /* boilerplate for any CCS engine workaround */
}
/*
@@ -2844,13 +2767,12 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
- IS_PONTEVECCHIO(i915) ||
IS_DG2(i915)) {
/* Wa_22014226127 */
wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
}
- if (IS_PONTEVECCHIO(i915) || IS_DG2(i915))
+ if (IS_DG2(i915))
/* Wa_14015227452:dg2,pvc */
wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE);
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c.rej b/drivers/gpu/drm/i915/gt/intel_workarounds.c.rej
new file mode 100644
index 0000000000000..91463b1d684ad
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c.rej
@@ -0,0 +1,18 @@
+diff a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c (rejected hunks)
+@@ -2844,14 +2767,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
+
+ if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
+ IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
+- IS_PONTEVECCHIO(i915) ||
+ IS_DG2(i915)) {
+ /* Wa_22014226127 */
+ wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
+ }
+
+- if (IS_PONTEVECCHIO(i915) || IS_DG2(i915))
+- /* Wa_14015227452:dg2,pvc */
++ if (IS_DG2(i915))
++ /* Wa_14015227452 */
+ wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE);
+
+ if (IS_DG2(i915)) {
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 28277321d9ca9..b47051ddf17f2 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -50,10 +50,6 @@ static void uc_expand_default_options(struct intel_uc *uc)
/* Default: enable HuC authentication and GuC submission */
i915->params.enable_guc = ENABLE_GUC_LOAD_HUC | ENABLE_GUC_SUBMISSION;
-
- /* PVC does not use HuC */
- if (IS_PONTEVECCHIO(i915))
- i915->params.enable_guc &= ~ENABLE_GUC_LOAD_HUC;
}
/* Reset GuC providing us with fresh state for both GuC and HuC.
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 990eaa029d9c2..24c78873b3cf5 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -156,18 +156,6 @@ static const char *i915_cache_level_str(struct drm_i915_gem_object *obj)
case 4: return " WB (2-Way Coh)";
default: return " not defined";
}
- } else if (IS_PONTEVECCHIO(i915)) {
- switch (obj->pat_index) {
- case 0: return " UC";
- case 1: return " WC";
- case 2: return " WT";
- case 3: return " WB";
- case 4: return " WT (CLOS1)";
- case 5: return " WB (CLOS1)";
- case 6: return " WT (CLOS2)";
- case 7: return " WT (CLOS2)";
- default: return " not defined";
- }
} else if (GRAPHICS_VER(i915) >= 12) {
switch (obj->pat_index) {
case 0: return " WB";
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index dff056587459f..cf52d4adaa204 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -545,7 +545,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_ALDERLAKE_S(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_S)
#define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P)
#define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2)
-#define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO)
#define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)
#define IS_LUNARLAKE(i915) 0
@@ -620,14 +619,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_TIGERLAKE_UY(i915) \
IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
-#define IS_PVC_BD_STEP(__i915, since, until) \
- (IS_PONTEVECCHIO(__i915) && \
- IS_BASEDIE_STEP(__i915, since, until))
-
-#define IS_PVC_CT_STEP(__i915, since, until) \
- (IS_PONTEVECCHIO(__i915) && \
- IS_GRAPHICS_STEP(__i915, since, until))
-
#define IS_LP(i915) (INTEL_INFO(i915)->is_lp)
#define IS_GEN9_LP(i915) (GRAPHICS_VER(i915) == 9 && IS_LP(i915))
#define IS_GEN9_BC(i915) (GRAPHICS_VER(i915) == 9 && !IS_LP(i915))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 8b673fdcf178f..1e69783ae4fd9 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -59,14 +59,6 @@
[I915_CACHE_WT] = 2, \
}
-#define PVC_CACHELEVEL \
- .cachelevel_to_pat = { \
- [I915_CACHE_NONE] = 0, \
- [I915_CACHE_LLC] = 3, \
- [I915_CACHE_L3_LLC] = 3, \
- [I915_CACHE_WT] = 2, \
- }
-
#define MTL_CACHELEVEL \
.cachelevel_to_pat = { \
[I915_CACHE_NONE] = 2, \
@@ -756,34 +748,6 @@ static const struct intel_device_info ats_m_info = {
.tuning_thread_rr_after_dep = 1,
};
-#define XE_HPC_FEATURES \
- XE_HP_FEATURES, \
- .dma_mask_size = 52, \
- .has_3d_pipeline = 0, \
- .has_guc_deprivilege = 1, \
- .has_l3_ccs_read = 1, \
- .has_mslice_steering = 0, \
- .has_one_eu_per_fuse_bit = 1
-
-__maybe_unused
-static const struct intel_device_info pvc_info = {
- XE_HPC_FEATURES,
- DGFX_FEATURES,
- .__runtime.graphics.ip.ver = 12,
- .__runtime.graphics.ip.rel = 60,
- .__runtime.media.ip.ver = 12,
- .__runtime.media.ip.rel = 60,
- PLATFORM(INTEL_PONTEVECCHIO),
- .has_flat_ccs = 0,
- .max_pat_index = 7,
- .platform_engine_mask =
- BIT(BCS0) |
- BIT(VCS0) |
- BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
- .require_force_probe = 1,
- PVC_CACHELEVEL,
-};
-
static const struct intel_gt_definition xelpmp_extra_gt[] = {
{
.type = GT_MEDIA,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7a84eb31818cc..c18e7dbb025e7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1750,7 +1750,6 @@
#define BXT_RP_STATE_CAP _MMIO(0x138170)
#define GEN9_RP_STATE_LIMITS _MMIO(0x138148)
-#define PVC_RP_STATE_CAP _MMIO(0x281014)
#define MTL_RP_STATE_CAP _MMIO(0x138000)
#define MTL_MEDIAP_STATE_CAP _MMIO(0x138020)
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index e34e1aabe6f86..7e70ee4fbd84d 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -350,17 +350,6 @@ static void dg2_init_clock_gating(struct drm_i915_private *i915)
SGSI_SIDECLK_DIS);
}
-static void pvc_init_clock_gating(struct drm_i915_private *i915)
-{
- /* Wa_14012385139:pvc */
- if (IS_PVC_BD_STEP(i915, STEP_A0, STEP_B0))
- intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0, SGR_DIS);
-
- /* Wa_22010954014:pvc */
- if (IS_PVC_BD_STEP(i915, STEP_A0, STEP_B0))
- intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS);
-}
-
static void cnp_init_clock_gating(struct drm_i915_private *i915)
{
if (!HAS_PCH_CNP(i915))
@@ -722,7 +711,6 @@ static const struct drm_i915_clock_gating_funcs platform##_clock_gating_funcs =
.init_clock_gating = platform##_init_clock_gating, \
}
-CG_FUNCS(pvc);
CG_FUNCS(dg2);
CG_FUNCS(cfl);
CG_FUNCS(skl);
@@ -756,9 +744,7 @@ CG_FUNCS(nop);
*/
void intel_clock_gating_hooks_init(struct drm_i915_private *i915)
{
- if (IS_PONTEVECCHIO(i915))
- i915->clock_gating_funcs = &pvc_clock_gating_funcs;
- else if (IS_DG2(i915))
+ if (IS_DG2(i915))
i915->clock_gating_funcs = &dg2_clock_gating_funcs;
else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
i915->clock_gating_funcs = &cfl_clock_gating_funcs;
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index de28cbe758f7e..a0a43ea07f118 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -71,7 +71,6 @@ static const char * const platform_names[] = {
PLATFORM_NAME(ALDERLAKE_S),
PLATFORM_NAME(ALDERLAKE_P),
PLATFORM_NAME(DG2),
- PLATFORM_NAME(PONTEVECCHIO),
PLATFORM_NAME(METEORLAKE),
};
#undef PLATFORM_NAME
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 2299327e59f0a..d1a2abc7e5139 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -88,7 +88,6 @@ enum intel_platform {
INTEL_ALDERLAKE_S,
INTEL_ALDERLAKE_P,
INTEL_DG2,
- INTEL_PONTEVECCHIO,
INTEL_METEORLAKE,
INTEL_MAX_PLATFORMS
};
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index d524bfe17c270..a5adfb5d8fd2a 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -146,8 +146,6 @@ static u8 gmd_to_intel_step(struct drm_i915_private *i915,
return step;
}
-static void pvc_step_init(struct drm_i915_private *i915, int pci_revid);
-
void intel_step_init(struct drm_i915_private *i915)
{
const struct intel_step_info *revids = NULL;
@@ -171,10 +169,7 @@ void intel_step_init(struct drm_i915_private *i915)
return;
}
- if (IS_PONTEVECCHIO(i915)) {
- pvc_step_init(i915, revid);
- return;
- } else if (IS_DG2_G10(i915)) {
+ if (IS_DG2_G10(i915)) {
revids = dg2_g10_revid_step_tbl;
size = ARRAY_SIZE(dg2_g10_revid_step_tbl);
} else if (IS_DG2_G11(i915)) {
@@ -267,69 +262,6 @@ void intel_step_init(struct drm_i915_private *i915)
RUNTIME_INFO(i915)->step = step;
}
-#define PVC_BD_REVID GENMASK(5, 3)
-#define PVC_CT_REVID GENMASK(2, 0)
-
-static const int pvc_bd_subids[] = {
- [0x0] = STEP_A0,
- [0x3] = STEP_B0,
- [0x4] = STEP_B1,
- [0x5] = STEP_B3,
-};
-
-static const int pvc_ct_subids[] = {
- [0x3] = STEP_A0,
- [0x5] = STEP_B0,
- [0x6] = STEP_B1,
- [0x7] = STEP_C0,
-};
-
-static int
-pvc_step_lookup(struct drm_i915_private *i915, const char *type,
- const int *table, int size, int subid)
-{
- if (subid < size && table[subid] != STEP_NONE)
- return table[subid];
-
- drm_warn(&i915->drm, "Unknown %s id 0x%02x\n", type, subid);
-
- /*
- * As on other platforms, try to use the next higher ID if we land on a
- * gap in the table.
- */
- while (subid < size && table[subid] == STEP_NONE)
- subid++;
-
- if (subid < size) {
- drm_dbg(&i915->drm, "Using steppings for %s id 0x%02x\n",
- type, subid);
- return table[subid];
- }
-
- drm_dbg(&i915->drm, "Using future steppings\n");
- return STEP_FUTURE;
-}
-
-/*
- * PVC needs special handling since we don't lookup the
- * revid in a table, but rather specific bitfields within
- * the revid for various components.
- */
-static void pvc_step_init(struct drm_i915_private *i915, int pci_revid)
-{
- int ct_subid, bd_subid;
-
- bd_subid = FIELD_GET(PVC_BD_REVID, pci_revid);
- ct_subid = FIELD_GET(PVC_CT_REVID, pci_revid);
-
- RUNTIME_INFO(i915)->step.basedie_step =
- pvc_step_lookup(i915, "Base Die", pvc_bd_subids,
- ARRAY_SIZE(pvc_bd_subids), bd_subid);
- RUNTIME_INFO(i915)->step.graphics_step =
- pvc_step_lookup(i915, "Compute Tile", pvc_ct_subids,
- ARRAY_SIZE(pvc_ct_subids), ct_subid);
-}
-
#define STEP_NAME_CASE(name) \
case STEP_##name: \
return #name;
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 4d2b15dbe9acd..729409a4bada8 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1106,45 +1106,6 @@ static const struct i915_range dg2_shadowed_regs[] = {
{ .start = 0x1F8510, .end = 0x1F8550 },
};
-static const struct i915_range pvc_shadowed_regs[] = {
- { .start = 0x2030, .end = 0x2030 },
- { .start = 0x2510, .end = 0x2550 },
- { .start = 0xA008, .end = 0xA00C },
- { .start = 0xA188, .end = 0xA188 },
- { .start = 0xA278, .end = 0xA278 },
- { .start = 0xA540, .end = 0xA56C },
- { .start = 0xC4C8, .end = 0xC4C8 },
- { .start = 0xC4E0, .end = 0xC4E0 },
- { .start = 0xC600, .end = 0xC600 },
- { .start = 0xC658, .end = 0xC658 },
- { .start = 0x22030, .end = 0x22030 },
- { .start = 0x22510, .end = 0x22550 },
- { .start = 0x1C0030, .end = 0x1C0030 },
- { .start = 0x1C0510, .end = 0x1C0550 },
- { .start = 0x1C4030, .end = 0x1C4030 },
- { .start = 0x1C4510, .end = 0x1C4550 },
- { .start = 0x1C8030, .end = 0x1C8030 },
- { .start = 0x1C8510, .end = 0x1C8550 },
- { .start = 0x1D0030, .end = 0x1D0030 },
- { .start = 0x1D0510, .end = 0x1D0550 },
- { .start = 0x1D4030, .end = 0x1D4030 },
- { .start = 0x1D4510, .end = 0x1D4550 },
- { .start = 0x1D8030, .end = 0x1D8030 },
- { .start = 0x1D8510, .end = 0x1D8550 },
- { .start = 0x1E0030, .end = 0x1E0030 },
- { .start = 0x1E0510, .end = 0x1E0550 },
- { .start = 0x1E4030, .end = 0x1E4030 },
- { .start = 0x1E4510, .end = 0x1E4550 },
- { .start = 0x1E8030, .end = 0x1E8030 },
- { .start = 0x1E8510, .end = 0x1E8550 },
- { .start = 0x1F0030, .end = 0x1F0030 },
- { .start = 0x1F0510, .end = 0x1F0550 },
- { .start = 0x1F4030, .end = 0x1F4030 },
- { .start = 0x1F4510, .end = 0x1F4550 },
- { .start = 0x1F8030, .end = 0x1F8030 },
- { .start = 0x1F8510, .end = 0x1F8550 },
-};
-
static const struct i915_range mtl_shadowed_regs[] = {
{ .start = 0x2030, .end = 0x2030 },
{ .start = 0x2510, .end = 0x2550 },
@@ -1619,105 +1580,6 @@ static const struct intel_forcewake_range __dg2_fw_ranges[] = {
GEN_FW_RANGE(0x1f8000, 0x1fa0ff, FORCEWAKE_MEDIA_VEBOX3),
};
-static const struct intel_forcewake_range __pvc_fw_ranges[] = {
- GEN_FW_RANGE(0x0, 0xaff, 0),
- GEN_FW_RANGE(0xb00, 0xbff, FORCEWAKE_GT),
- GEN_FW_RANGE(0xc00, 0xfff, 0),
- GEN_FW_RANGE(0x1000, 0x1fff, FORCEWAKE_GT),
- GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
- GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT),
- GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
- GEN_FW_RANGE(0x4000, 0x813f, FORCEWAKE_GT), /*
- 0x4000 - 0x4aff: gt
- 0x4b00 - 0x4fff: reserved
- 0x5000 - 0x51ff: gt
- 0x5200 - 0x52ff: reserved
- 0x5300 - 0x53ff: gt
- 0x5400 - 0x7fff: reserved
- 0x8000 - 0x813f: gt */
- GEN_FW_RANGE(0x8140, 0x817f, FORCEWAKE_RENDER),
- GEN_FW_RANGE(0x8180, 0x81ff, 0),
- GEN_FW_RANGE(0x8200, 0x94cf, FORCEWAKE_GT), /*
- 0x8200 - 0x82ff: gt
- 0x8300 - 0x84ff: reserved
- 0x8500 - 0x887f: gt
- 0x8880 - 0x8a7f: reserved
- 0x8a80 - 0x8aff: gt
- 0x8b00 - 0x8fff: reserved
- 0x9000 - 0x947f: gt
- 0x9480 - 0x94cf: reserved */
- GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),
- GEN_FW_RANGE(0x9560, 0x967f, 0), /*
- 0x9560 - 0x95ff: always on
- 0x9600 - 0x967f: reserved */
- GEN_FW_RANGE(0x9680, 0x97ff, FORCEWAKE_RENDER), /*
- 0x9680 - 0x96ff: render
- 0x9700 - 0x97ff: reserved */
- GEN_FW_RANGE(0x9800, 0xcfff, FORCEWAKE_GT), /*
- 0x9800 - 0xb4ff: gt
- 0xb500 - 0xbfff: reserved
- 0xc000 - 0xcfff: gt */
- GEN_FW_RANGE(0xd000, 0xd3ff, 0),
- GEN_FW_RANGE(0xd400, 0xdbff, FORCEWAKE_GT),
- GEN_FW_RANGE(0xdc00, 0xdcff, FORCEWAKE_RENDER),
- GEN_FW_RANGE(0xdd00, 0xde7f, FORCEWAKE_GT), /*
- 0xdd00 - 0xddff: gt
- 0xde00 - 0xde7f: reserved */
- GEN_FW_RANGE(0xde80, 0xe8ff, FORCEWAKE_RENDER), /*
- 0xde80 - 0xdeff: render
- 0xdf00 - 0xe1ff: reserved
- 0xe200 - 0xe7ff: render
- 0xe800 - 0xe8ff: reserved */
- GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_GT), /*
- 0xe900 - 0xe9ff: gt
- 0xea00 - 0xebff: reserved
- 0xec00 - 0xffff: gt
- 0x10000 - 0x11fff: reserved */
- GEN_FW_RANGE(0x12000, 0x12fff, 0), /*
- 0x12000 - 0x127ff: always on
- 0x12800 - 0x12fff: reserved */
- GEN_FW_RANGE(0x13000, 0x19fff, FORCEWAKE_GT), /*
- 0x13000 - 0x135ff: gt
- 0x13600 - 0x147ff: reserved
- 0x14800 - 0x153ff: gt
- 0x15400 - 0x19fff: reserved */
- GEN_FW_RANGE(0x1a000, 0x21fff, FORCEWAKE_RENDER), /*
- 0x1a000 - 0x1ffff: render
- 0x20000 - 0x21fff: reserved */
- GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT),
- GEN_FW_RANGE(0x24000, 0x2417f, 0), /*
- 24000 - 0x2407f: always on
- 24080 - 0x2417f: reserved */
- GEN_FW_RANGE(0x24180, 0x25fff, FORCEWAKE_GT), /*
- 0x24180 - 0x241ff: gt
- 0x24200 - 0x251ff: reserved
- 0x25200 - 0x252ff: gt
- 0x25300 - 0x25fff: reserved */
- GEN_FW_RANGE(0x26000, 0x2ffff, FORCEWAKE_RENDER), /*
- 0x26000 - 0x27fff: render
- 0x28000 - 0x2ffff: reserved */
- GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_GT),
- GEN_FW_RANGE(0x40000, 0x1bffff, 0),
- GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /*
- 0x1c0000 - 0x1c2bff: VD0
- 0x1c2c00 - 0x1c2cff: reserved
- 0x1c2d00 - 0x1c2dff: VD0
- 0x1c2e00 - 0x1c3eff: reserved
- 0x1c3f00 - 0x1c3fff: VD0 */
- GEN_FW_RANGE(0x1c4000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX1), /*
- 0x1c4000 - 0x1c6aff: VD1
- 0x1c6b00 - 0x1c7eff: reserved
- 0x1c7f00 - 0x1c7fff: VD1
- 0x1c8000 - 0x1cffff: reserved */
- GEN_FW_RANGE(0x1d0000, 0x23ffff, FORCEWAKE_MEDIA_VDBOX2), /*
- 0x1d0000 - 0x1d2aff: VD2
- 0x1d2b00 - 0x1d3eff: reserved
- 0x1d3f00 - 0x1d3fff: VD2
- 0x1d4000 - 0x23ffff: reserved */
- GEN_FW_RANGE(0x240000, 0x3dffff, 0),
- GEN_FW_RANGE(0x3e0000, 0x3effff, FORCEWAKE_GT),
-};
-
static const struct intel_forcewake_range __mtl_fw_ranges[] = {
GEN_FW_RANGE(0x0, 0xaff, 0),
GEN_FW_RANGE(0xb00, 0xbff, FORCEWAKE_GT),
@@ -2560,10 +2422,6 @@ static int uncore_forcewake_init(struct intel_uncore *uncore)
ASSIGN_FW_DOMAINS_TABLE(uncore, __mtl_fw_ranges);
ASSIGN_SHADOW_TABLE(uncore, mtl_shadowed_regs);
ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
- } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 60)) {
- ASSIGN_FW_DOMAINS_TABLE(uncore, __pvc_fw_ranges);
- ASSIGN_SHADOW_TABLE(uncore, pvc_shadowed_regs);
- ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
ASSIGN_FW_DOMAINS_TABLE(uncore, __dg2_fw_ranges);
ASSIGN_SHADOW_TABLE(uncore, dg2_shadowed_regs);
diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c
index 502bcadc5f396..41eaa9b7f67d0 100644
--- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
+++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
@@ -71,7 +71,6 @@ static int intel_shadow_table_check(void)
{ gen11_shadowed_regs, ARRAY_SIZE(gen11_shadowed_regs) },
{ gen12_shadowed_regs, ARRAY_SIZE(gen12_shadowed_regs) },
{ dg2_shadowed_regs, ARRAY_SIZE(dg2_shadowed_regs) },
- { pvc_shadowed_regs, ARRAY_SIZE(pvc_shadowed_regs) },
{ mtl_shadowed_regs, ARRAY_SIZE(mtl_shadowed_regs) },
{ xelpmp_shadowed_regs, ARRAY_SIZE(xelpmp_shadowed_regs) },
};
@@ -119,7 +118,6 @@ int intel_uncore_mock_selftests(void)
{ __gen9_fw_ranges, ARRAY_SIZE(__gen9_fw_ranges), true },
{ __gen11_fw_ranges, ARRAY_SIZE(__gen11_fw_ranges), true },
{ __gen12_fw_ranges, ARRAY_SIZE(__gen12_fw_ranges), true },
- { __pvc_fw_ranges, ARRAY_SIZE(__pvc_fw_ranges), true },
{ __mtl_fw_ranges, ARRAY_SIZE(__mtl_fw_ranges), true },
{ __xelpmp_fw_ranges, ARRAY_SIZE(__xelpmp_fw_ranges), true },
};
--git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
index a7e7ec3b5db92..a01d1b869c2df 100644
--- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
+++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
@@ -86,7 +86,6 @@ static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, XE_ALDERLAKE_S)
#define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, XE_ALDERLAKE_P)
#define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, XE_DG2)
-#define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, XE_PVC)
#define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_METEORLAKE)
#define IS_LUNARLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_LUNARLAKE)
@@ -130,9 +129,6 @@ static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
((xe)->info.subplatform == XE_SUBPLATFORM_DG2_ ## variant && \
IS_GRAPHICS_STEP(xe, first, last))
-/* XXX: No basedie stepping support yet */
-#define IS_PVC_BD_STEP(xe, first, last) (!WARN_ON(1) && IS_PONTEVECCHIO(xe))
-
#define IS_TIGERLAKE_DISPLAY_STEP(xe, first, last) (IS_TIGERLAKE(xe) && IS_DISPLAY_STEP(xe, first, last))
#define IS_ROCKETLAKE_DISPLAY_STEP(xe, first, last) (IS_ROCKETLAKE(xe) && IS_DISPLAY_STEP(xe, first, last))
#define IS_DG1_DISPLAY_STEP(xe, first, last) (IS_DG1(xe) && IS_DISPLAY_STEP(xe, first, last))
--
2.43.0
^ permalink raw reply related [flat|nested] 15+ messages in thread* [CI 6/6] drm/i915: Remove special handling for !RCS_MASK()
2024-03-20 6:02 [CI 0/6] drm/i915: cleanup dead code Lucas De Marchi
` (4 preceding siblings ...)
2024-03-20 6:03 ` [CI 5/6] drm/i915: Drop dead code for pvc Lucas De Marchi
@ 2024-03-20 6:03 ` Lucas De Marchi
2024-03-20 7:31 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: cleanup dead code Patchwork
` (5 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Lucas De Marchi @ 2024-03-20 6:03 UTC (permalink / raw)
To: intel-gfx
With both XEHPSDV and PVC removed (as platforms, most of their code
remain used by others), there's no need to handle !RCS_MASK() as
other platforms don't ever have fused-off render. Remove those code
paths and the special WA flag when initializing GuC.
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 5 ++---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4 ----
2 files changed, 2 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 396f5fe993c3f..476651bd0a210 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -497,9 +497,8 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id,
engine->logical_mask = BIT(logical_instance);
__sprint_engine_name(engine);
- if ((engine->class == COMPUTE_CLASS && !RCS_MASK(engine->gt) &&
- __ffs(CCS_MASK(engine->gt)) == engine->instance) ||
- engine->class == RENDER_CLASS)
+ if ((engine->class == COMPUTE_CLASS || engine->class == RENDER_CLASS) &&
+ __ffs(CCS_MASK(engine->gt) | RCS_MASK(engine->gt)) == engine->instance)
engine->flags |= I915_ENGINE_FIRST_RENDER_COMPUTE;
/* features common between engines sharing EUs */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 217277329546c..3dd7699f2ad3b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -320,10 +320,6 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
if (IS_DG2_G11(gt->i915))
flags |= GUC_WA_CONTEXT_ISOLATION;
- /* Wa_18020744125 */
- if (!RCS_MASK(gt))
- flags |= GUC_WA_RCS_REGS_IN_CCS_REGS_LIST;
-
/*
* Wa_14018913170: Applicable to all platforms supported by i915 so
* don't bother testing for all X/Y/Z platforms explicitly.
--
2.43.0
^ permalink raw reply related [flat|nested] 15+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for drm/i915: cleanup dead code
2024-03-20 6:02 [CI 0/6] drm/i915: cleanup dead code Lucas De Marchi
` (5 preceding siblings ...)
2024-03-20 6:03 ` [CI 6/6] drm/i915: Remove special handling for !RCS_MASK() Lucas De Marchi
@ 2024-03-20 7:31 ` Patchwork
2024-03-20 7:31 ` ✗ Fi.CI.SPARSE: " Patchwork
` (4 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2024-03-20 7:31 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: cleanup dead code
URL : https://patchwork.freedesktop.org/series/131354/
State : warning
== Summary ==
Error: dim checkpatch failed
8f73eff2311a drm/i915: Drop dead code for xehpsdv
-:918: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#918: FILE: drivers/gpu/drm/i915/intel_uncore.c:1538:
+ 0x13400 - 0x147ff: reserved */ \
-:928: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#928: FILE: drivers/gpu/drm/i915/intel_uncore.c:1544:
+ GEN_FW_RANGE(0x16e00, 0x21fff, FORCEWAKE_RENDER), /* \
+ 0x16e00 - 0x1ffff: render \
-:929: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#929: FILE: drivers/gpu/drm/i915/intel_uncore.c:1545:
+ 0x20000 - 0x21fff: reserved */ \
total: 0 errors, 3 warnings, 0 checks, 818 lines checked
7af567a833e9 drm/i915: Remove XEHP_FWRANGES()
-:175: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#175: FILE: drivers/gpu/drm/i915/intel_uncore.c:1476:
+ GEN_FW_RANGE(0x0, 0x1fff, 0), /*
+ 0x0 - 0xaff: reserved
-:176: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#176: FILE: drivers/gpu/drm/i915/intel_uncore.c:1477:
+ 0xb00 - 0x1fff: always on */
-:180: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#180: FILE: drivers/gpu/drm/i915/intel_uncore.c:1481:
+ GEN_FW_RANGE(0x4b00, 0x51ff, 0), /*
+ 0x4b00 - 0x4fff: reserved
-:181: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#181: FILE: drivers/gpu/drm/i915/intel_uncore.c:1482:
+ 0x5000 - 0x51ff: always on */
-:186: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#186: FILE: drivers/gpu/drm/i915/intel_uncore.c:1487:
+ GEN_FW_RANGE(0x8160, 0x81ff, 0), /*
+ 0x8160 - 0x817f: reserved
-:187: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#187: FILE: drivers/gpu/drm/i915/intel_uncore.c:1488:
+ 0x8180 - 0x81ff: always on */
-:191: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#191: FILE: drivers/gpu/drm/i915/intel_uncore.c:1492:
+ GEN_FW_RANGE(0x8500, 0x8cff, FORCEWAKE_GT), /*
+ 0x8500 - 0x87ff: gt
-:193: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#193: FILE: drivers/gpu/drm/i915/intel_uncore.c:1494:
+ 0x8c80 - 0x8cff: gt (DG2 only) */
-:195: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#195: FILE: drivers/gpu/drm/i915/intel_uncore.c:1496:
+ GEN_FW_RANGE(0x8d00, 0x8fff, FORCEWAKE_RENDER), /*
+ 0x8d00 - 0x8dff: render (DG2 only)
-:196: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#196: FILE: drivers/gpu/drm/i915/intel_uncore.c:1497:
+ 0x8e00 - 0x8fff: reserved */
-:198: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#198: FILE: drivers/gpu/drm/i915/intel_uncore.c:1499:
+ GEN_FW_RANGE(0x9000, 0x94cf, FORCEWAKE_GT), /*
+ 0x9000 - 0x947f: gt
-:199: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#199: FILE: drivers/gpu/drm/i915/intel_uncore.c:1500:
+ 0x9480 - 0x94cf: reserved */
-:202: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#202: FILE: drivers/gpu/drm/i915/intel_uncore.c:1503:
+ GEN_FW_RANGE(0x9560, 0x967f, 0), /*
+ 0x9560 - 0x95ff: always on
-:203: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#203: FILE: drivers/gpu/drm/i915/intel_uncore.c:1504:
+ 0x9600 - 0x967f: reserved */
-:205: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#205: FILE: drivers/gpu/drm/i915/intel_uncore.c:1506:
+ GEN_FW_RANGE(0x9680, 0x97ff, FORCEWAKE_RENDER), /*
+ 0x9680 - 0x96ff: render
-:206: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#206: FILE: drivers/gpu/drm/i915/intel_uncore.c:1507:
+ 0x9700 - 0x97ff: reserved */
-:208: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#208: FILE: drivers/gpu/drm/i915/intel_uncore.c:1509:
+ GEN_FW_RANGE(0x9800, 0xcfff, FORCEWAKE_GT), /*
+ 0x9800 - 0xb4ff: gt
-:210: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#210: FILE: drivers/gpu/drm/i915/intel_uncore.c:1511:
+ 0xc000 - 0xcfff: gt */
-:216: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#216: FILE: drivers/gpu/drm/i915/intel_uncore.c:1517:
+ GEN_FW_RANGE(0xdd00, 0xde7f, FORCEWAKE_GT), /*
+ 0xdd00 - 0xddff: gt
-:217: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#217: FILE: drivers/gpu/drm/i915/intel_uncore.c:1518:
+ 0xde00 - 0xde7f: reserved */
-:219: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#219: FILE: drivers/gpu/drm/i915/intel_uncore.c:1520:
+ GEN_FW_RANGE(0xde80, 0xe8ff, FORCEWAKE_RENDER), /*
+ 0xde80 - 0xdfff: render
-:221: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#221: FILE: drivers/gpu/drm/i915/intel_uncore.c:1522:
+ 0xe100 - 0xe8ff: render */
-:223: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#223: FILE: drivers/gpu/drm/i915/intel_uncore.c:1524:
+ GEN_FW_RANGE(0xe900, 0xffff, FORCEWAKE_GT), /*
+ 0xe900 - 0xe9ff: gt
-:225: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#225: FILE: drivers/gpu/drm/i915/intel_uncore.c:1526:
+ 0xf000 - 0xffff: gt */
-:227: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#227: FILE: drivers/gpu/drm/i915/intel_uncore.c:1528:
+ GEN_FW_RANGE(0x10000, 0x12fff, 0), /*
+ 0x10000 - 0x11fff: reserved
-:229: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#229: FILE: drivers/gpu/drm/i915/intel_uncore.c:1530:
+ 0x12800 - 0x12fff: reserved */
-:232: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#232: FILE: drivers/gpu/drm/i915/intel_uncore.c:1533:
+ GEN_FW_RANGE(0x13200, 0x147ff, FORCEWAKE_MEDIA_VDBOX2), /*
+ 0x13200 - 0x133ff: VD2 (DG2 only)
-:233: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#233: FILE: drivers/gpu/drm/i915/intel_uncore.c:1534:
+ 0x13400 - 0x147ff: reserved */
-:236: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#236: FILE: drivers/gpu/drm/i915/intel_uncore.c:1537:
+ GEN_FW_RANGE(0x15000, 0x16dff, FORCEWAKE_GT), /*
+ 0x15000 - 0x15fff: gt (DG2 only)
-:237: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#237: FILE: drivers/gpu/drm/i915/intel_uncore.c:1538:
+ 0x16000 - 0x16dff: reserved */
-:239: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#239: FILE: drivers/gpu/drm/i915/intel_uncore.c:1540:
+ GEN_FW_RANGE(0x16e00, 0x21fff, FORCEWAKE_RENDER), /*
+ 0x16e00 - 0x1ffff: render
-:240: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#240: FILE: drivers/gpu/drm/i915/intel_uncore.c:1541:
+ 0x20000 - 0x21fff: reserved */
-:243: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#243: FILE: drivers/gpu/drm/i915/intel_uncore.c:1544:
+ GEN_FW_RANGE(0x24000, 0x2417f, 0), /*
+ 0x24000 - 0x2407f: always on
-:244: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#244: FILE: drivers/gpu/drm/i915/intel_uncore.c:1545:
+ 0x24080 - 0x2417f: reserved */
-:246: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#246: FILE: drivers/gpu/drm/i915/intel_uncore.c:1547:
+ GEN_FW_RANGE(0x24180, 0x249ff, FORCEWAKE_GT), /*
+ 0x24180 - 0x241ff: gt
-:247: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#247: FILE: drivers/gpu/drm/i915/intel_uncore.c:1548:
+ 0x24200 - 0x249ff: reserved */
-:249: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#249: FILE: drivers/gpu/drm/i915/intel_uncore.c:1550:
+ GEN_FW_RANGE(0x24a00, 0x251ff, FORCEWAKE_RENDER), /*
+ 0x24a00 - 0x24a7f: render
-:250: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#250: FILE: drivers/gpu/drm/i915/intel_uncore.c:1551:
+ 0x24a80 - 0x251ff: reserved */
-:252: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#252: FILE: drivers/gpu/drm/i915/intel_uncore.c:1553:
+ GEN_FW_RANGE(0x25200, 0x25fff, FORCEWAKE_GT), /*
+ 0x25200 - 0x252ff: gt
-:253: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#253: FILE: drivers/gpu/drm/i915/intel_uncore.c:1554:
+ 0x25300 - 0x25fff: reserved */
-:255: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#255: FILE: drivers/gpu/drm/i915/intel_uncore.c:1556:
+ GEN_FW_RANGE(0x26000, 0x2ffff, FORCEWAKE_RENDER), /*
+ 0x26000 - 0x27fff: render
-:257: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#257: FILE: drivers/gpu/drm/i915/intel_uncore.c:1558:
+ 0x2a000 - 0x2ffff: undocumented */
-:261: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#261: FILE: drivers/gpu/drm/i915/intel_uncore.c:1562:
+ GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /*
+ 0x1c0000 - 0x1c2bff: VD0
-:265: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#265: FILE: drivers/gpu/drm/i915/intel_uncore.c:1566:
+ 0x1c3f00 - 0x1c3fff: VD0 */
-:267: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#267: FILE: drivers/gpu/drm/i915/intel_uncore.c:1568:
+ GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1), /*
+ 0x1c4000 - 0x1c6bff: VD1
-:270: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#270: FILE: drivers/gpu/drm/i915/intel_uncore.c:1571:
+ 0x1c6e00 - 0x1c7fff: reserved */
-:272: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#272: FILE: drivers/gpu/drm/i915/intel_uncore.c:1573:
+ GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), /*
+ 0x1c8000 - 0x1ca0ff: VE0
-:273: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#273: FILE: drivers/gpu/drm/i915/intel_uncore.c:1574:
+ 0x1ca100 - 0x1cbfff: reserved */
-:279: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#279: FILE: drivers/gpu/drm/i915/intel_uncore.c:1580:
+ GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), /*
+ 0x1d0000 - 0x1d2bff: VD2
-:284: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#284: FILE: drivers/gpu/drm/i915/intel_uncore.c:1585:
+ 0x1d3f00 - 0x1d3fff: VD2 */
-:286: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#286: FILE: drivers/gpu/drm/i915/intel_uncore.c:1587:
+ GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3), /*
+ 0x1d4000 - 0x1d6bff: VD3
-:289: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#289: FILE: drivers/gpu/drm/i915/intel_uncore.c:1590:
+ 0x1d6e00 - 0x1d7fff: reserved */
-:291: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#291: FILE: drivers/gpu/drm/i915/intel_uncore.c:1592:
+ GEN_FW_RANGE(0x1d8000, 0x1dffff, FORCEWAKE_MEDIA_VEBOX1), /*
+ 0x1d8000 - 0x1da0ff: VE1
-:292: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#292: FILE: drivers/gpu/drm/i915/intel_uncore.c:1593:
+ 0x1da100 - 0x1dffff: reserved */
-:294: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#294: FILE: drivers/gpu/drm/i915/intel_uncore.c:1595:
+ GEN_FW_RANGE(0x1e0000, 0x1e3fff, FORCEWAKE_MEDIA_VDBOX4), /*
+ 0x1e0000 - 0x1e2bff: VD4
-:298: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#298: FILE: drivers/gpu/drm/i915/intel_uncore.c:1599:
+ 0x1e3f00 - 0x1e3fff: VD4 */
-:300: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#300: FILE: drivers/gpu/drm/i915/intel_uncore.c:1601:
+ GEN_FW_RANGE(0x1e4000, 0x1e7fff, FORCEWAKE_MEDIA_VDBOX5), /*
+ 0x1e4000 - 0x1e6bff: VD5
-:303: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#303: FILE: drivers/gpu/drm/i915/intel_uncore.c:1604:
+ 0x1e6e00 - 0x1e7fff: reserved */
-:305: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#305: FILE: drivers/gpu/drm/i915/intel_uncore.c:1606:
+ GEN_FW_RANGE(0x1e8000, 0x1effff, FORCEWAKE_MEDIA_VEBOX2), /*
+ 0x1e8000 - 0x1ea0ff: VE2
-:306: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#306: FILE: drivers/gpu/drm/i915/intel_uncore.c:1607:
+ 0x1ea100 - 0x1effff: reserved */
-:308: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#308: FILE: drivers/gpu/drm/i915/intel_uncore.c:1609:
+ GEN_FW_RANGE(0x1f0000, 0x1f3fff, FORCEWAKE_MEDIA_VDBOX6), /*
+ 0x1f0000 - 0x1f2bff: VD6
-:312: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#312: FILE: drivers/gpu/drm/i915/intel_uncore.c:1613:
+ 0x1f3f00 - 0x1f3fff: VD6 */
-:314: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#314: FILE: drivers/gpu/drm/i915/intel_uncore.c:1615:
+ GEN_FW_RANGE(0x1f4000, 0x1f7fff, FORCEWAKE_MEDIA_VDBOX7), /*
+ 0x1f4000 - 0x1f6bff: VD7
-:317: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#317: FILE: drivers/gpu/drm/i915/intel_uncore.c:1618:
+ 0x1f6e00 - 0x1f7fff: reserved */
total: 0 errors, 64 warnings, 0 checks, 304 lines checked
5221a75b289b drm/i915: Stop inheriting IP_VER(12, 50)
4fe1645b9ebc drm/i915: Update IP_VER(12, 50)
b9f80de3482e drm/i915: Drop dead code for pvc
-:422: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#422:
new file mode 100644
-:429: ERROR:TRAILING_WHITESPACE: trailing whitespace
#429: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c.rej:3:
+ $
-:437: ERROR:TRAILING_WHITESPACE: trailing whitespace
#437: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c.rej:11:
+ $
-:443: ERROR:TRAILING_WHITESPACE: trailing whitespace
#443: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c.rej:17:
+ $
total: 3 errors, 1 warnings, 0 checks, 794 lines checked
bcf5869d9d95 drm/i915: Remove special handling for !RCS_MASK()
^ permalink raw reply [flat|nested] 15+ messages in thread* ✗ Fi.CI.SPARSE: warning for drm/i915: cleanup dead code
2024-03-20 6:02 [CI 0/6] drm/i915: cleanup dead code Lucas De Marchi
` (6 preceding siblings ...)
2024-03-20 7:31 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: cleanup dead code Patchwork
@ 2024-03-20 7:31 ` Patchwork
2024-03-20 7:42 ` ✓ Fi.CI.BAT: success " Patchwork
` (3 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2024-03-20 7:31 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: cleanup dead code
URL : https://patchwork.freedesktop.org/series/131354/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 15+ messages in thread* ✓ Fi.CI.BAT: success for drm/i915: cleanup dead code
2024-03-20 6:02 [CI 0/6] drm/i915: cleanup dead code Lucas De Marchi
` (7 preceding siblings ...)
2024-03-20 7:31 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2024-03-20 7:42 ` Patchwork
2024-03-20 18:26 ` ✗ Fi.CI.IGT: failure " Patchwork
` (2 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2024-03-20 7:42 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 11595 bytes --]
== Series Details ==
Series: drm/i915: cleanup dead code
URL : https://patchwork.freedesktop.org/series/131354/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14453 -> Patchwork_131354v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/index.html
Participating hosts (37 -> 36)
------------------------------
Missing (1): fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_131354v1 that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- bat-jsl-1: [PASS][1] -> [FAIL][2] ([i915#8293])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/bat-jsl-1/boot.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-jsl-1/boot.html
#### Possible fixes ####
* boot:
- bat-arls-3: [FAIL][3] ([i915#10234]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/bat-arls-3/boot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-arls-3/boot.html
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@basic-hwmon:
- bat-arls-3: NOTRUN -> [SKIP][5] ([i915#9318])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-arls-3/igt@debugfs_test@basic-hwmon.html
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-arls-3: NOTRUN -> [SKIP][6] ([i915#10213]) +3 other tests skip
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-arls-3/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_lmem_swapping@verify-random:
- bat-mtlp-6: NOTRUN -> [SKIP][7] ([i915#4613]) +3 other tests skip
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-mtlp-6/igt@gem_lmem_swapping@verify-random.html
* igt@gem_mmap@basic:
- bat-arls-3: NOTRUN -> [SKIP][8] ([i915#4083])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-arls-3/igt@gem_mmap@basic.html
* igt@gem_render_tiled_blits@basic:
- bat-arls-3: NOTRUN -> [SKIP][9] ([i915#10197] / [i915#10211] / [i915#4079])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-arls-3/igt@gem_render_tiled_blits@basic.html
* igt@gem_tiled_blits@basic:
- bat-arls-3: NOTRUN -> [SKIP][10] ([i915#10196] / [i915#4077]) +2 other tests skip
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-arls-3/igt@gem_tiled_blits@basic.html
* igt@gem_tiled_pread_basic:
- bat-arls-3: NOTRUN -> [SKIP][11] ([i915#10206] / [i915#4079])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-arls-3/igt@gem_tiled_pread_basic.html
* igt@i915_pm_rps@basic-api:
- bat-arls-3: NOTRUN -> [SKIP][12] ([i915#10209])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-arls-3/igt@i915_pm_rps@basic-api.html
- bat-mtlp-6: NOTRUN -> [SKIP][13] ([i915#6621])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-mtlp-6/igt@i915_pm_rps@basic-api.html
* igt@kms_addfb_basic@addfb25-x-tiled-legacy:
- bat-arls-3: NOTRUN -> [SKIP][14] ([i915#10200]) +9 other tests skip
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-arls-3/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- bat-arls-3: NOTRUN -> [SKIP][15] ([i915#10202]) +1 other test skip
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-arls-3/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_dsc@dsc-basic:
- bat-arls-3: NOTRUN -> [SKIP][16] ([i915#9886])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-arls-3/igt@kms_dsc@dsc-basic.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-arls-3: NOTRUN -> [SKIP][17] ([i915#10207])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-arls-3/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-mtlp-6: NOTRUN -> [SKIP][18] ([i915#5274] / [i915#9792])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-mtlp-6/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_frontbuffer_tracking@basic:
- bat-mtlp-6: NOTRUN -> [SKIP][19] ([i915#4342] / [i915#5354] / [i915#9792])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-mtlp-6/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_pipe_crc_basic@hang-read-crc:
- bat-mtlp-6: NOTRUN -> [SKIP][20] ([i915#9792]) +7 other tests skip
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-mtlp-6/igt@kms_pipe_crc_basic@hang-read-crc.html
* igt@kms_pm_backlight@basic-brightness:
- bat-arls-3: NOTRUN -> [SKIP][21] ([i915#9812])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-arls-3/igt@kms_pm_backlight@basic-brightness.html
- bat-mtlp-6: NOTRUN -> [SKIP][22] ([i915#5354] / [i915#9792])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-mtlp-6/igt@kms_pm_backlight@basic-brightness.html
* igt@kms_psr@psr-cursor-plane-move:
- bat-mtlp-6: NOTRUN -> [SKIP][23] ([i915#9673] / [i915#9732] / [i915#9792]) +3 other tests skip
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-mtlp-6/igt@kms_psr@psr-cursor-plane-move.html
* igt@kms_psr@psr-primary-mmap-gtt:
- bat-arls-3: NOTRUN -> [SKIP][24] ([i915#9732]) +3 other tests skip
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-arls-3/igt@kms_psr@psr-primary-mmap-gtt.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-arls-3: NOTRUN -> [SKIP][25] ([i915#10208] / [i915#8809])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-arls-3/igt@kms_setmode@basic-clone-single-crtc.html
- bat-mtlp-6: NOTRUN -> [SKIP][26] ([i915#3555] / [i915#8809] / [i915#9792])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-mtlp-6/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-flip:
- bat-mtlp-6: NOTRUN -> [SKIP][27] ([i915#3708] / [i915#9792])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-mtlp-6/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-fence-mmap:
- bat-arls-3: NOTRUN -> [SKIP][28] ([i915#10196] / [i915#3708] / [i915#4077]) +1 other test skip
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-arls-3/igt@prime_vgem@basic-fence-mmap.html
- bat-mtlp-6: NOTRUN -> [SKIP][29] ([i915#3708] / [i915#4077]) +1 other test skip
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-mtlp-6/igt@prime_vgem@basic-fence-mmap.html
* igt@prime_vgem@basic-fence-read:
- bat-arls-3: NOTRUN -> [SKIP][30] ([i915#10212] / [i915#3708])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-arls-3/igt@prime_vgem@basic-fence-read.html
* igt@prime_vgem@basic-read:
- bat-arls-3: NOTRUN -> [SKIP][31] ([i915#10214] / [i915#3708])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-arls-3/igt@prime_vgem@basic-read.html
- bat-mtlp-6: NOTRUN -> [SKIP][32] ([i915#3708]) +1 other test skip
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-mtlp-6/igt@prime_vgem@basic-read.html
* igt@prime_vgem@basic-write:
- bat-arls-3: NOTRUN -> [SKIP][33] ([i915#10216] / [i915#3708])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-arls-3/igt@prime_vgem@basic-write.html
- bat-mtlp-6: NOTRUN -> [SKIP][34] ([i915#10216] / [i915#3708])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-mtlp-6/igt@prime_vgem@basic-write.html
#### Possible fixes ####
* igt@i915_selftest@live@hugepages:
- fi-apl-guc: [ABORT][35] ([i915#10461]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/fi-apl-guc/igt@i915_selftest@live@hugepages.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/fi-apl-guc/igt@i915_selftest@live@hugepages.html
[i915#10196]: https://gitlab.freedesktop.org/drm/intel/issues/10196
[i915#10197]: https://gitlab.freedesktop.org/drm/intel/issues/10197
[i915#10200]: https://gitlab.freedesktop.org/drm/intel/issues/10200
[i915#10202]: https://gitlab.freedesktop.org/drm/intel/issues/10202
[i915#10206]: https://gitlab.freedesktop.org/drm/intel/issues/10206
[i915#10207]: https://gitlab.freedesktop.org/drm/intel/issues/10207
[i915#10208]: https://gitlab.freedesktop.org/drm/intel/issues/10208
[i915#10209]: https://gitlab.freedesktop.org/drm/intel/issues/10209
[i915#10211]: https://gitlab.freedesktop.org/drm/intel/issues/10211
[i915#10212]: https://gitlab.freedesktop.org/drm/intel/issues/10212
[i915#10213]: https://gitlab.freedesktop.org/drm/intel/issues/10213
[i915#10214]: https://gitlab.freedesktop.org/drm/intel/issues/10214
[i915#10216]: https://gitlab.freedesktop.org/drm/intel/issues/10216
[i915#10234]: https://gitlab.freedesktop.org/drm/intel/issues/10234
[i915#10461]: https://gitlab.freedesktop.org/drm/intel/issues/10461
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4342]: https://gitlab.freedesktop.org/drm/intel/issues/4342
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
[i915#8809]: https://gitlab.freedesktop.org/drm/intel/issues/8809
[i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318
[i915#9673]: https://gitlab.freedesktop.org/drm/intel/issues/9673
[i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732
[i915#9792]: https://gitlab.freedesktop.org/drm/intel/issues/9792
[i915#9812]: https://gitlab.freedesktop.org/drm/intel/issues/9812
[i915#9886]: https://gitlab.freedesktop.org/drm/intel/issues/9886
Build changes
-------------
* Linux: CI_DRM_14453 -> Patchwork_131354v1
CI-20190529: 20190529
CI_DRM_14453: 67518d9ea0b8c4a01a4e304a0c71845bbabd0430 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7770: fef0422fd296f7c65724315f2a455ffb6959fb0d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_131354v1: 67518d9ea0b8c4a01a4e304a0c71845bbabd0430 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
445d00d97648 drm/i915: Remove special handling for !RCS_MASK()
48e47d9e286a drm/i915: Drop dead code for pvc
f9668cf40e29 drm/i915: Update IP_VER(12, 50)
fbb4a80ee5aa drm/i915: Stop inheriting IP_VER(12, 50)
2d7136914f5a drm/i915: Remove XEHP_FWRANGES()
d76d3ef753b5 drm/i915: Drop dead code for xehpsdv
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/index.html
[-- Attachment #2: Type: text/html, Size: 14271 bytes --]
^ permalink raw reply [flat|nested] 15+ messages in thread* ✗ Fi.CI.IGT: failure for drm/i915: cleanup dead code
2024-03-20 6:02 [CI 0/6] drm/i915: cleanup dead code Lucas De Marchi
` (8 preceding siblings ...)
2024-03-20 7:42 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2024-03-20 18:26 ` Patchwork
2024-03-22 21:28 ` [CI 0/6] " Lucas De Marchi
2024-03-25 9:56 ` Jani Nikula
11 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2024-03-20 18:26 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 86236 bytes --]
== Series Details ==
Series: drm/i915: cleanup dead code
URL : https://patchwork.freedesktop.org/series/131354/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14453_full -> Patchwork_131354v1_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_131354v1_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_131354v1_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_131354v1_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_flip@dpms-off-confusion@a-hdmi-a1:
- shard-snb: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-snb4/igt@kms_flip@dpms-off-confusion@a-hdmi-a1.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-snb7/igt@kms_flip@dpms-off-confusion@a-hdmi-a1.html
* igt@kms_flip@flip-vs-panning-vs-hang@a-hdmi-a1:
- shard-dg2: NOTRUN -> [INCOMPLETE][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-8/igt@kms_flip@flip-vs-panning-vs-hang@a-hdmi-a1.html
Known issues
------------
Here are the changes found in Patchwork_131354v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@object-reloc-keep-cache:
- shard-rkl: NOTRUN -> [SKIP][4] ([i915#8411])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-1/igt@api_intel_bb@object-reloc-keep-cache.html
- shard-dg2: NOTRUN -> [SKIP][5] ([i915#8411])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@api_intel_bb@object-reloc-keep-cache.html
* igt@api_intel_bb@render-ccs:
- shard-dg2: NOTRUN -> [FAIL][6] ([i915#10380])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-8/igt@api_intel_bb@render-ccs.html
* igt@device_reset@cold-reset-bound:
- shard-dg1: NOTRUN -> [SKIP][7] ([i915#7701])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-17/igt@device_reset@cold-reset-bound.html
* igt@device_reset@unbind-cold-reset-rebind:
- shard-dg2: NOTRUN -> [SKIP][8] ([i915#7701])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-10/igt@device_reset@unbind-cold-reset-rebind.html
* igt@drm_fdinfo@busy-check-all@ccs3:
- shard-dg2: NOTRUN -> [SKIP][9] ([i915#8414]) +19 other tests skip
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-8/igt@drm_fdinfo@busy-check-all@ccs3.html
* igt@drm_fdinfo@busy-idle-check-all@ccs0:
- shard-mtlp: NOTRUN -> [SKIP][10] ([i915#8414]) +5 other tests skip
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-3/igt@drm_fdinfo@busy-idle-check-all@ccs0.html
* igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
- shard-rkl: [PASS][11] -> [FAIL][12] ([i915#7742])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-rkl-1/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-5/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
* igt@gem_busy@semaphore:
- shard-dg1: NOTRUN -> [SKIP][13] ([i915#3936])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-17/igt@gem_busy@semaphore.html
- shard-mtlp: NOTRUN -> [SKIP][14] ([i915#3936])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-1/igt@gem_busy@semaphore.html
* igt@gem_caching@writes:
- shard-mtlp: NOTRUN -> [SKIP][15] ([i915#4873]) +1 other test skip
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-8/igt@gem_caching@writes.html
* igt@gem_ccs@block-multicopy-compressed:
- shard-dg1: NOTRUN -> [SKIP][16] ([i915#9323])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-17/igt@gem_ccs@block-multicopy-compressed.html
* igt@gem_ccs@ctrl-surf-copy:
- shard-rkl: NOTRUN -> [SKIP][17] ([i915#3555] / [i915#9323])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-1/igt@gem_ccs@ctrl-surf-copy.html
* igt@gem_ccs@suspend-resume:
- shard-mtlp: NOTRUN -> [SKIP][18] ([i915#9323])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-8/igt@gem_ccs@suspend-resume.html
* igt@gem_ccs@suspend-resume@tile64-compressed-compfmt0-smem-lmem0:
- shard-dg2: NOTRUN -> [INCOMPLETE][19] ([i915#7297])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@gem_ccs@suspend-resume@tile64-compressed-compfmt0-smem-lmem0.html
* igt@gem_close_race@multigpu-basic-process:
- shard-tglu: NOTRUN -> [SKIP][20] ([i915#7697])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-tglu-8/igt@gem_close_race@multigpu-basic-process.html
- shard-dg2: NOTRUN -> [SKIP][21] ([i915#7697])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@gem_close_race@multigpu-basic-process.html
* igt@gem_ctx_persistence@hang:
- shard-snb: NOTRUN -> [SKIP][22] ([i915#1099])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-snb2/igt@gem_ctx_persistence@hang.html
* igt@gem_ctx_sseu@engines:
- shard-rkl: NOTRUN -> [SKIP][23] ([i915#280]) +1 other test skip
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-2/igt@gem_ctx_sseu@engines.html
* igt@gem_ctx_sseu@invalid-args:
- shard-mtlp: NOTRUN -> [SKIP][24] ([i915#280])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-8/igt@gem_ctx_sseu@invalid-args.html
* igt@gem_ctx_sseu@invalid-sseu:
- shard-dg2: NOTRUN -> [SKIP][25] ([i915#280]) +2 other tests skip
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@gem_ctx_sseu@invalid-sseu.html
* igt@gem_eio@reset-stress:
- shard-snb: NOTRUN -> [FAIL][26] ([i915#8898])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-snb2/igt@gem_eio@reset-stress.html
* igt@gem_exec_balancer@bonded-false-hang:
- shard-dg1: NOTRUN -> [SKIP][27] ([i915#4812])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-16/igt@gem_exec_balancer@bonded-false-hang.html
* igt@gem_exec_balancer@bonded-sync:
- shard-dg2: NOTRUN -> [SKIP][28] ([i915#4771])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-10/igt@gem_exec_balancer@bonded-sync.html
* igt@gem_exec_balancer@noheartbeat:
- shard-dg2: NOTRUN -> [SKIP][29] ([i915#8555]) +1 other test skip
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-8/igt@gem_exec_balancer@noheartbeat.html
* igt@gem_exec_balancer@parallel-dmabuf-import-out-fence:
- shard-rkl: NOTRUN -> [SKIP][30] ([i915#4525])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-1/igt@gem_exec_balancer@parallel-dmabuf-import-out-fence.html
* igt@gem_exec_balancer@sliced:
- shard-mtlp: NOTRUN -> [SKIP][31] ([i915#4812])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-3/igt@gem_exec_balancer@sliced.html
* igt@gem_exec_capture@many-4k-incremental:
- shard-glk: NOTRUN -> [FAIL][32] ([i915#9606])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-glk5/igt@gem_exec_capture@many-4k-incremental.html
* igt@gem_exec_fair@basic-deadline:
- shard-dg1: NOTRUN -> [SKIP][33] ([i915#3539] / [i915#4852]) +1 other test skip
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-16/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-rrul:
- shard-mtlp: NOTRUN -> [SKIP][34] ([i915#4473] / [i915#4771])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-8/igt@gem_exec_fair@basic-none-rrul.html
* igt@gem_exec_fair@basic-pace:
- shard-dg2: NOTRUN -> [SKIP][35] ([i915#3539])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@gem_exec_fair@basic-pace.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-rkl: [PASS][36] -> [FAIL][37] ([i915#2842])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-rkl-1/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-5/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [PASS][38] -> [FAIL][39] ([i915#2842])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-glk5/igt@gem_exec_fair@basic-throttle@rcs0.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-glk1/igt@gem_exec_fair@basic-throttle@rcs0.html
- shard-tglu: [PASS][40] -> [FAIL][41] ([i915#2842])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-tglu-6/igt@gem_exec_fair@basic-throttle@rcs0.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-tglu-8/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_flush@basic-uc-pro-default:
- shard-dg2: NOTRUN -> [SKIP][42] ([i915#3539] / [i915#4852]) +1 other test skip
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@gem_exec_flush@basic-uc-pro-default.html
* igt@gem_exec_gttfill@multigpu-basic:
- shard-mtlp: NOTRUN -> [SKIP][43] ([i915#7697])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-3/igt@gem_exec_gttfill@multigpu-basic.html
* igt@gem_exec_reloc@basic-cpu-noreloc:
- shard-mtlp: NOTRUN -> [SKIP][44] ([i915#3281]) +7 other tests skip
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-3/igt@gem_exec_reloc@basic-cpu-noreloc.html
* igt@gem_exec_reloc@basic-gtt:
- shard-dg2: NOTRUN -> [SKIP][45] ([i915#3281]) +6 other tests skip
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@gem_exec_reloc@basic-gtt.html
- shard-rkl: NOTRUN -> [SKIP][46] ([i915#3281]) +4 other tests skip
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-1/igt@gem_exec_reloc@basic-gtt.html
* igt@gem_exec_reloc@basic-wc-read:
- shard-dg1: NOTRUN -> [SKIP][47] ([i915#3281]) +5 other tests skip
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-17/igt@gem_exec_reloc@basic-wc-read.html
* igt@gem_exec_schedule@preempt-queue-chain:
- shard-mtlp: NOTRUN -> [SKIP][48] ([i915#4537] / [i915#4812])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-8/igt@gem_exec_schedule@preempt-queue-chain.html
- shard-dg2: NOTRUN -> [SKIP][49] ([i915#4537] / [i915#4812]) +1 other test skip
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@gem_exec_schedule@preempt-queue-chain.html
* igt@gem_exec_schedule@thriceslice:
- shard-snb: NOTRUN -> [SKIP][50] +118 other tests skip
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-snb2/igt@gem_exec_schedule@thriceslice.html
* igt@gem_fence_thrash@bo-write-verify-y:
- shard-dg1: NOTRUN -> [SKIP][51] ([i915#4860])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-17/igt@gem_fence_thrash@bo-write-verify-y.html
* igt@gem_lmem_evict@dontneed-evict-race:
- shard-rkl: NOTRUN -> [SKIP][52] ([i915#4613] / [i915#7582])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-5/igt@gem_lmem_evict@dontneed-evict-race.html
* igt@gem_lmem_swapping@heavy-multi:
- shard-glk: NOTRUN -> [SKIP][53] ([i915#4613]) +1 other test skip
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-glk8/igt@gem_lmem_swapping@heavy-multi.html
* igt@gem_lmem_swapping@heavy-verify-multi-ccs:
- shard-mtlp: NOTRUN -> [SKIP][54] ([i915#4613]) +2 other tests skip
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-7/igt@gem_lmem_swapping@heavy-verify-multi-ccs.html
* igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0:
- shard-dg2: [PASS][55] -> [FAIL][56] ([i915#10378])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-dg2-6/igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-3/igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0.html
* igt@gem_lmem_swapping@parallel-multi:
- shard-tglu: NOTRUN -> [SKIP][57] ([i915#4613])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-tglu-8/igt@gem_lmem_swapping@parallel-multi.html
* igt@gem_lmem_swapping@parallel-random-verify-ccs@lmem0:
- shard-dg1: NOTRUN -> [SKIP][58] ([i915#4565])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-17/igt@gem_lmem_swapping@parallel-random-verify-ccs@lmem0.html
* igt@gem_lmem_swapping@verify-random-ccs:
- shard-rkl: NOTRUN -> [SKIP][59] ([i915#4613])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-1/igt@gem_lmem_swapping@verify-random-ccs.html
* igt@gem_media_fill@media-fill:
- shard-mtlp: NOTRUN -> [SKIP][60] ([i915#8289])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-3/igt@gem_media_fill@media-fill.html
* igt@gem_mmap_gtt@medium-copy:
- shard-dg1: NOTRUN -> [SKIP][61] ([i915#4077]) +3 other tests skip
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-16/igt@gem_mmap_gtt@medium-copy.html
* igt@gem_mmap_wc@read-write:
- shard-dg1: NOTRUN -> [SKIP][62] ([i915#4083])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-17/igt@gem_mmap_wc@read-write.html
* igt@gem_mmap_wc@write-cpu-read-wc-unflushed:
- shard-dg2: NOTRUN -> [SKIP][63] ([i915#4083]) +1 other test skip
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@gem_mmap_wc@write-cpu-read-wc-unflushed.html
* igt@gem_mmap_wc@write-read-distinct:
- shard-mtlp: NOTRUN -> [SKIP][64] ([i915#4083]) +2 other tests skip
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-7/igt@gem_mmap_wc@write-read-distinct.html
* igt@gem_partial_pwrite_pread@write:
- shard-dg2: NOTRUN -> [SKIP][65] ([i915#3282]) +4 other tests skip
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@gem_partial_pwrite_pread@write.html
* igt@gem_partial_pwrite_pread@writes-after-reads:
- shard-rkl: NOTRUN -> [SKIP][66] ([i915#3282]) +5 other tests skip
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-5/igt@gem_partial_pwrite_pread@writes-after-reads.html
* igt@gem_pread@display:
- shard-mtlp: NOTRUN -> [SKIP][67] ([i915#3282]) +2 other tests skip
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-3/igt@gem_pread@display.html
* igt@gem_pxp@create-protected-buffer:
- shard-rkl: NOTRUN -> [SKIP][68] ([i915#4270]) +1 other test skip
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-5/igt@gem_pxp@create-protected-buffer.html
* igt@gem_pxp@regular-baseline-src-copy-readible:
- shard-dg1: NOTRUN -> [SKIP][69] ([i915#4270]) +3 other tests skip
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-17/igt@gem_pxp@regular-baseline-src-copy-readible.html
* igt@gem_pxp@verify-pxp-key-change-after-suspend-resume:
- shard-dg2: NOTRUN -> [SKIP][70] ([i915#4270]) +1 other test skip
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-8/igt@gem_pxp@verify-pxp-key-change-after-suspend-resume.html
* igt@gem_pxp@verify-pxp-stale-buf-execution:
- shard-mtlp: NOTRUN -> [SKIP][71] ([i915#4270]) +3 other tests skip
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-3/igt@gem_pxp@verify-pxp-stale-buf-execution.html
* igt@gem_readwrite@read-write:
- shard-dg1: NOTRUN -> [SKIP][72] ([i915#3282])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-16/igt@gem_readwrite@read-write.html
* igt@gem_render_copy@y-tiled-ccs-to-x-tiled:
- shard-mtlp: NOTRUN -> [SKIP][73] ([i915#8428]) +2 other tests skip
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-8/igt@gem_render_copy@y-tiled-ccs-to-x-tiled.html
* igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs:
- shard-dg2: NOTRUN -> [SKIP][74] ([i915#5190] / [i915#8428]) +4 other tests skip
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-8/igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs.html
* igt@gem_set_tiling_vs_pwrite:
- shard-mtlp: NOTRUN -> [SKIP][75] ([i915#4079])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-7/igt@gem_set_tiling_vs_pwrite.html
* igt@gem_tiled_partial_pwrite_pread@writes:
- shard-dg2: NOTRUN -> [SKIP][76] ([i915#4077]) +13 other tests skip
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@gem_tiled_partial_pwrite_pread@writes.html
* igt@gem_tiled_pread_pwrite:
- shard-dg2: NOTRUN -> [SKIP][77] ([i915#4079])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@gem_tiled_pread_pwrite.html
* igt@gem_tiling_max_stride:
- shard-mtlp: NOTRUN -> [SKIP][78] ([i915#4077]) +5 other tests skip
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-7/igt@gem_tiling_max_stride.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-rkl: NOTRUN -> [SKIP][79] ([i915#3323])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-2/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-dg2: NOTRUN -> [SKIP][80] ([i915#3297]) +3 other tests skip
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@gem_userptr_blits@dmabuf-unsync.html
- shard-rkl: NOTRUN -> [SKIP][81] ([i915#3297]) +1 other test skip
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-5/igt@gem_userptr_blits@dmabuf-unsync.html
* igt@gem_userptr_blits@map-fixed-invalidate:
- shard-dg1: NOTRUN -> [SKIP][82] ([i915#3297] / [i915#4880])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-16/igt@gem_userptr_blits@map-fixed-invalidate.html
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-mtlp: NOTRUN -> [SKIP][83] ([i915#3297]) +1 other test skip
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-7/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@gen3_render_tiledy_blits:
- shard-mtlp: NOTRUN -> [SKIP][84] +13 other tests skip
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-8/igt@gen3_render_tiledy_blits.html
* igt@gen9_exec_parse@allowed-single:
- shard-mtlp: NOTRUN -> [SKIP][85] ([i915#2856]) +2 other tests skip
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-7/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@basic-rejected:
- shard-tglu: NOTRUN -> [SKIP][86] ([i915#2527] / [i915#2856])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-tglu-8/igt@gen9_exec_parse@basic-rejected.html
* igt@gen9_exec_parse@batch-without-end:
- shard-dg2: NOTRUN -> [SKIP][87] ([i915#2856]) +3 other tests skip
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@gen9_exec_parse@batch-without-end.html
* igt@gen9_exec_parse@bb-secure:
- shard-dg1: NOTRUN -> [SKIP][88] ([i915#2527]) +1 other test skip
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-17/igt@gen9_exec_parse@bb-secure.html
* igt@gen9_exec_parse@unaligned-jump:
- shard-rkl: NOTRUN -> [SKIP][89] ([i915#2527])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-2/igt@gen9_exec_parse@unaligned-jump.html
* igt@i915_module_load@load:
- shard-glk: NOTRUN -> [SKIP][90] ([i915#6227])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-glk5/igt@i915_module_load@load.html
* igt@i915_pm_freq_api@freq-suspend:
- shard-rkl: NOTRUN -> [SKIP][91] ([i915#8399])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-1/igt@i915_pm_freq_api@freq-suspend.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-bcs0:
- shard-dg1: [PASS][92] -> [FAIL][93] ([i915#3591])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-dg1-18/igt@i915_pm_rc6_residency@rc6-idle@gt0-bcs0.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-13/igt@i915_pm_rc6_residency@rc6-idle@gt0-bcs0.html
* igt@i915_pm_rps@waitboost:
- shard-mtlp: NOTRUN -> [FAIL][94] ([i915#8346])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-3/igt@i915_pm_rps@waitboost.html
* igt@i915_selftest@mock@memory_region:
- shard-dg2: NOTRUN -> [DMESG-WARN][95] ([i915#9311])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@i915_selftest@mock@memory_region.html
- shard-rkl: NOTRUN -> [DMESG-WARN][96] ([i915#9311])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-1/igt@i915_selftest@mock@memory_region.html
* igt@intel_hwmon@hwmon-read:
- shard-rkl: NOTRUN -> [SKIP][97] ([i915#7707])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-2/igt@intel_hwmon@hwmon-read.html
* igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling:
- shard-dg2: NOTRUN -> [SKIP][98] ([i915#4212]) +1 other test skip
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling.html
* igt@kms_addfb_basic@addfb25-x-tiled-legacy:
- shard-mtlp: NOTRUN -> [SKIP][99] ([i915#4212]) +1 other test skip
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-8/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-4-rc-ccs-cc:
- shard-mtlp: NOTRUN -> [SKIP][100] ([i915#8709]) +11 other tests skip
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-3/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-4-rc-ccs-cc.html
* igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
- shard-glk: NOTRUN -> [SKIP][101] ([i915#1769])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-glk5/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
* igt@kms_big_fb@4-tiled-8bpp-rotate-180:
- shard-dg1: NOTRUN -> [SKIP][102] ([i915#4538] / [i915#5286]) +2 other tests skip
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-17/igt@kms_big_fb@4-tiled-8bpp-rotate-180.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0:
- shard-mtlp: [PASS][103] -> [FAIL][104] ([i915#5138])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-mtlp-4/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
- shard-rkl: NOTRUN -> [SKIP][105] ([i915#5286]) +3 other tests skip
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-tglu: [PASS][106] -> [FAIL][107] ([i915#3743])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-tglu-8/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-tglu-3/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-270:
- shard-rkl: NOTRUN -> [SKIP][108] ([i915#3638]) +2 other tests skip
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-2/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-addfb:
- shard-dg2: NOTRUN -> [SKIP][109] ([i915#5190])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@kms_big_fb@y-tiled-addfb.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-dg2: NOTRUN -> [SKIP][110] ([i915#4538] / [i915#5190]) +9 other tests skip
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
- shard-mtlp: NOTRUN -> [SKIP][111] ([i915#6187])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-7/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180:
- shard-dg1: NOTRUN -> [SKIP][112] ([i915#4538]) +1 other test skip
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-16/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180.html
* igt@kms_big_joiner@2x-modeset:
- shard-dg1: NOTRUN -> [SKIP][113] ([i915#2705]) +1 other test skip
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-16/igt@kms_big_joiner@2x-modeset.html
* igt@kms_big_joiner@invalid-modeset:
- shard-dg2: NOTRUN -> [SKIP][114] ([i915#2705])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@kms_big_joiner@invalid-modeset.html
- shard-rkl: NOTRUN -> [SKIP][115] ([i915#2705])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-1/igt@kms_big_joiner@invalid-modeset.html
* igt@kms_ccs@bad-pixel-format-4-tiled-dg2-rc-ccs-cc@pipe-c-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][116] ([i915#6095]) +31 other tests skip
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-8/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-rc-ccs-cc@pipe-c-edp-1.html
* igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][117] ([i915#10307] / [i915#10434]) +5 other tests skip
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-10/igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@bad-rotation-90-4-tiled-mtl-mc-ccs@pipe-b-hdmi-a-3:
- shard-dg1: NOTRUN -> [SKIP][118] ([i915#6095]) +71 other tests skip
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-13/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-mc-ccs@pipe-b-hdmi-a-3.html
* igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][119] ([i915#10307]) +133 other tests skip
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-3.html
* igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][120] ([i915#6095]) +71 other tests skip
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-1/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html
* igt@kms_ccs@random-ccs-data-4-tiled-xe2-ccs:
- shard-dg1: NOTRUN -> [SKIP][121] ([i915#10278]) +1 other test skip
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-16/igt@kms_ccs@random-ccs-data-4-tiled-xe2-ccs.html
* igt@kms_cdclk@plane-scaling@pipe-d-dp-4:
- shard-dg2: NOTRUN -> [SKIP][122] ([i915#4087]) +3 other tests skip
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-11/igt@kms_cdclk@plane-scaling@pipe-d-dp-4.html
* igt@kms_chamelium_color@degamma:
- shard-dg2: NOTRUN -> [SKIP][123] +21 other tests skip
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@kms_chamelium_color@degamma.html
* igt@kms_chamelium_frames@hdmi-crc-fast:
- shard-dg2: NOTRUN -> [SKIP][124] ([i915#7828]) +4 other tests skip
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-8/igt@kms_chamelium_frames@hdmi-crc-fast.html
* igt@kms_chamelium_frames@vga-frame-dump:
- shard-dg1: NOTRUN -> [SKIP][125] ([i915#7828]) +3 other tests skip
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-17/igt@kms_chamelium_frames@vga-frame-dump.html
* igt@kms_chamelium_hpd@hdmi-hpd-enable-disable-mode:
- shard-mtlp: NOTRUN -> [SKIP][126] ([i915#7828]) +6 other tests skip
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-7/igt@kms_chamelium_hpd@hdmi-hpd-enable-disable-mode.html
* igt@kms_chamelium_hpd@vga-hpd-fast:
- shard-rkl: NOTRUN -> [SKIP][127] ([i915#7828]) +2 other tests skip
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-2/igt@kms_chamelium_hpd@vga-hpd-fast.html
* igt@kms_content_protection@atomic@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [TIMEOUT][128] ([i915#7173])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-11/igt@kms_content_protection@atomic@pipe-a-dp-4.html
* igt@kms_content_protection@dp-mst-lic-type-0:
- shard-dg2: NOTRUN -> [SKIP][129] ([i915#3299]) +1 other test skip
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@kms_content_protection@dp-mst-lic-type-0.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-rkl: NOTRUN -> [SKIP][130] ([i915#3116]) +1 other test skip
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-2/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_content_protection@lic-type-0:
- shard-mtlp: NOTRUN -> [SKIP][131] ([i915#6944] / [i915#9424])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-7/igt@kms_content_protection@lic-type-0.html
* igt@kms_content_protection@mei-interface:
- shard-mtlp: NOTRUN -> [SKIP][132] ([i915#8063] / [i915#9433])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-3/igt@kms_content_protection@mei-interface.html
* igt@kms_content_protection@uevent:
- shard-dg1: NOTRUN -> [SKIP][133] ([i915#7116] / [i915#9424])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-17/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@cursor-onscreen-32x32:
- shard-mtlp: NOTRUN -> [SKIP][134] ([i915#3555] / [i915#8814])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-7/igt@kms_cursor_crc@cursor-onscreen-32x32.html
* igt@kms_cursor_crc@cursor-onscreen-512x512:
- shard-mtlp: NOTRUN -> [SKIP][135] ([i915#3359])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-3/igt@kms_cursor_crc@cursor-onscreen-512x512.html
* igt@kms_cursor_crc@cursor-random-512x170:
- shard-dg2: NOTRUN -> [SKIP][136] ([i915#3359])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-8/igt@kms_cursor_crc@cursor-random-512x170.html
- shard-rkl: NOTRUN -> [SKIP][137] ([i915#3359])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-2/igt@kms_cursor_crc@cursor-random-512x170.html
* igt@kms_cursor_crc@cursor-rapid-movement-32x32:
- shard-dg1: NOTRUN -> [SKIP][138] ([i915#3555]) +4 other tests skip
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-17/igt@kms_cursor_crc@cursor-rapid-movement-32x32.html
* igt@kms_cursor_crc@cursor-rapid-movement-64x21:
- shard-mtlp: NOTRUN -> [SKIP][139] ([i915#8814]) +2 other tests skip
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-8/igt@kms_cursor_crc@cursor-rapid-movement-64x21.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy:
- shard-mtlp: NOTRUN -> [SKIP][140] ([i915#9809]) +1 other test skip
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-8/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic:
- shard-snb: [PASS][141] -> [ABORT][142] ([i915#8852])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-snb6/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-snb7/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [PASS][143] -> [FAIL][144] ([i915#2346]) +1 other test fail
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@forked-move@pipe-a:
- shard-glk: NOTRUN -> [DMESG-WARN][145] ([i915#10166])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-glk5/igt@kms_cursor_legacy@forked-move@pipe-a.html
* igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
- shard-mtlp: NOTRUN -> [SKIP][146] ([i915#9833])
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-3/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html
* igt@kms_display_modes@extended-mode-basic:
- shard-dg2: NOTRUN -> [SKIP][147] ([i915#3555]) +4 other tests skip
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@kms_display_modes@extended-mode-basic.html
- shard-rkl: NOTRUN -> [SKIP][148] ([i915#3555]) +4 other tests skip
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-1/igt@kms_display_modes@extended-mode-basic.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][149] ([i915#3804])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-1/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2.html
* igt@kms_draw_crc@draw-method-mmap-gtt:
- shard-dg1: NOTRUN -> [SKIP][150] ([i915#8812])
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-17/igt@kms_draw_crc@draw-method-mmap-gtt.html
* igt@kms_draw_crc@draw-method-mmap-wc:
- shard-dg2: NOTRUN -> [SKIP][151] ([i915#8812])
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-8/igt@kms_draw_crc@draw-method-mmap-wc.html
* igt@kms_dsc@dsc-with-bpc:
- shard-dg2: NOTRUN -> [SKIP][152] ([i915#3555] / [i915#3840])
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@kms_dsc@dsc-with-bpc.html
- shard-rkl: NOTRUN -> [SKIP][153] ([i915#3555] / [i915#3840])
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-5/igt@kms_dsc@dsc-with-bpc.html
* igt@kms_fbcon_fbt@psr:
- shard-dg2: NOTRUN -> [SKIP][154] ([i915#3469])
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@kms_fbcon_fbt@psr.html
* igt@kms_feature_discovery@display-3x:
- shard-dg1: NOTRUN -> [SKIP][155] ([i915#1839])
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-16/igt@kms_feature_discovery@display-3x.html
* igt@kms_feature_discovery@display-4x:
- shard-mtlp: NOTRUN -> [SKIP][156] ([i915#1839])
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-3/igt@kms_feature_discovery@display-4x.html
* igt@kms_feature_discovery@dp-mst:
- shard-dg2: NOTRUN -> [SKIP][157] ([i915#9337])
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@kms_feature_discovery@dp-mst.html
- shard-rkl: NOTRUN -> [SKIP][158] ([i915#9337])
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-1/igt@kms_feature_discovery@dp-mst.html
* igt@kms_feature_discovery@psr2:
- shard-dg1: NOTRUN -> [SKIP][159] ([i915#658])
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-17/igt@kms_feature_discovery@psr2.html
* igt@kms_flip@2x-flip-vs-dpms:
- shard-rkl: NOTRUN -> [SKIP][160] +26 other tests skip
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-2/igt@kms_flip@2x-flip-vs-dpms.html
* igt@kms_flip@2x-flip-vs-fences:
- shard-dg2: NOTRUN -> [SKIP][161] ([i915#8381])
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@kms_flip@2x-flip-vs-fences.html
* igt@kms_flip@2x-flip-vs-suspend:
- shard-mtlp: NOTRUN -> [SKIP][162] ([i915#3637])
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-7/igt@kms_flip@2x-flip-vs-suspend.html
* igt@kms_flip@2x-modeset-vs-vblank-race:
- shard-dg1: NOTRUN -> [SKIP][163] ([i915#9934]) +3 other tests skip
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-16/igt@kms_flip@2x-modeset-vs-vblank-race.html
* igt@kms_flip@flip-vs-fences-interruptible:
- shard-dg1: NOTRUN -> [SKIP][164] ([i915#8381])
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-17/igt@kms_flip@flip-vs-fences-interruptible.html
- shard-mtlp: NOTRUN -> [SKIP][165] ([i915#8381])
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-1/igt@kms_flip@flip-vs-fences-interruptible.html
* igt@kms_flip@flip-vs-suspend@b-edp1:
- shard-mtlp: [PASS][166] -> [FAIL][167] ([i915#10083])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-mtlp-2/igt@kms_flip@flip-vs-suspend@b-edp1.html
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-1/igt@kms_flip@flip-vs-suspend@b-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][168] ([i915#2672]) +2 other tests skip
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-5/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][169] ([i915#2672] / [i915#3555]) +1 other test skip
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][170] ([i915#2672]) +3 other tests skip
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][171] ([i915#2672]) +1 other test skip
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-7/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-default-mode.html
* igt@kms_force_connector_basic@prune-stale-modes:
- shard-mtlp: NOTRUN -> [SKIP][172] ([i915#5274])
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-8/igt@kms_force_connector_basic@prune-stale-modes.html
- shard-dg2: NOTRUN -> [SKIP][173] ([i915#5274])
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-wc:
- shard-dg1: NOTRUN -> [SKIP][174] ([i915#8708]) +9 other tests skip
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-16/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
- shard-dg2: [PASS][175] -> [FAIL][176] ([i915#6880])
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-dg2-8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt.html
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-indfb-fliptrack-mmap-gtt:
- shard-tglu: NOTRUN -> [SKIP][177]
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-tglu-8/igt@kms_frontbuffer_tracking@fbc-2p-indfb-fliptrack-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-cpu:
- shard-dg2: NOTRUN -> [SKIP][178] ([i915#5354]) +25 other tests skip
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbc-tiling-y:
- shard-mtlp: NOTRUN -> [SKIP][179] ([i915#10055])
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-7/igt@kms_frontbuffer_tracking@fbc-tiling-y.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt:
- shard-rkl: NOTRUN -> [SKIP][180] ([i915#1825]) +25 other tests skip
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render:
- shard-dg1: NOTRUN -> [SKIP][181] +24 other tests skip
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-17/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][182] ([i915#8708]) +4 other tests skip
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-cpu:
- shard-mtlp: NOTRUN -> [SKIP][183] ([i915#1825]) +23 other tests skip
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][184] ([i915#8708]) +17 other tests skip
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
- shard-rkl: NOTRUN -> [SKIP][185] ([i915#5439])
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
* igt@kms_frontbuffer_tracking@plane-fbc-rte:
- shard-dg2: NOTRUN -> [SKIP][186] ([i915#10070])
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@kms_frontbuffer_tracking@plane-fbc-rte.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite:
- shard-dg1: NOTRUN -> [SKIP][187] ([i915#3458]) +7 other tests skip
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-17/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-render:
- shard-dg2: NOTRUN -> [SKIP][188] ([i915#3458]) +13 other tests skip
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-render.html
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-render:
- shard-rkl: NOTRUN -> [SKIP][189] ([i915#3023]) +12 other tests skip
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-rgb565-draw-render.html
* igt@kms_hdmi_inject@inject-audio:
- shard-tglu: NOTRUN -> [SKIP][190] ([i915#433])
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-tglu-8/igt@kms_hdmi_inject@inject-audio.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-dg2: NOTRUN -> [SKIP][191] ([i915#3555] / [i915#8228])
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-1/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_hdr@static-swap:
- shard-mtlp: NOTRUN -> [SKIP][192] ([i915#3555] / [i915#8228])
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-7/igt@kms_hdr@static-swap.html
* igt@kms_panel_fitting@atomic-fastset:
- shard-dg1: NOTRUN -> [SKIP][193] ([i915#6301])
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-16/igt@kms_panel_fitting@atomic-fastset.html
* igt@kms_plane_alpha_blend@alpha-basic@pipe-c-hdmi-a-1:
- shard-glk: NOTRUN -> [FAIL][194] ([i915#7862]) +1 other test fail
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-glk8/igt@kms_plane_alpha_blend@alpha-basic@pipe-c-hdmi-a-1.html
* igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-hdmi-a-1:
- shard-glk: NOTRUN -> [FAIL][195] ([i915#4573]) +1 other test fail
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-glk5/igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-hdmi-a-1.html
* igt@kms_plane_scaling@intel-max-src-size:
- shard-dg2: NOTRUN -> [SKIP][196] ([i915#6953] / [i915#9423])
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@kms_plane_scaling@intel-max-src-size.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-a-hdmi-a-2:
- shard-dg2: NOTRUN -> [SKIP][197] ([i915#9423]) +3 other tests skip
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-3/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-a-hdmi-a-2.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][198] ([i915#5176]) +3 other tests skip
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-7/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-b-edp-1.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][199] ([i915#9423]) +5 other tests skip
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-1/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-b-hdmi-a-2.html
* igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-c-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][200] ([i915#9423]) +11 other tests skip
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-17/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-c-hdmi-a-4.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-c-dp-4:
- shard-dg2: NOTRUN -> [SKIP][201] ([i915#5235] / [i915#9423]) +11 other tests skip
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-11/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-c-dp-4.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][202] ([i915#5235]) +7 other tests skip
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-16/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-hdmi-a-4.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25@pipe-a-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][203] ([i915#5235]) +9 other tests skip
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-7/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25@pipe-a-edp-1.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][204] ([i915#5235]) +9 other tests skip
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-1/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-hdmi-a-2.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-d-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][205] ([i915#3555] / [i915#5235]) +1 other test skip
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-3/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-d-edp-1.html
* igt@kms_pm_backlight@basic-brightness:
- shard-dg1: NOTRUN -> [SKIP][206] ([i915#5354]) +1 other test skip
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-16/igt@kms_pm_backlight@basic-brightness.html
* igt@kms_pm_dc@dc6-dpms:
- shard-dg2: NOTRUN -> [SKIP][207] ([i915#5978])
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-8/igt@kms_pm_dc@dc6-dpms.html
- shard-rkl: NOTRUN -> [SKIP][208] ([i915#3361])
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-2/igt@kms_pm_dc@dc6-dpms.html
- shard-tglu: [PASS][209] -> [FAIL][210] ([i915#9295])
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-tglu-3/igt@kms_pm_dc@dc6-dpms.html
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-tglu-7/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_pm_lpsp@screens-disabled:
- shard-mtlp: NOTRUN -> [SKIP][211] ([i915#8430])
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-7/igt@kms_pm_lpsp@screens-disabled.html
* igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-rkl: NOTRUN -> [SKIP][212] ([i915#9519]) +1 other test skip
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-5/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@kms_pm_rpm@dpms-non-lpsp:
- shard-dg2: [PASS][213] -> [SKIP][214] ([i915#9519]) +1 other test skip
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-dg2-6/igt@kms_pm_rpm@dpms-non-lpsp.html
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-8/igt@kms_pm_rpm@dpms-non-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp-stress:
- shard-dg2: NOTRUN -> [SKIP][215] ([i915#9519])
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@kms_pm_rpm@modeset-lpsp-stress.html
* igt@kms_pm_rpm@modeset-non-lpsp:
- shard-mtlp: NOTRUN -> [SKIP][216] ([i915#9519])
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-8/igt@kms_pm_rpm@modeset-non-lpsp.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-rkl: [PASS][217] -> [SKIP][218] ([i915#9519]) +1 other test skip
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-rkl-1/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-5/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@kms_prime@basic-crc-hybrid:
- shard-mtlp: NOTRUN -> [SKIP][219] ([i915#6524])
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-7/igt@kms_prime@basic-crc-hybrid.html
* igt@kms_prime@basic-crc-vgem:
- shard-dg1: NOTRUN -> [SKIP][220] ([i915#6524])
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-16/igt@kms_prime@basic-crc-vgem.html
* igt@kms_prime@basic-modeset-hybrid:
- shard-tglu: NOTRUN -> [SKIP][221] ([i915#6524])
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-tglu-8/igt@kms_prime@basic-modeset-hybrid.html
- shard-dg2: NOTRUN -> [SKIP][222] ([i915#6524] / [i915#6805])
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@kms_prime@basic-modeset-hybrid.html
* igt@kms_psr2_sf@fbc-overlay-primary-update-sf-dmg-area@b-pipe-psr2-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][223] ([i915#9808]) +1 other test skip
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-3/igt@kms_psr2_sf@fbc-overlay-primary-update-sf-dmg-area@b-pipe-psr2-edp-1.html
* igt@kms_psr@fbc-psr-primary-render@edp-1:
- shard-mtlp: NOTRUN -> [SKIP][224] ([i915#9688]) +9 other tests skip
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-3/igt@kms_psr@fbc-psr-primary-render@edp-1.html
* igt@kms_psr@psr-sprite-plane-move:
- shard-tglu: NOTRUN -> [SKIP][225] ([i915#9732]) +1 other test skip
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-tglu-8/igt@kms_psr@psr-sprite-plane-move.html
* igt@kms_psr@psr-sprite-plane-onoff:
- shard-rkl: NOTRUN -> [SKIP][226] ([i915#9732]) +14 other tests skip
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-2/igt@kms_psr@psr-sprite-plane-onoff.html
* igt@kms_psr@psr2-primary-mmap-cpu:
- shard-dg1: NOTRUN -> [SKIP][227] ([i915#9732]) +9 other tests skip
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-16/igt@kms_psr@psr2-primary-mmap-cpu.html
* igt@kms_psr@psr2-primary-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][228] ([i915#9732]) +18 other tests skip
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-8/igt@kms_psr@psr2-primary-mmap-gtt.html
* igt@kms_psr@psr2-sprite-plane-onoff:
- shard-glk: NOTRUN -> [SKIP][229] +225 other tests skip
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-glk8/igt@kms_psr@psr2-sprite-plane-onoff.html
* igt@kms_rotation_crc@primary-rotation-90:
- shard-dg2: NOTRUN -> [SKIP][230] ([i915#4235])
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-8/igt@kms_rotation_crc@primary-rotation-90.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
- shard-dg1: NOTRUN -> [SKIP][231] ([i915#5289])
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-17/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
- shard-dg2: NOTRUN -> [SKIP][232] ([i915#4235] / [i915#5190])
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
- shard-rkl: NOTRUN -> [SKIP][233] ([i915#5289]) +1 other test skip
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-1/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
* igt@kms_rotation_crc@sprite-rotation-270:
- shard-mtlp: NOTRUN -> [SKIP][234] ([i915#4235]) +2 other tests skip
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-8/igt@kms_rotation_crc@sprite-rotation-270.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-mtlp: NOTRUN -> [SKIP][235] ([i915#8623])
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-8/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
- shard-dg2: NOTRUN -> [SKIP][236] ([i915#8623])
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1:
- shard-tglu: [PASS][237] -> [FAIL][238] ([i915#9196])
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-tglu-2/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-tglu-4/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html
* igt@kms_writeback@writeback-check-output:
- shard-dg2: NOTRUN -> [SKIP][239] ([i915#2437]) +1 other test skip
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@kms_writeback@writeback-check-output.html
- shard-tglu: NOTRUN -> [SKIP][240] ([i915#2437])
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-tglu-8/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-check-output-xrgb2101010:
- shard-dg2: NOTRUN -> [SKIP][241] ([i915#2437] / [i915#9412])
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@kms_writeback@writeback-check-output-xrgb2101010.html
- shard-rkl: NOTRUN -> [SKIP][242] ([i915#2437] / [i915#9412])
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-1/igt@kms_writeback@writeback-check-output-xrgb2101010.html
* igt@kms_writeback@writeback-fb-id:
- shard-rkl: NOTRUN -> [SKIP][243] ([i915#2437])
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-2/igt@kms_writeback@writeback-fb-id.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-glk: NOTRUN -> [SKIP][244] ([i915#2437])
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-glk8/igt@kms_writeback@writeback-invalid-parameters.html
* igt@perf@global-sseu-config-invalid:
- shard-mtlp: NOTRUN -> [SKIP][245] ([i915#7387])
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-8/igt@perf@global-sseu-config-invalid.html
- shard-dg2: NOTRUN -> [SKIP][246] ([i915#7387])
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@perf@global-sseu-config-invalid.html
* igt@perf@unprivileged-single-ctx-counters:
- shard-rkl: NOTRUN -> [SKIP][247] ([i915#2433])
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-2/igt@perf@unprivileged-single-ctx-counters.html
* igt@perf_pmu@cpu-hotplug:
- shard-mtlp: NOTRUN -> [SKIP][248] ([i915#8850])
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-8/igt@perf_pmu@cpu-hotplug.html
* igt@perf_pmu@faulting-read@gtt:
- shard-mtlp: NOTRUN -> [SKIP][249] ([i915#8440])
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-7/igt@perf_pmu@faulting-read@gtt.html
* igt@perf_pmu@frequency@gt0:
- shard-dg1: NOTRUN -> [FAIL][250] ([i915#6806])
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-16/igt@perf_pmu@frequency@gt0.html
* igt@prime_vgem@basic-write:
- shard-mtlp: NOTRUN -> [SKIP][251] ([i915#10216] / [i915#3708])
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-3/igt@prime_vgem@basic-write.html
* igt@prime_vgem@fence-flip-hang:
- shard-mtlp: NOTRUN -> [SKIP][252] ([i915#3708])
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-7/igt@prime_vgem@fence-flip-hang.html
* igt@sriov_basic@enable-vfs-autoprobe-on:
- shard-mtlp: NOTRUN -> [SKIP][253] ([i915#9917])
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-3/igt@sriov_basic@enable-vfs-autoprobe-on.html
* igt@syncobj_timeline@invalid-wait-zero-handles:
- shard-dg2: NOTRUN -> [FAIL][254] ([i915#9781])
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@syncobj_timeline@invalid-wait-zero-handles.html
- shard-rkl: NOTRUN -> [FAIL][255] ([i915#9781])
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-1/igt@syncobj_timeline@invalid-wait-zero-handles.html
* igt@v3d/v3d_submit_cl@bad-extension:
- shard-dg1: NOTRUN -> [SKIP][256] ([i915#2575]) +5 other tests skip
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-17/igt@v3d/v3d_submit_cl@bad-extension.html
* igt@v3d/v3d_submit_cl@bad-multisync-out-sync:
- shard-dg2: NOTRUN -> [SKIP][257] ([i915#2575]) +11 other tests skip
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@v3d/v3d_submit_cl@bad-multisync-out-sync.html
* igt@v3d/v3d_submit_cl@valid-multisync-submission:
- shard-tglu: NOTRUN -> [SKIP][258] ([i915#2575])
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-tglu-8/igt@v3d/v3d_submit_cl@valid-multisync-submission.html
* igt@v3d/v3d_submit_csd@bad-pad:
- shard-mtlp: NOTRUN -> [SKIP][259] ([i915#2575]) +8 other tests skip
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-8/igt@v3d/v3d_submit_csd@bad-pad.html
* igt@vc4/vc4_create_bo@create-bo-4096:
- shard-mtlp: NOTRUN -> [SKIP][260] ([i915#7711]) +5 other tests skip
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-3/igt@vc4/vc4_create_bo@create-bo-4096.html
* igt@vc4/vc4_create_bo@create-bo-zeroed:
- shard-rkl: NOTRUN -> [SKIP][261] ([i915#7711]) +4 other tests skip
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-2/igt@vc4/vc4_create_bo@create-bo-zeroed.html
* igt@vc4/vc4_mmap@mmap-bo:
- shard-dg2: NOTRUN -> [SKIP][262] ([i915#7711]) +4 other tests skip
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@vc4/vc4_mmap@mmap-bo.html
* igt@vc4/vc4_perfmon@create-two-perfmon:
- shard-dg1: NOTRUN -> [SKIP][263] ([i915#7711]) +3 other tests skip
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-17/igt@vc4/vc4_perfmon@create-two-perfmon.html
#### Possible fixes ####
* igt@gem_eio@kms:
- shard-tglu: [INCOMPLETE][264] -> [PASS][265]
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-tglu-10/igt@gem_eio@kms.html
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-tglu-8/igt@gem_eio@kms.html
* igt@gem_eio@unwedge-stress:
- shard-dg1: [FAIL][266] ([i915#5784]) -> [PASS][267]
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-dg1-13/igt@gem_eio@unwedge-stress.html
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-18/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-rkl: [FAIL][268] ([i915#2842]) -> [PASS][269]
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-rkl-1/igt@gem_exec_fair@basic-none-solo@rcs0.html
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-6/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][270] ([i915#2842]) -> [PASS][271]
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-tglu: [FAIL][272] ([i915#2842]) -> [PASS][273]
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-tglu-7/igt@gem_exec_fair@basic-pace@rcs0.html
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-tglu-3/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_lmem_swapping@heavy-verify-random@lmem0:
- shard-dg2: [FAIL][274] ([i915#10378]) -> [PASS][275] +1 other test pass
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-dg2-3/igt@gem_lmem_swapping@heavy-verify-random@lmem0.html
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-11/igt@gem_lmem_swapping@heavy-verify-random@lmem0.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg1: [DMESG-WARN][276] ([i915#4936] / [i915#5493]) -> [PASS][277]
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-dg1-16/igt@gem_lmem_swapping@smem-oom@lmem0.html
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-15/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [ABORT][278] ([i915#5566]) -> [PASS][279]
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-glk2/igt@gen9_exec_parse@allowed-single.html
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-glk5/igt@gen9_exec_parse@allowed-single.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-tglu: [INCOMPLETE][280] ([i915#9820]) -> [PASS][281]
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-tglu-6/igt@i915_module_load@reload-with-fault-injection.html
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-tglu-8/igt@i915_module_load@reload-with-fault-injection.html
- shard-dg2: [INCOMPLETE][282] ([i915#9820] / [i915#9849]) -> [PASS][283]
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-dg2-10/igt@i915_module_load@reload-with-fault-injection.html
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-6/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0:
- shard-dg1: [FAIL][284] ([i915#3591]) -> [PASS][285]
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-dg1-18/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-13/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-mtlp: [FAIL][286] ([i915#3743]) -> [PASS][287]
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-mtlp-3/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-mtlp-3/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-rkl: [ABORT][288] -> [PASS][289]
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-rkl-3/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-5/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-tglu: [FAIL][290] ([i915#3743]) -> [PASS][291] +3 other tests pass
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-tglu-3/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-tglu-5/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank@ab-vga1-hdmi-a1:
- shard-snb: [ABORT][292] -> [PASS][293] +1 other test pass
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-snb7/igt@kms_flip@2x-flip-vs-absolute-wf_vblank@ab-vga1-hdmi-a1.html
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-snb7/igt@kms_flip@2x-flip-vs-absolute-wf_vblank@ab-vga1-hdmi-a1.html
* igt@kms_flip@wf_vblank-ts-check-interruptible@b-vga1:
- shard-snb: [FAIL][294] ([i915#2122]) -> [PASS][295] +1 other test pass
[294]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-snb7/igt@kms_flip@wf_vblank-ts-check-interruptible@b-vga1.html
[295]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-snb1/igt@kms_flip@wf_vblank-ts-check-interruptible@b-vga1.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
- shard-dg2: [FAIL][296] ([i915#6880]) -> [PASS][297]
[296]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen.html
[297]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen.html
* igt@kms_plane_lowres@tiling-none@pipe-b-hdmi-a-1:
- shard-dg2: [INCOMPLETE][298] -> [PASS][299]
[298]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-dg2-10/igt@kms_plane_lowres@tiling-none@pipe-b-hdmi-a-1.html
[299]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-10/igt@kms_plane_lowres@tiling-none@pipe-b-hdmi-a-1.html
* igt@kms_pm_rpm@dpms-lpsp:
- shard-dg2: [SKIP][300] ([i915#9519]) -> [PASS][301]
[300]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-dg2-2/igt@kms_pm_rpm@dpms-lpsp.html
[301]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-8/igt@kms_pm_rpm@dpms-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp:
- shard-rkl: [SKIP][302] ([i915#9519]) -> [PASS][303] +3 other tests pass
[302]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-rkl-6/igt@kms_pm_rpm@modeset-lpsp.html
[303]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-2/igt@kms_pm_rpm@modeset-lpsp.html
* igt@kms_sysfs_edid_timing:
- shard-dg2: [FAIL][304] ([IGT#2]) -> [PASS][305]
[304]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-dg2-8/igt@kms_sysfs_edid_timing.html
[305]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-11/igt@kms_sysfs_edid_timing.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1:
- shard-snb: [FAIL][306] ([i915#9196]) -> [PASS][307]
[306]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-snb7/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html
[307]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-snb1/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html
* igt@perf_pmu@enable-race@rcs0:
- shard-dg1: [INCOMPLETE][308] ([i915#9853]) -> [PASS][309]
[308]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-dg1-13/igt@perf_pmu@enable-race@rcs0.html
[309]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-17/igt@perf_pmu@enable-race@rcs0.html
#### Warnings ####
* igt@gem_create@create-ext-cpu-access-big:
- shard-dg2: [INCOMPLETE][310] ([i915#9364]) -> [ABORT][311] ([i915#9846])
[310]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-dg2-6/igt@gem_create@create-ext-cpu-access-big.html
[311]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-8/igt@gem_create@create-ext-cpu-access-big.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-dg1: [INCOMPLETE][312] ([i915#9820] / [i915#9849]) -> [ABORT][313] ([i915#9820])
[312]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-dg1-18/igt@i915_module_load@reload-with-fault-injection.html
[313]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg1-13/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0:
- shard-tglu: [WARN][314] ([i915#2681]) -> [FAIL][315] ([i915#3591])
[314]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-tglu-3/igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0.html
[315]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-tglu-5/igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-rkl: [SKIP][316] ([i915#4816]) -> [SKIP][317] ([i915#4070] / [i915#4816])
[316]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-rkl-3/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
[317]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-rkl-1/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_psr@fbc-psr-primary-mmap-cpu:
- shard-dg2: [SKIP][318] ([i915#9673] / [i915#9732]) -> [SKIP][319] ([i915#9732]) +4 other tests skip
[318]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-dg2-11/igt@kms_psr@fbc-psr-primary-mmap-cpu.html
[319]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-1/igt@kms_psr@fbc-psr-primary-mmap-cpu.html
* igt@kms_psr@fbc-psr2-sprite-blt:
- shard-dg2: [SKIP][320] ([i915#9732]) -> [SKIP][321] ([i915#9673] / [i915#9732]) +12 other tests skip
[320]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/shard-dg2-3/igt@kms_psr@fbc-psr2-sprite-blt.html
[321]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/shard-dg2-11/igt@kms_psr@fbc-psr2-sprite-blt.html
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[i915#10055]: https://gitlab.freedesktop.org/drm/intel/issues/10055
[i915#10070]: https://gitlab.freedesktop.org/drm/intel/issues/10070
[i915#10083]: https://gitlab.freedesktop.org/drm/intel/issues/10083
[i915#10166]: https://gitlab.freedesktop.org/drm/intel/issues/10166
[i915#10216]: https://gitlab.freedesktop.org/drm/intel/issues/10216
[i915#10278]: https://gitlab.freedesktop.org/drm/intel/issues/10278
[i915#10307]: https://gitlab.freedesktop.org/drm/intel/issues/10307
[i915#10378]: https://gitlab.freedesktop.org/drm/intel/issues/10378
[i915#10380]: https://gitlab.freedesktop.org/drm/intel/issues/10380
[i915#10434]: https://gitlab.freedesktop.org/drm/intel/issues/10434
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4087]: https://gitlab.freedesktop.org/drm/intel/issues/4087
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
[i915#4473]: https://gitlab.freedesktop.org/drm/intel/issues/4473
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4537]: https://gitlab.freedesktop.org/drm/intel/issues/4537
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4573]: https://gitlab.freedesktop.org/drm/intel/issues/4573
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4936]: https://gitlab.freedesktop.org/drm/intel/issues/4936
[i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#5978]: https://gitlab.freedesktop.org/drm/intel/issues/5978
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6187]: https://gitlab.freedesktop.org/drm/intel/issues/6187
[i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6805]: https://gitlab.freedesktop.org/drm/intel/issues/6805
[i915#6806]: https://gitlab.freedesktop.org/drm/intel/issues/6806
[i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173
[i915#7297]: https://gitlab.freedesktop.org/drm/intel/issues/7297
[i915#7387]: https://gitlab.freedesktop.org/drm/intel/issues/7387
[i915#7582]: https://gitlab.freedesktop.org/drm/intel/issues/7582
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
[i915#7707]: https://gitlab.freedesktop.org/drm/intel/issues/7707
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7862]: https://gitlab.freedesktop.org/drm/intel/issues/7862
[i915#8063]: https://gitlab.freedesktop.org/drm/intel/issues/8063
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8289]: https://gitlab.freedesktop.org/drm/intel/issues/8289
[i915#8346]: https://gitlab.freedesktop.org/drm/intel/issues/8346
[i915#8381]: https://gitlab.freedesktop.org/drm/intel/issues/8381
[i915#8399]: https://gitlab.freedesktop.org/drm/intel/issues/8399
[i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411
[i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428
[i915#8430]: https://gitlab.freedesktop.org/drm/intel/issues/8430
[i915#8440]: https://gitlab.freedesktop.org/drm/intel/issues/8440
[i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555
[i915#8623]: https://gitlab.freedesktop.org/drm/intel/issues/8623
[i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/intel/issues/8709
[i915#8812]: https://gitlab.freedesktop.org/drm/intel/issues/8812
[i915#8814]: https://gitlab.freedesktop.org/drm/intel/issues/8814
[i915#8850]: https://gitlab.freedesktop.org/drm/intel/issues/8850
[i915#8852]: https://gitlab.freedesktop.org/drm/intel/issues/8852
[i915#8898]: https://gitlab.freedesktop.org/drm/intel/issues/8898
[i915#9196]: https://gitlab.freedesktop.org/drm/intel/issues/9196
[i915#9295]: https://gitlab.freedesktop.org/drm/intel/issues/9295
[i915#9311]: https://gitlab.freedesktop.org/drm/intel/issues/9311
[i915#9323]: https://gitlab.freedesktop.org/drm/intel/issues/9323
[i915#9337]: https://gitlab.freedesktop.org/drm/intel/issues/9337
[i915#9364]: https://gitlab.freedesktop.org/drm/intel/issues/9364
[i915#9412]: https://gitlab.freedesktop.org/drm/intel/issues/9412
[i915#9423]: https://gitlab.freedesktop.org/drm/intel/issues/9423
[i915#9424]: https://gitlab.freedesktop.org/drm/intel/issues/9424
[i915#9433]: https://gitlab.freedesktop.org/drm/intel/issues/9433
[i915#9519]: https://gitlab.freedesktop.org/drm/intel/issues/9519
[i915#9606]: https://gitlab.freedesktop.org/drm/intel/issues/9606
[i915#9673]: https://gitlab.freedesktop.org/drm/intel/issues/9673
[i915#9688]: https://gitlab.freedesktop.org/drm/intel/issues/9688
[i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732
[i915#9781]: https://gitlab.freedesktop.org/drm/intel/issues/9781
[i915#9808]: https://gitlab.freedesktop.org/drm/intel/issues/9808
[i915#9809]: https://gitlab.freedesktop.org/drm/intel/issues/9809
[i915#9820]: https://gitlab.freedesktop.org/drm/intel/issues/9820
[i915#9833]: https://gitlab.freedesktop.org/drm/intel/issues/9833
[i915#9846]: https://gitlab.freedesktop.org/drm/intel/issues/9846
[i915#9849]: https://gitlab.freedesktop.org/drm/intel/issues/9849
[i915#9853]: https://gitlab.freedesktop.org/drm/intel/issues/9853
[i915#9917]: https://gitlab.freedesktop.org/drm/intel/issues/9917
[i915#9934]: https://gitlab.freedesktop.org/drm/intel/issues/9934
Build changes
-------------
* Linux: CI_DRM_14453 -> Patchwork_131354v1
CI-20190529: 20190529
CI_DRM_14453: 67518d9ea0b8c4a01a4e304a0c71845bbabd0430 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7770: fef0422fd296f7c65724315f2a455ffb6959fb0d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_131354v1: 67518d9ea0b8c4a01a4e304a0c71845bbabd0430 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/index.html
[-- Attachment #2: Type: text/html, Size: 103086 bytes --]
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [CI 0/6] drm/i915: cleanup dead code
2024-03-20 6:02 [CI 0/6] drm/i915: cleanup dead code Lucas De Marchi
` (9 preceding siblings ...)
2024-03-20 18:26 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2024-03-22 21:28 ` Lucas De Marchi
2024-03-25 9:56 ` Jani Nikula
11 siblings, 0 replies; 15+ messages in thread
From: Lucas De Marchi @ 2024-03-22 21:28 UTC (permalink / raw)
To: intel-gfx
On Tue, Mar 19, 2024 at 11:02:57PM -0700, Lucas De Marchi wrote:
>For CI coverage. No change from previous version except the rebase.
>See 20240312235145.2443975-1-lucas.demarchi@intel.com
>and 20240312235145.2443975-1-lucas.demarchi@intel.com for details.
>
>I will probably wait the drm-next backmerge anyway so drm-intel-next and
>drm-intel-gt-next are back in sync.
Unrelated failure in CI. This is now applied to drm-intel-next. Thank
you all for review and acks. There were minor conflicts with
drm-intel-gt-next due to workarounds applied there (and still not in
drm-next).
Lucas De Marchi
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [CI 0/6] drm/i915: cleanup dead code
2024-03-20 6:02 [CI 0/6] drm/i915: cleanup dead code Lucas De Marchi
` (10 preceding siblings ...)
2024-03-22 21:28 ` [CI 0/6] " Lucas De Marchi
@ 2024-03-25 9:56 ` Jani Nikula
2024-03-25 13:19 ` Lucas De Marchi
11 siblings, 1 reply; 15+ messages in thread
From: Jani Nikula @ 2024-03-25 9:56 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx
On Tue, 19 Mar 2024, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> .../gpu/drm/i915/gt/intel_workarounds.c.rej | 18 +
> create mode 100644 drivers/gpu/drm/i915/gt/intel_workarounds.c.rej
Whoops. [1]
BR,
Jani.
[1] https://lore.kernel.org/r/20240325083435.4f970eec@canb.auug.org.au
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [CI 0/6] drm/i915: cleanup dead code
2024-03-25 9:56 ` Jani Nikula
@ 2024-03-25 13:19 ` Lucas De Marchi
2024-03-25 13:37 ` Jani Nikula
0 siblings, 1 reply; 15+ messages in thread
From: Lucas De Marchi @ 2024-03-25 13:19 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Mon, Mar 25, 2024 at 11:56:51AM +0200, Jani Nikula wrote:
>On Tue, 19 Mar 2024, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>> .../gpu/drm/i915/gt/intel_workarounds.c.rej | 18 +
>> create mode 100644 drivers/gpu/drm/i915/gt/intel_workarounds.c.rej
>
>Whoops. [1]
argh... sorry about that. Should I just amend the commit removing it? Or
a real fix on top?
Lucas De Marchi
>
>BR,
>Jani.
>
>
>
>[1] https://lore.kernel.org/r/20240325083435.4f970eec@canb.auug.org.au
>
>
>--
>Jani Nikula, Intel
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [CI 0/6] drm/i915: cleanup dead code
2024-03-25 13:19 ` Lucas De Marchi
@ 2024-03-25 13:37 ` Jani Nikula
0 siblings, 0 replies; 15+ messages in thread
From: Jani Nikula @ 2024-03-25 13:37 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Mon, 25 Mar 2024, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> On Mon, Mar 25, 2024 at 11:56:51AM +0200, Jani Nikula wrote:
>>On Tue, 19 Mar 2024, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>>> .../gpu/drm/i915/gt/intel_workarounds.c.rej | 18 +
>>> create mode 100644 drivers/gpu/drm/i915/gt/intel_workarounds.c.rej
>>
>>Whoops. [1]
>
>
> argh... sorry about that. Should I just amend the commit removing it? Or
> a real fix on top?
No force pushes, so a fix please.
BR,
Jani.
>
> Lucas De Marchi
>
>
>>
>>BR,
>>Jani.
>>
>>
>>
>>[1] https://lore.kernel.org/r/20240325083435.4f970eec@canb.auug.org.au
>>
>>
>>--
>>Jani Nikula, Intel
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 15+ messages in thread