From: Thomas Gleixner <tglx@linutronix.de>
To: Anup Patel <apatel@ventanamicro.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Frank Rowand <frowand.list@gmail.com>
Cc: "Anup Patel" <apatel@ventanamicro.com>,
devicetree@vger.kernel.org, "Conor Dooley" <conor+dt@kernel.org>,
"Saravana Kannan" <saravanak@google.com>,
"Marc Zyngier" <maz@kernel.org>,
"Anup Patel" <anup@brainfault.org>,
"Atish Patra" <atishp@rivosinc.com>,
linux-kernel@vger.kernel.org, "Björn Töpel" <bjorn@kernel.org>,
"Atish Patra" <atishp@atishpatra.org>,
linux-riscv@lists.infradead.org,
"Andrew Jones" <ajones@ventanamicro.com>
Subject: Re: [PATCH 1/3] RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs
Date: Fri, 27 Oct 2023 09:59:40 +0200 [thread overview]
Message-ID: <87y1fo3383.ffs@tglx> (raw)
In-Reply-To: <20231025142820.390238-2-apatel@ventanamicro.com>
On Wed, Oct 25 2023 at 19:58, Anup Patel wrote:
> The riscv_of_processor_hartid() used by riscv_of_parent_hartid() fails
> for HARTs disabled in the DT. This results in the following warning
> thrown by the RISC-V INTC driver for the E-core on SiFive boards:
>
> [ 0.000000] riscv-intc: unable to find hart id for /cpus/cpu@0/interrupt-controller
>
> The riscv_of_parent_hartid() is only expected to read the hartid from
> the DT so we should directly call of_get_cpu_hwid() instead of calling
We should? Or maybe not?
Please write precise changelogs and use imperative wording as documented
in Documentation/process.
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WARNING: multiple messages have this Message-ID (diff)
From: Thomas Gleixner <tglx@linutronix.de>
To: Anup Patel <apatel@ventanamicro.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Frank Rowand <frowand.list@gmail.com>
Cc: "Conor Dooley" <conor+dt@kernel.org>,
"Marc Zyngier" <maz@kernel.org>, "Björn Töpel" <bjorn@kernel.org>,
"Atish Patra" <atishp@atishpatra.org>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Sunil V L" <sunilvl@ventanamicro.com>,
"Saravana Kannan" <saravanak@google.com>,
"Anup Patel" <anup@brainfault.org>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org,
"Anup Patel" <apatel@ventanamicro.com>,
"Atish Patra" <atishp@rivosinc.com>
Subject: Re: [PATCH 1/3] RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs
Date: Fri, 27 Oct 2023 09:59:40 +0200 [thread overview]
Message-ID: <87y1fo3383.ffs@tglx> (raw)
In-Reply-To: <20231025142820.390238-2-apatel@ventanamicro.com>
On Wed, Oct 25 2023 at 19:58, Anup Patel wrote:
> The riscv_of_processor_hartid() used by riscv_of_parent_hartid() fails
> for HARTs disabled in the DT. This results in the following warning
> thrown by the RISC-V INTC driver for the E-core on SiFive boards:
>
> [ 0.000000] riscv-intc: unable to find hart id for /cpus/cpu@0/interrupt-controller
>
> The riscv_of_parent_hartid() is only expected to read the hartid from
> the DT so we should directly call of_get_cpu_hwid() instead of calling
We should? Or maybe not?
Please write precise changelogs and use imperative wording as documented
in Documentation/process.
next prev parent reply other threads:[~2023-10-27 7:59 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-25 14:28 [PATCH 0/3] Linux RISC-V AIA Preparatory Series Anup Patel
2023-10-25 14:28 ` Anup Patel
2023-10-25 14:28 ` [PATCH 1/3] RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs Anup Patel
2023-10-25 14:28 ` Anup Patel
2023-10-27 7:59 ` Thomas Gleixner [this message]
2023-10-27 7:59 ` Thomas Gleixner
2023-10-27 14:38 ` Anup Patel
2023-10-25 14:28 ` [PATCH 2/3] of: property: Add fw_devlink support for msi-parent Anup Patel
2023-10-25 14:28 ` Anup Patel
2023-10-27 7:57 ` Thomas Gleixner
2023-10-27 7:57 ` Thomas Gleixner
2023-10-27 15:31 ` Anup Patel
2023-10-27 17:29 ` Thomas Gleixner
2023-10-27 17:29 ` Thomas Gleixner
2023-10-25 14:28 ` [PATCH 3/3] irqchip/sifive-plic: Fix syscore registration for multi-socket systems Anup Patel
2023-10-25 14:28 ` Anup Patel
2023-10-27 8:17 ` [tip: irq/core] " tip-bot2 for Anup Patel
2023-10-25 14:31 ` [PATCH 0/3] Linux RISC-V AIA Preparatory Series Anup Patel
2023-10-25 14:31 ` Anup Patel
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