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From: Francisco Jerez <currojerez@riseup.net>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Cc: stable@vger.kernel.org, Chris Wilson <chris@chris-wilson.co.uk>
Subject: Re: [Intel-gfx] [PATCH] drm/i915/gt: Update PMINTRMSK holding fw
Date: Wed, 15 Apr 2020 12:14:27 -0700	[thread overview]
Message-ID: <87y2qwy31o.fsf@riseup.net> (raw)
In-Reply-To: <20200415075018.7636-1-chris@chris-wilson.co.uk>


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Chris Wilson <chris@chris-wilson.co.uk> writes:

> If we use a non-forcewaked write to PMINTRMSK, it does not take effect
> until much later, if at all, causing a loss of RPS interrupts and no GPU
> reclocking, leaving the GPU running at the wrong frequency for long
> periods of time.
>
> Reported-by: Francisco Jerez <currojerez@riseup.net>
> Suggested-by: Francisco Jerez <currojerez@riseup.net>
> Fixes: 35cc7f32c298 ("drm/i915/gt: Use non-forcewake writes for RPS")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

Reviewed-by: Francisco Jerez <currojerez@riseup.net>

> Cc: Francisco Jerez <currojerez@riseup.net>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Andi Shyti <andi.shyti@intel.com>
> Cc: <stable@vger.kernel.org> # v5.6+
> ---
>  drivers/gpu/drm/i915/gt/intel_rps.c | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> index 86110458e2a7..6a3505467406 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -81,13 +81,14 @@ static void rps_enable_interrupts(struct intel_rps *rps)
>  		events = (GEN6_PM_RP_UP_THRESHOLD |
>  			  GEN6_PM_RP_DOWN_THRESHOLD |
>  			  GEN6_PM_RP_DOWN_TIMEOUT);
> -
>  	WRITE_ONCE(rps->pm_events, events);
> +
>  	spin_lock_irq(&gt->irq_lock);
>  	gen6_gt_pm_enable_irq(gt, rps->pm_events);
>  	spin_unlock_irq(&gt->irq_lock);
>  
> -	set(gt->uncore, GEN6_PMINTRMSK, rps_pm_mask(rps, rps->cur_freq));
> +	intel_uncore_write(gt->uncore,
> +                           GEN6_PMINTRMSK, rps_pm_mask(rps, rps->last_freq));
>  }
>  
>  static void gen6_rps_reset_interrupts(struct intel_rps *rps)
> @@ -120,7 +121,9 @@ static void rps_disable_interrupts(struct intel_rps *rps)
>  	struct intel_gt *gt = rps_to_gt(rps);
>  
>  	WRITE_ONCE(rps->pm_events, 0);
> -	set(gt->uncore, GEN6_PMINTRMSK, rps_pm_sanitize_mask(rps, ~0u));
> +
> +	intel_uncore_write(gt->uncore,
> +                           GEN6_PMINTRMSK, rps_pm_sanitize_mask(rps, ~0u));
>  
>  	spin_lock_irq(&gt->irq_lock);
>  	gen6_gt_pm_disable_irq(gt, GEN6_PM_RPS_EVENTS);
> -- 
> 2.20.1

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WARNING: multiple messages have this Message-ID (diff)
From: Francisco Jerez <currojerez@riseup.net>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Cc: Chris Wilson <chris@chris-wilson.co.uk>,
	Mika Kuoppala <mika.kuoppala@linux.intel.com>,
	Andi Shyti <andi.shyti@intel.com>,
	stable@vger.kernel.org
Subject: Re: [PATCH] drm/i915/gt: Update PMINTRMSK holding fw
Date: Wed, 15 Apr 2020 12:14:27 -0700	[thread overview]
Message-ID: <87y2qwy31o.fsf@riseup.net> (raw)
In-Reply-To: <20200415075018.7636-1-chris@chris-wilson.co.uk>


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Chris Wilson <chris@chris-wilson.co.uk> writes:

> If we use a non-forcewaked write to PMINTRMSK, it does not take effect
> until much later, if at all, causing a loss of RPS interrupts and no GPU
> reclocking, leaving the GPU running at the wrong frequency for long
> periods of time.
>
> Reported-by: Francisco Jerez <currojerez@riseup.net>
> Suggested-by: Francisco Jerez <currojerez@riseup.net>
> Fixes: 35cc7f32c298 ("drm/i915/gt: Use non-forcewake writes for RPS")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

Reviewed-by: Francisco Jerez <currojerez@riseup.net>

> Cc: Francisco Jerez <currojerez@riseup.net>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Andi Shyti <andi.shyti@intel.com>
> Cc: <stable@vger.kernel.org> # v5.6+
> ---
>  drivers/gpu/drm/i915/gt/intel_rps.c | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> index 86110458e2a7..6a3505467406 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -81,13 +81,14 @@ static void rps_enable_interrupts(struct intel_rps *rps)
>  		events = (GEN6_PM_RP_UP_THRESHOLD |
>  			  GEN6_PM_RP_DOWN_THRESHOLD |
>  			  GEN6_PM_RP_DOWN_TIMEOUT);
> -
>  	WRITE_ONCE(rps->pm_events, events);
> +
>  	spin_lock_irq(&gt->irq_lock);
>  	gen6_gt_pm_enable_irq(gt, rps->pm_events);
>  	spin_unlock_irq(&gt->irq_lock);
>  
> -	set(gt->uncore, GEN6_PMINTRMSK, rps_pm_mask(rps, rps->cur_freq));
> +	intel_uncore_write(gt->uncore,
> +                           GEN6_PMINTRMSK, rps_pm_mask(rps, rps->last_freq));
>  }
>  
>  static void gen6_rps_reset_interrupts(struct intel_rps *rps)
> @@ -120,7 +121,9 @@ static void rps_disable_interrupts(struct intel_rps *rps)
>  	struct intel_gt *gt = rps_to_gt(rps);
>  
>  	WRITE_ONCE(rps->pm_events, 0);
> -	set(gt->uncore, GEN6_PMINTRMSK, rps_pm_sanitize_mask(rps, ~0u));
> +
> +	intel_uncore_write(gt->uncore,
> +                           GEN6_PMINTRMSK, rps_pm_sanitize_mask(rps, ~0u));
>  
>  	spin_lock_irq(&gt->irq_lock);
>  	gen6_gt_pm_disable_irq(gt, GEN6_PM_RPS_EVENTS);
> -- 
> 2.20.1

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  parent reply	other threads:[~2020-04-15 19:14 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-15  7:50 [Intel-gfx] [PATCH] drm/i915/gt: Update PMINTRMSK holding fw Chris Wilson
2020-04-15  7:50 ` Chris Wilson
2020-04-15  8:32 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2020-04-15  8:48 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2020-04-15  8:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-04-15 11:09 ` [Intel-gfx] [PATCH] " Mika Kuoppala
2020-04-15 11:09   ` Mika Kuoppala
2020-04-15 11:24 ` [Intel-gfx] " Andi Shyti
2020-04-15 11:24   ` Andi Shyti
2020-04-15 19:14 ` Francisco Jerez [this message]
2020-04-15 19:14   ` Francisco Jerez
2020-04-16  1:40 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for " Patchwork

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