[PATCH 0/2] Pipe CSC and Gamma Enabling for GLK.

[PATCH 0/2] Pipe CSC and Gamma Enabling for GLK.

[Dhanya Pillai]

From: Dhanya <dhanya.p.r@intel.com>

This series contains patches for enabling CSC and Gamma for
GLK. Also, it programs unity gamma to Pre-CSC Gamma lut for GLK+.

Tested on GLK silicon.

Dhanya (2):
  drm/i915/glk: Enable Pipe Level CSC & Gamma Feature.
  drm/i915/glk: Program pre_csc_gamma with unity gamma

 drivers/gpu/drm/i915/i915_reg.h      | 13 +++++++++++++
 drivers/gpu/drm/i915/intel_color.c   | 37 +++++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_display.c | 18 +++++++++++++-----
 3 files changed, 62 insertions(+), 6 deletions(-)

-- 
1.9.1

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[PATCH 1/2] drm/i915/glk: Enable Pipe Level CSC & Gamma Feature.

[Dhanya Pillai]

From: Dhanya <dhanya.p.r@intel.com>

For GLK, we need to program new register PLANE_COLOR_CTL
for enabling CSC and Gamma. This patch sets the pipe gamma
and pipe csc bit in the PLANE_COLOR_CTL.

Signed-off-by: Dhanya <dhanya.p.r@intel.com>
---
 drivers/gpu/drm/i915/intel_color.c   |  2 +-
 drivers/gpu/drm/i915/intel_display.c | 18 +++++++++++++-----
 2 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index f0f2d04..8bfcdcd 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -538,7 +538,7 @@ void intel_color_init(struct drm_crtc *crtc)
 		dev_priv->display.load_luts = haswell_load_luts;
 	} else if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv) ||
 		   IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv) ||
-		   IS_COFFEELAKE(dev_priv)) {
+		   IS_COFFEELAKE(dev_priv) || IS_GEN9_LP(dev_priv)) {
 		dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
 		dev_priv->display.load_luts = broadwell_load_luts;
 	} else {
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 266b03f..d91a456 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3441,9 +3441,19 @@ static void skylake_update_primary_plane(struct drm_plane *plane,
 	int dst_w = drm_rect_width(&plane_state->base.dst);
 	int dst_h = drm_rect_height(&plane_state->base.dst);
 
-	plane_ctl = PLANE_CTL_ENABLE |
-		    PLANE_CTL_PIPE_GAMMA_ENABLE |
-		    PLANE_CTL_PIPE_CSC_ENABLE;
+	plane_ctl = PLANE_CTL_ENABLE;
+
+	if (IS_GEN9_LP(dev_priv) && !IS_BROXTON(dev_priv)) {
+		I915_WRITE(PLANE_COLOR_CTL(pipe, 0),
+				PLANE_CTL_PLANE_GAMMA_DISABLE |
+				PLANE_CTL_PIPE_GAMMA_ENABLE |
+				PLANE_CTL_PIPE_CSC_ENABLE);
+	} else {
+		plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE |
+			PLANE_CTL_PIPE_CSC_ENABLE |
+			PLANE_CTL_PLANE_GAMMA_DISABLE;
+	}
+
 
 	plane_ctl |= skl_plane_ctl_format(fb->format->format);
 	plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
@@ -3466,8 +3476,6 @@ static void skylake_update_primary_plane(struct drm_plane *plane,
 	I915_WRITE(PLANE_STRIDE(pipe, plane_id), stride);
 	I915_WRITE(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
 
-	if (IS_GEMINILAKE(dev_priv))
-		I915_WRITE(PLANE_COLOR_CTL(pipe, 0), PLANE_GAMMA_DISABLE);
 
 	if (scaler_id >= 0) {
 		uint32_t ps_ctrl = 0;
-- 
1.9.1

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[PATCH 2/2] drm/i915/glk: Program pre_csc_gamma with unity gamma

[Dhanya Pillai]

From: Dhanya <dhanya.p.r@intel.com>

For GLK, Pre-CSC Gamma correction get enabled/disabled based
on "Pipe CSC Enable" bit in the PLANE_COLOR_CTL.
This patch programs Unity Gamma in these registers.

Signed-off-by: Dhanya <dhanya.p.r@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h    | 13 +++++++++++++
 drivers/gpu/drm/i915/intel_color.c | 35 +++++++++++++++++++++++++++++++++++
 2 files changed, 48 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index be756bd..ab6684d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8512,6 +8512,19 @@ enum {
 #define PREC_PAL_GC_MAX(pipe, i)	_MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)
 #define PREC_PAL_EXT_GC_MAX(pipe, i)	_MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
 
+/*pipe pre-csc gamma LUTS on GEN10+*/
+#define PRE_CSC_GAMMA_AUTO_INCREMENT (1 << 10)
+#define PRE_CSC_GAMMA_LUT_SIZE 35
+#define _PRE_CSC_GAMMA_INDEX_A  0x4A484
+#define _PRE_CSC_GAMMA_INDEX_B  0x4AC84
+#define _PRE_CSC_GAMMA_INDEX_C  0x4B484
+#define _PRE_CSC_GAMMA_DATA_A  0x4A488
+#define _PRE_CSC_GAMMA_DATA_B  0x4AC88
+#define _PRE_CSC_GAMMA_DATA_C  0x4B488
+
+#define PRE_CSC_GAMMA_INDEX(pipe)   _MMIO_PIPE(pipe, _PRE_CSC_GAMMA_INDEX_A, _PRE_CSC_GAMMA_INDEX_B)
+#define PRE_CSC_GAMMA_DATA(pipe)    _MMIO_PIPE(pipe, _PRE_CSC_GAMMA_DATA_A, _PRE_CSC_GAMMA_DATA_B)
+
 /* pipe CSC & degamma/gamma LUTs on CHV */
 #define _CGM_PIPE_A_CSC_COEFF01	(VLV_DISPLAY_BASE + 0x67900)
 #define _CGM_PIPE_A_CSC_COEFF23	(VLV_DISPLAY_BASE + 0x67904)
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 8bfcdcd..05dcaa6 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -91,6 +91,32 @@ static void ctm_mult_by_limited(uint64_t *result, int64_t *input)
 	}
 }
 
+/*Set up the Pre-CSC Gamma correction for Gen9+*/
+static void i9xx_load_pre_csc_gamma_lut(struct drm_crtc_state *crtc_state)
+{
+	struct drm_crtc *crtc = crtc_state->crtc;
+	struct drm_device *dev = crtc->dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	int i, pipe = intel_crtc->pipe;
+
+	I915_WRITE(PRE_CSC_GAMMA_INDEX(pipe),
+			PRE_CSC_GAMMA_AUTO_INCREMENT);
+
+	for (i = 0; i < PRE_CSC_GAMMA_LUT_SIZE; i++) {
+		uint32_t v = (i * ((1 << 16) - 1));
+
+		I915_WRITE(PRE_CSC_GAMMA_DATA(pipe), v);
+	}
+	/*
+	 * Reset the index, otherwise it prevents the legacy palette to be
+	 * written properly.
+	 */
+	I915_WRITE(PRE_CSC_GAMMA_INDEX(pipe), 0);
+
+}
+
+
 /* Set up the pipe CSC unit. */
 static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state)
 {
@@ -101,6 +127,15 @@ static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state)
 	uint16_t coeffs[9] = { 0, };
 	struct intel_crtc_state *intel_crtc_state = to_intel_crtc_state(crtc_state);
 
+	/*
+	 *For Gen9_LP+ Pre-CSC Gamma correction get enabled/disabled based on
+	 *"Pipe CSC Enable" bit in the PLANE_COLOR_CTL. We need to program 1:1
+	 * gamma value in these.
+	 */
+
+	if (IS_GEN9_LP(dev_priv) && !IS_BROXTON(dev_priv))
+		i9xx_load_pre_csc_gamma_lut(crtc_state);
+
 	if (crtc_state->ctm) {
 		struct drm_color_ctm *ctm =
 			(struct drm_color_ctm *)crtc_state->ctm->data;
-- 
1.9.1

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Re: [PATCH 0/2] Pipe CSC and Gamma Enabling for GLK.

[Jani Nikula]

On Thu, 29 Dec 2016, Dhanya Pillai <dhanya.p.r@intel.com> wrote:
> This series contains patches for enabling CSC and Gamma for
> GLK. Also, it programs unity gamma to Pre-CSC Gamma lut for GLK+.

The patches don't apply on top of drm-tip branch of [1]. Please rebase
and repost.

BR,
Jani.


[1] https://cgit.freedesktop.org/drm-tip



-- 
Jani Nikula, Intel Open Source Technology Center
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