Re: [PATCH 1/3] RISC-V: enable IRQ-PIPELINE

[Philippe Gerum <rpm@xenomai.org>]

Florian Bezdeka <florian.bezdeka@siemens.com> writes:

> On Fri, 2024-10-11 at 09:15 +0200, Jan Kiszka wrote:
>> On 11.10.24 08:37, shannmu wrote:
>> > This adds virtual interrupt functions `arch_xxx`,
>> > irq-pipelined top-level interrupt handler `handle_riscv_irq`
>> > and `handle_arch_irq_pipelined`,
>> > real interrupt-flags functions `native_xxx`,
>> > `mark_trap_entry` and `mark_trap_exit` in trap functions,
>> > multiplexed ipi_message_type `IPI_RESCHEDULE` for in-band ipi.
>> > 
>> > Signed-off-by: shannmu <shanmu1901@gmail.com>
>> > ---
>> >  arch/riscv/Kconfig                    |   5 +
>> >  arch/riscv/include/asm/dovetail.h     |  58 +++++++
>> >  arch/riscv/include/asm/irq_pipeline.h | 173 +++++++++++++++++++++
>> >  arch/riscv/include/asm/irqflags.h     |  26 ++--
>> >  arch/riscv/include/asm/mmu_context.h  |  21 ++-
>> >  arch/riscv/include/asm/syscall.h      |   6 +
>> >  arch/riscv/kernel/Makefile            |   1 +
>> >  arch/riscv/kernel/irq.c               |  72 ++++++---
>> >  arch/riscv/kernel/irq_pipeline.c      |  46 ++++++
>> >  arch/riscv/kernel/smp.c               | 135 ++++++++++++----
>> >  arch/riscv/kernel/smpboot.c           |   2 +-
>> >  arch/riscv/kernel/traps.c             | 212 +++++++++++++++-----------
>> >  arch/riscv/mm/fault.c                 |  46 +++---
>> >  13 files changed, 633 insertions(+), 170 deletions(-)
>> >  create mode 100644 arch/riscv/include/asm/dovetail.h
>> >  create mode 100644 arch/riscv/include/asm/irq_pipeline.h
>> >  create mode 100644 arch/riscv/kernel/irq_pipeline.c
>> > 
>> 
>> Thanks for sharing your work! Could you explain how these bits compare
>> to what Tobias sent earlier [1]? Is it possible to combine your work
>> with that to ensure nothing relevant is missed?
>
> Thanks for sharing +1. One major difference is the base branch. Tobias
> was working on 6.11 while this one is based on 6.6.
>
> As we now have two different works streams it makes sense to
> synchronize and ideally align on a roadmap / work sharing plan. That
> would help to minimize review / testing efforts - at least on my side.
>

Agreed. For the record, I'm willing to merge the RISC-V architecture
support into Dovetail and the EVL core. We'd just need to merge both
ongoing efforts to get this done faster.

-- 
Philippe.