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From: "Alex Bennée" <alex.bennee@linaro.org>
To: qemu-arm@nongnu.org
Cc: qemu-devel@nongnu.org, Peter Maydell <peter.maydell@linaro.org>
Subject: Re: [Qemu-arm] [PATCH v2 23/29] target/arm: Use tcg_gen_abs_i64 and tcg_gen_gvec_abs
Date: Thu, 02 May 2019 17:07:42 +0100	[thread overview]
Message-ID: <87zho44z75.fsf@zen.linaroharston> (raw)
In-Reply-To: <20190501050536.15580-24-richard.henderson@linaro.org>


Richard Henderson <richard.henderson@linaro.org> writes:

> Cc: qemu-arm@nongnu.org
> Cc: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

> ---
>  target/arm/helper.h        |  2 --
>  target/arm/neon_helper.c   |  5 -----
>  target/arm/translate-a64.c | 41 +++++---------------------------------
>  target/arm/translate.c     | 11 +++-------
>  4 files changed, 8 insertions(+), 51 deletions(-)
>
> diff --git a/target/arm/helper.h b/target/arm/helper.h
> index 50cb036378..132aa1682e 100644
> --- a/target/arm/helper.h
> +++ b/target/arm/helper.h
> @@ -352,8 +352,6 @@ DEF_HELPER_2(neon_ceq_u8, i32, i32, i32)
>  DEF_HELPER_2(neon_ceq_u16, i32, i32, i32)
>  DEF_HELPER_2(neon_ceq_u32, i32, i32, i32)
>
> -DEF_HELPER_1(neon_abs_s8, i32, i32)
> -DEF_HELPER_1(neon_abs_s16, i32, i32)
>  DEF_HELPER_1(neon_clz_u8, i32, i32)
>  DEF_HELPER_1(neon_clz_u16, i32, i32)
>  DEF_HELPER_1(neon_cls_s8, i32, i32)
> diff --git a/target/arm/neon_helper.c b/target/arm/neon_helper.c
> index ed1c6fc41c..4259056723 100644
> --- a/target/arm/neon_helper.c
> +++ b/target/arm/neon_helper.c
> @@ -1228,11 +1228,6 @@ NEON_VOP(ceq_u16, neon_u16, 2)
>  NEON_VOP(ceq_u32, neon_u32, 1)
>  #undef NEON_FN
>
> -#define NEON_FN(dest, src, dummy) dest = (src < 0) ? -src : src
> -NEON_VOP1(abs_s8, neon_s8, 4)
> -NEON_VOP1(abs_s16, neon_s16, 2)
> -#undef NEON_FN
> -
>  /* Count Leading Sign/Zero Bits.  */
>  static inline int do_clz8(uint8_t x)
>  {
> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
> index 9dcc5ff3a3..b7c5a928b4 100644
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -9468,11 +9468,7 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
>          if (u) {
>              tcg_gen_neg_i64(tcg_rd, tcg_rn);
>          } else {
> -            TCGv_i64 tcg_zero = tcg_const_i64(0);
> -            tcg_gen_neg_i64(tcg_rd, tcg_rn);
> -            tcg_gen_movcond_i64(TCG_COND_GT, tcg_rd, tcg_rn, tcg_zero,
> -                                tcg_rn, tcg_rd);
> -            tcg_temp_free_i64(tcg_zero);
> +            tcg_gen_abs_i64(tcg_rd, tcg_rn);
>          }
>          break;
>      case 0x2f: /* FABS */
> @@ -12366,11 +12362,12 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
>          }
>          break;
>      case 0xb:
> -        if (u) { /* NEG */
> +        if (u) { /* ABS, NEG */
>              gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_neg, size);
> -            return;
> +        } else {
> +            gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_abs, size);
>          }
> -        break;
> +        return;
>      }
>
>      if (size == 3) {
> @@ -12438,17 +12435,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
>                          gen_helper_neon_qabs_s32(tcg_res, cpu_env, tcg_op);
>                      }
>                      break;
> -                case 0xb: /* ABS, NEG */
> -                    if (u) {
> -                        tcg_gen_neg_i32(tcg_res, tcg_op);
> -                    } else {
> -                        TCGv_i32 tcg_zero = tcg_const_i32(0);
> -                        tcg_gen_neg_i32(tcg_res, tcg_op);
> -                        tcg_gen_movcond_i32(TCG_COND_GT, tcg_res, tcg_op,
> -                                            tcg_zero, tcg_op, tcg_res);
> -                        tcg_temp_free_i32(tcg_zero);
> -                    }
> -                    break;
>                  case 0x2f: /* FABS */
>                      gen_helper_vfp_abss(tcg_res, tcg_op);
>                      break;
> @@ -12561,23 +12547,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
>                      tcg_temp_free_i32(tcg_zero);
>                      break;
>                  }
> -                case 0xb: /* ABS, NEG */
> -                    if (u) {
> -                        TCGv_i32 tcg_zero = tcg_const_i32(0);
> -                        if (size) {
> -                            gen_helper_neon_sub_u16(tcg_res, tcg_zero, tcg_op);
> -                        } else {
> -                            gen_helper_neon_sub_u8(tcg_res, tcg_zero, tcg_op);
> -                        }
> -                        tcg_temp_free_i32(tcg_zero);
> -                    } else {
> -                        if (size) {
> -                            gen_helper_neon_abs_s16(tcg_res, tcg_op);
> -                        } else {
> -                            gen_helper_neon_abs_s8(tcg_res, tcg_op);
> -                        }
> -                    }
> -                    break;
>                  case 0x4: /* CLS, CLZ */
>                      if (u) {
>                          if (size == 0) {
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index b25781554f..dd053c80d6 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -8120,6 +8120,9 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
>                  case NEON_2RM_VNEG:
>                      tcg_gen_gvec_neg(size, rd_ofs, rm_ofs, vec_size, vec_size);
>                      break;
> +                case NEON_2RM_VABS:
> +                    tcg_gen_gvec_abs(size, rd_ofs, rm_ofs, vec_size, vec_size);
> +                    break;
>
>                  default:
>                  elementwise:
> @@ -8225,14 +8228,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
>                              }
>                              tcg_temp_free_i32(tmp2);
>                              break;
> -                        case NEON_2RM_VABS:
> -                            switch(size) {
> -                            case 0: gen_helper_neon_abs_s8(tmp, tmp); break;
> -                            case 1: gen_helper_neon_abs_s16(tmp, tmp); break;
> -                            case 2: tcg_gen_abs_i32(tmp, tmp); break;
> -                            default: abort();
> -                            }
> -                            break;
>                          case NEON_2RM_VCGT0_F:
>                          {
>                              TCGv_ptr fpstatus = get_fpstatus_ptr(1);


--
Alex Bennée

WARNING: multiple messages have this Message-ID (diff)
From: "Alex Bennée" <alex.bennee@linaro.org>
To: qemu-arm@nongnu.org
Cc: qemu-devel@nongnu.org, Peter Maydell <peter.maydell@linaro.org>
Subject: Re: [Qemu-devel] [Qemu-arm] [PATCH v2 23/29] target/arm: Use tcg_gen_abs_i64 and tcg_gen_gvec_abs
Date: Thu, 02 May 2019 17:07:42 +0100	[thread overview]
Message-ID: <87zho44z75.fsf@zen.linaroharston> (raw)
In-Reply-To: <20190501050536.15580-24-richard.henderson@linaro.org>


Richard Henderson <richard.henderson@linaro.org> writes:

> Cc: qemu-arm@nongnu.org
> Cc: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

> ---
>  target/arm/helper.h        |  2 --
>  target/arm/neon_helper.c   |  5 -----
>  target/arm/translate-a64.c | 41 +++++---------------------------------
>  target/arm/translate.c     | 11 +++-------
>  4 files changed, 8 insertions(+), 51 deletions(-)
>
> diff --git a/target/arm/helper.h b/target/arm/helper.h
> index 50cb036378..132aa1682e 100644
> --- a/target/arm/helper.h
> +++ b/target/arm/helper.h
> @@ -352,8 +352,6 @@ DEF_HELPER_2(neon_ceq_u8, i32, i32, i32)
>  DEF_HELPER_2(neon_ceq_u16, i32, i32, i32)
>  DEF_HELPER_2(neon_ceq_u32, i32, i32, i32)
>
> -DEF_HELPER_1(neon_abs_s8, i32, i32)
> -DEF_HELPER_1(neon_abs_s16, i32, i32)
>  DEF_HELPER_1(neon_clz_u8, i32, i32)
>  DEF_HELPER_1(neon_clz_u16, i32, i32)
>  DEF_HELPER_1(neon_cls_s8, i32, i32)
> diff --git a/target/arm/neon_helper.c b/target/arm/neon_helper.c
> index ed1c6fc41c..4259056723 100644
> --- a/target/arm/neon_helper.c
> +++ b/target/arm/neon_helper.c
> @@ -1228,11 +1228,6 @@ NEON_VOP(ceq_u16, neon_u16, 2)
>  NEON_VOP(ceq_u32, neon_u32, 1)
>  #undef NEON_FN
>
> -#define NEON_FN(dest, src, dummy) dest = (src < 0) ? -src : src
> -NEON_VOP1(abs_s8, neon_s8, 4)
> -NEON_VOP1(abs_s16, neon_s16, 2)
> -#undef NEON_FN
> -
>  /* Count Leading Sign/Zero Bits.  */
>  static inline int do_clz8(uint8_t x)
>  {
> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
> index 9dcc5ff3a3..b7c5a928b4 100644
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -9468,11 +9468,7 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
>          if (u) {
>              tcg_gen_neg_i64(tcg_rd, tcg_rn);
>          } else {
> -            TCGv_i64 tcg_zero = tcg_const_i64(0);
> -            tcg_gen_neg_i64(tcg_rd, tcg_rn);
> -            tcg_gen_movcond_i64(TCG_COND_GT, tcg_rd, tcg_rn, tcg_zero,
> -                                tcg_rn, tcg_rd);
> -            tcg_temp_free_i64(tcg_zero);
> +            tcg_gen_abs_i64(tcg_rd, tcg_rn);
>          }
>          break;
>      case 0x2f: /* FABS */
> @@ -12366,11 +12362,12 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
>          }
>          break;
>      case 0xb:
> -        if (u) { /* NEG */
> +        if (u) { /* ABS, NEG */
>              gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_neg, size);
> -            return;
> +        } else {
> +            gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_abs, size);
>          }
> -        break;
> +        return;
>      }
>
>      if (size == 3) {
> @@ -12438,17 +12435,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
>                          gen_helper_neon_qabs_s32(tcg_res, cpu_env, tcg_op);
>                      }
>                      break;
> -                case 0xb: /* ABS, NEG */
> -                    if (u) {
> -                        tcg_gen_neg_i32(tcg_res, tcg_op);
> -                    } else {
> -                        TCGv_i32 tcg_zero = tcg_const_i32(0);
> -                        tcg_gen_neg_i32(tcg_res, tcg_op);
> -                        tcg_gen_movcond_i32(TCG_COND_GT, tcg_res, tcg_op,
> -                                            tcg_zero, tcg_op, tcg_res);
> -                        tcg_temp_free_i32(tcg_zero);
> -                    }
> -                    break;
>                  case 0x2f: /* FABS */
>                      gen_helper_vfp_abss(tcg_res, tcg_op);
>                      break;
> @@ -12561,23 +12547,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
>                      tcg_temp_free_i32(tcg_zero);
>                      break;
>                  }
> -                case 0xb: /* ABS, NEG */
> -                    if (u) {
> -                        TCGv_i32 tcg_zero = tcg_const_i32(0);
> -                        if (size) {
> -                            gen_helper_neon_sub_u16(tcg_res, tcg_zero, tcg_op);
> -                        } else {
> -                            gen_helper_neon_sub_u8(tcg_res, tcg_zero, tcg_op);
> -                        }
> -                        tcg_temp_free_i32(tcg_zero);
> -                    } else {
> -                        if (size) {
> -                            gen_helper_neon_abs_s16(tcg_res, tcg_op);
> -                        } else {
> -                            gen_helper_neon_abs_s8(tcg_res, tcg_op);
> -                        }
> -                    }
> -                    break;
>                  case 0x4: /* CLS, CLZ */
>                      if (u) {
>                          if (size == 0) {
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index b25781554f..dd053c80d6 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -8120,6 +8120,9 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
>                  case NEON_2RM_VNEG:
>                      tcg_gen_gvec_neg(size, rd_ofs, rm_ofs, vec_size, vec_size);
>                      break;
> +                case NEON_2RM_VABS:
> +                    tcg_gen_gvec_abs(size, rd_ofs, rm_ofs, vec_size, vec_size);
> +                    break;
>
>                  default:
>                  elementwise:
> @@ -8225,14 +8228,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
>                              }
>                              tcg_temp_free_i32(tmp2);
>                              break;
> -                        case NEON_2RM_VABS:
> -                            switch(size) {
> -                            case 0: gen_helper_neon_abs_s8(tmp, tmp); break;
> -                            case 1: gen_helper_neon_abs_s16(tmp, tmp); break;
> -                            case 2: tcg_gen_abs_i32(tmp, tmp); break;
> -                            default: abort();
> -                            }
> -                            break;
>                          case NEON_2RM_VCGT0_F:
>                          {
>                              TCGv_ptr fpstatus = get_fpstatus_ptr(1);


--
Alex Bennée

WARNING: multiple messages have this Message-ID (diff)
From: "Alex Bennée" <alex.bennee@linaro.org>
To: qemu-arm@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [Qemu-arm] [PATCH v2 23/29] target/arm: Use tcg_gen_abs_i64 and tcg_gen_gvec_abs
Date: Thu, 02 May 2019 17:07:42 +0100	[thread overview]
Message-ID: <87zho44z75.fsf@zen.linaroharston> (raw)
Message-ID: <20190502160742.6npruk6kCUfsuNtE38vxd9XUFll4X-vbAtw0kNaX4cc@z> (raw)
In-Reply-To: <20190501050536.15580-24-richard.henderson@linaro.org>


Richard Henderson <richard.henderson@linaro.org> writes:

> Cc: qemu-arm@nongnu.org
> Cc: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

> ---
>  target/arm/helper.h        |  2 --
>  target/arm/neon_helper.c   |  5 -----
>  target/arm/translate-a64.c | 41 +++++---------------------------------
>  target/arm/translate.c     | 11 +++-------
>  4 files changed, 8 insertions(+), 51 deletions(-)
>
> diff --git a/target/arm/helper.h b/target/arm/helper.h
> index 50cb036378..132aa1682e 100644
> --- a/target/arm/helper.h
> +++ b/target/arm/helper.h
> @@ -352,8 +352,6 @@ DEF_HELPER_2(neon_ceq_u8, i32, i32, i32)
>  DEF_HELPER_2(neon_ceq_u16, i32, i32, i32)
>  DEF_HELPER_2(neon_ceq_u32, i32, i32, i32)
>
> -DEF_HELPER_1(neon_abs_s8, i32, i32)
> -DEF_HELPER_1(neon_abs_s16, i32, i32)
>  DEF_HELPER_1(neon_clz_u8, i32, i32)
>  DEF_HELPER_1(neon_clz_u16, i32, i32)
>  DEF_HELPER_1(neon_cls_s8, i32, i32)
> diff --git a/target/arm/neon_helper.c b/target/arm/neon_helper.c
> index ed1c6fc41c..4259056723 100644
> --- a/target/arm/neon_helper.c
> +++ b/target/arm/neon_helper.c
> @@ -1228,11 +1228,6 @@ NEON_VOP(ceq_u16, neon_u16, 2)
>  NEON_VOP(ceq_u32, neon_u32, 1)
>  #undef NEON_FN
>
> -#define NEON_FN(dest, src, dummy) dest = (src < 0) ? -src : src
> -NEON_VOP1(abs_s8, neon_s8, 4)
> -NEON_VOP1(abs_s16, neon_s16, 2)
> -#undef NEON_FN
> -
>  /* Count Leading Sign/Zero Bits.  */
>  static inline int do_clz8(uint8_t x)
>  {
> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
> index 9dcc5ff3a3..b7c5a928b4 100644
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -9468,11 +9468,7 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
>          if (u) {
>              tcg_gen_neg_i64(tcg_rd, tcg_rn);
>          } else {
> -            TCGv_i64 tcg_zero = tcg_const_i64(0);
> -            tcg_gen_neg_i64(tcg_rd, tcg_rn);
> -            tcg_gen_movcond_i64(TCG_COND_GT, tcg_rd, tcg_rn, tcg_zero,
> -                                tcg_rn, tcg_rd);
> -            tcg_temp_free_i64(tcg_zero);
> +            tcg_gen_abs_i64(tcg_rd, tcg_rn);
>          }
>          break;
>      case 0x2f: /* FABS */
> @@ -12366,11 +12362,12 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
>          }
>          break;
>      case 0xb:
> -        if (u) { /* NEG */
> +        if (u) { /* ABS, NEG */
>              gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_neg, size);
> -            return;
> +        } else {
> +            gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_abs, size);
>          }
> -        break;
> +        return;
>      }
>
>      if (size == 3) {
> @@ -12438,17 +12435,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
>                          gen_helper_neon_qabs_s32(tcg_res, cpu_env, tcg_op);
>                      }
>                      break;
> -                case 0xb: /* ABS, NEG */
> -                    if (u) {
> -                        tcg_gen_neg_i32(tcg_res, tcg_op);
> -                    } else {
> -                        TCGv_i32 tcg_zero = tcg_const_i32(0);
> -                        tcg_gen_neg_i32(tcg_res, tcg_op);
> -                        tcg_gen_movcond_i32(TCG_COND_GT, tcg_res, tcg_op,
> -                                            tcg_zero, tcg_op, tcg_res);
> -                        tcg_temp_free_i32(tcg_zero);
> -                    }
> -                    break;
>                  case 0x2f: /* FABS */
>                      gen_helper_vfp_abss(tcg_res, tcg_op);
>                      break;
> @@ -12561,23 +12547,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
>                      tcg_temp_free_i32(tcg_zero);
>                      break;
>                  }
> -                case 0xb: /* ABS, NEG */
> -                    if (u) {
> -                        TCGv_i32 tcg_zero = tcg_const_i32(0);
> -                        if (size) {
> -                            gen_helper_neon_sub_u16(tcg_res, tcg_zero, tcg_op);
> -                        } else {
> -                            gen_helper_neon_sub_u8(tcg_res, tcg_zero, tcg_op);
> -                        }
> -                        tcg_temp_free_i32(tcg_zero);
> -                    } else {
> -                        if (size) {
> -                            gen_helper_neon_abs_s16(tcg_res, tcg_op);
> -                        } else {
> -                            gen_helper_neon_abs_s8(tcg_res, tcg_op);
> -                        }
> -                    }
> -                    break;
>                  case 0x4: /* CLS, CLZ */
>                      if (u) {
>                          if (size == 0) {
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index b25781554f..dd053c80d6 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -8120,6 +8120,9 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
>                  case NEON_2RM_VNEG:
>                      tcg_gen_gvec_neg(size, rd_ofs, rm_ofs, vec_size, vec_size);
>                      break;
> +                case NEON_2RM_VABS:
> +                    tcg_gen_gvec_abs(size, rd_ofs, rm_ofs, vec_size, vec_size);
> +                    break;
>
>                  default:
>                  elementwise:
> @@ -8225,14 +8228,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
>                              }
>                              tcg_temp_free_i32(tmp2);
>                              break;
> -                        case NEON_2RM_VABS:
> -                            switch(size) {
> -                            case 0: gen_helper_neon_abs_s8(tmp, tmp); break;
> -                            case 1: gen_helper_neon_abs_s16(tmp, tmp); break;
> -                            case 2: tcg_gen_abs_i32(tmp, tmp); break;
> -                            default: abort();
> -                            }
> -                            break;
>                          case NEON_2RM_VCGT0_F:
>                          {
>                              TCGv_ptr fpstatus = get_fpstatus_ptr(1);


--
Alex Bennée


  reply	other threads:[~2019-05-02 16:07 UTC|newest]

Thread overview: 61+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-01  5:05 [Qemu-devel] [PATCH v2 00/29] tcg vector improvements Richard Henderson
2019-05-01  5:05 ` [Qemu-devel] [PATCH v2 01/29] tcg: Implement tcg_gen_gvec_3i() Richard Henderson
2019-05-01 15:23   ` Alex Bennée
2019-05-01  5:05 ` [Qemu-devel] [PATCH v2 02/29] tcg: Do not recreate INDEX_op_neg_vec unless supported Richard Henderson
2019-05-01 15:26   ` Alex Bennée
2019-05-01  5:05 ` [Qemu-devel] [PATCH v2 03/29] tcg: Allow add_vec, sub_vec, neg_vec, not_vec to be expanded Richard Henderson
2019-05-01 15:56   ` Alex Bennée
2019-05-01  5:05 ` [Qemu-devel] [PATCH v2 04/29] tcg: Specify optional vector requirements with a list Richard Henderson
2019-05-01 17:24   ` Alex Bennée
2019-05-01  5:05 ` [Qemu-devel] [PATCH v2 05/29] tcg: Assert fixed_reg is read-only Richard Henderson
2019-05-01 17:26   ` Alex Bennée
2019-05-01  5:05 ` [Qemu-devel] [PATCH v2 06/29] tcg: Return bool success from tcg_out_mov Richard Henderson
2019-05-01 17:29   ` Alex Bennée
2019-05-01 20:31     ` Richard Henderson
2019-05-01  5:05 ` [Qemu-devel] [PATCH v2 07/29] tcg: Support cross-class moves without instruction support Richard Henderson
2019-05-01 17:34   ` Alex Bennée
2019-05-01 20:18     ` Richard Henderson
2019-05-01  5:05 ` [Qemu-devel] [PATCH v2 08/29] tcg: Promote tcg_out_{dup, dupi}_vec to backend interface Richard Henderson
2019-05-01 17:37   ` Alex Bennée
2019-05-01 20:21     ` Richard Henderson
2019-05-01  5:05 ` [Qemu-devel] [PATCH v2 09/29] tcg: Manually expand INDEX_op_dup_vec Richard Henderson
2019-05-02  9:42   ` Alex Bennée
2019-05-02 15:24     ` Richard Henderson
2019-05-01  5:05 ` [Qemu-devel] [PATCH v2 10/29] tcg: Add tcg_out_dupm_vec to the backend interface Richard Henderson
2019-05-01  5:05 ` [Qemu-devel] [PATCH v2 11/29] tcg/i386: Implement tcg_out_dupm_vec Richard Henderson
2019-05-01  5:05 ` [Qemu-devel] [PATCH v2 12/29] tcg/aarch64: " Richard Henderson
2019-05-02 13:26   ` Alex Bennée
2019-05-02 15:35     ` Richard Henderson
2019-05-01  5:05 ` [Qemu-devel] [PATCH v2 13/29] tcg: Add INDEX_op_dup_mem_vec Richard Henderson
2019-05-02 13:30   ` Alex Bennée
2019-05-02 15:38     ` Richard Henderson
2019-05-01  5:05 ` [Qemu-devel] [PATCH v2 14/29] tcg: Add gvec expanders for variable shift Richard Henderson
2019-05-02 14:08   ` Alex Bennée
2019-05-01  5:05 ` [Qemu-devel] [PATCH v2 15/29] tcg/i386: Support vector variable shift opcodes Richard Henderson
2019-05-01  5:05 ` [Qemu-devel] [PATCH v2 16/29] tcg/aarch64: " Richard Henderson
2019-05-02 14:12   ` Alex Bennée
2019-05-01  5:05 ` [Qemu-devel] [PATCH v2 17/29] tcg: Add gvec expanders for vector shift by scalar Richard Henderson
2019-05-02 14:37   ` Alex Bennée
2019-05-02 15:46     ` Richard Henderson
2019-05-01  5:05 ` [Qemu-devel] [PATCH v2 18/29] tcg/i386: Support vector scalar shift opcodes Richard Henderson
2019-05-01  5:05 ` [Qemu-devel] [PATCH v2 19/29] tcg: Add support for integer absolute value Richard Henderson
2019-05-02 15:25   ` Alex Bennée
2019-05-01  5:05 ` [Qemu-devel] [PATCH v2 20/29] tcg: Add support for vector " Richard Henderson
2019-05-02 15:47   ` Alex Bennée
2019-05-01  5:05 ` [Qemu-devel] [PATCH v2 21/29] tcg/i386: Support " Richard Henderson
2019-05-01  5:05 ` [Qemu-devel] [PATCH v2 22/29] tcg/aarch64: " Richard Henderson
2019-05-02 15:49   ` Alex Bennée
2019-05-01  5:05 ` [Qemu-arm] [PATCH v2 23/29] target/arm: Use tcg_gen_abs_i64 and tcg_gen_gvec_abs Richard Henderson
2019-05-01  5:05   ` [Qemu-devel] " Richard Henderson
2019-05-01  5:05   ` Richard Henderson
2019-05-02 16:07   ` Alex Bennée [this message]
2019-05-02 16:07     ` [Qemu-devel] [Qemu-arm] " Alex Bennée
2019-05-02 16:07     ` Alex Bennée
2019-05-01  5:05 ` [Qemu-devel] [PATCH v2 24/29] target/cris: Use tcg_gen_abs_tl Richard Henderson
2019-05-01  5:05 ` [Qemu-devel] [PATCH v2 25/29] target/ppc: Use tcg_gen_abs_i32 Richard Henderson
2019-05-01  5:05 ` [Qemu-devel] [PATCH v2 26/29] target/ppc: Use tcg_gen_abs_tl Richard Henderson
2019-05-01  5:05 ` [Qemu-devel] [PATCH v2 27/29] target/s390x: Use tcg_gen_abs_i64 Richard Henderson
2019-05-02 13:44   ` David Hildenbrand
2019-05-01  5:05 ` [Qemu-devel] [PATCH v2 28/29] target/tricore: Use tcg_gen_abs_tl Richard Henderson
2019-05-01  5:05 ` [Qemu-devel] [PATCH v2 29/29] target/xtensa: Use tcg_gen_abs_i32 Richard Henderson
2019-05-01 15:15   ` Max Filippov

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