From: Eric Anholt <eric@anholt.net>
To: Stefan Schake <stschake@gmail.com>
Cc: David Airlie <airlied@linux.ie>,
linux-rpi-kernel@lists.infradead.org,
dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] drm/vc4: Ensure interrupts are disabled
Date: Tue, 14 Nov 2017 11:44:41 -0800 [thread overview]
Message-ID: <87zi7o8x1y.fsf@anholt.net> (raw)
In-Reply-To: <CAOZHkRxf_puuVOoUUnbQ_mM92=pA5Mzoi4_LtJ8BKRnmau-HYg@mail.gmail.com>
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Stefan Schake <stschake@gmail.com> writes:
> On Tue, Nov 14, 2017 at 1:18 AM, Eric Anholt <eric@anholt.net> wrote:
>> Stefan Schake <stschake@gmail.com> writes:
>>
>>> The overflow mem work callback vc4_overflow_mem_work reenables its
>>> associated interrupt upon completion. To ensure all interrupts are disabled
>>> when we return from vc4_irq_uninstall, we need to disable it again if
>>> cancel_work_sync indicated pending work.
>>
>> Is there a reason we need the interrupts disabled at the V3D level while
>> we have the IRQ disabled at the irqchip level? Once we re-enable at the
>> irqchip, we immediately V3D_WRITE(V3D_INTENA, V3D_DRIVER_IRQS) anyway.
>
> irqchip will mask it in the ARM interrupt controller, so we will certainly never
> see an interrupt. I'm not sure on the exact guarantees V3D_INTENA and
> V3D_INTCTL make - does the state in INTENA affect if V3D will signal an
> interrupt in INTCTL? We're not currently clearing the latter in postinstall.
INTENA/INTDIS writes update the state of the single register that
controls which bits of INTCTL get ORed together to raise the interrupt
outside the V3D block.
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WARNING: multiple messages have this Message-ID (diff)
From: Eric Anholt <eric@anholt.net>
To: Stefan Schake <stschake@gmail.com>
Cc: dri-devel@lists.freedesktop.org,
linux-rpi-kernel@lists.infradead.org,
David Airlie <airlied@linux.ie>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] drm/vc4: Ensure interrupts are disabled
Date: Tue, 14 Nov 2017 11:44:41 -0800 [thread overview]
Message-ID: <87zi7o8x1y.fsf@anholt.net> (raw)
In-Reply-To: <CAOZHkRxf_puuVOoUUnbQ_mM92=pA5Mzoi4_LtJ8BKRnmau-HYg@mail.gmail.com>
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Stefan Schake <stschake@gmail.com> writes:
> On Tue, Nov 14, 2017 at 1:18 AM, Eric Anholt <eric@anholt.net> wrote:
>> Stefan Schake <stschake@gmail.com> writes:
>>
>>> The overflow mem work callback vc4_overflow_mem_work reenables its
>>> associated interrupt upon completion. To ensure all interrupts are disabled
>>> when we return from vc4_irq_uninstall, we need to disable it again if
>>> cancel_work_sync indicated pending work.
>>
>> Is there a reason we need the interrupts disabled at the V3D level while
>> we have the IRQ disabled at the irqchip level? Once we re-enable at the
>> irqchip, we immediately V3D_WRITE(V3D_INTENA, V3D_DRIVER_IRQS) anyway.
>
> irqchip will mask it in the ARM interrupt controller, so we will certainly never
> see an interrupt. I'm not sure on the exact guarantees V3D_INTENA and
> V3D_INTCTL make - does the state in INTENA affect if V3D will signal an
> interrupt in INTCTL? We're not currently clearing the latter in postinstall.
INTENA/INTDIS writes update the state of the single register that
controls which bits of INTCTL get ORed together to raise the interrupt
outside the V3D block.
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next prev parent reply other threads:[~2017-11-14 19:44 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-11-10 1:05 [PATCH 0/2] drm/vc4: Correctly uninstall interrupts Stefan Schake
2017-11-10 1:05 ` Stefan Schake
2017-11-10 1:05 ` [PATCH 1/2] drm/vc4: Account for interrupts in flight Stefan Schake
2017-11-10 1:05 ` Stefan Schake
2017-11-14 0:59 ` Eric Anholt
2017-11-14 0:59 ` Eric Anholt
2017-11-10 1:05 ` [PATCH 2/2] drm/vc4: Ensure interrupts are disabled Stefan Schake
2017-11-10 1:05 ` Stefan Schake
2017-11-14 0:18 ` Eric Anholt
2017-11-14 0:18 ` Eric Anholt
2017-11-14 11:43 ` Stefan Schake
2017-11-14 19:44 ` Eric Anholt [this message]
2017-11-14 19:44 ` Eric Anholt
2017-11-14 23:18 ` Stefan Schake
2017-11-14 23:18 ` Stefan Schake
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