Re: [PATCH v2 5/5] phy: qcom-mipi-csi2: Add sc7280 D-PHY provider

[Krzysztof Kozlowski <krzk@kernel.org>]

On 03/11/2026 22:41, Anusha Arun Nandi wrote:
> Add the SC7280 CSIPHY to the generic MIPI CSI2 PHY driver, 
> bound to a new "qcom,sc7280-csi2-phy" compatible
> and reusing the existing D-PHY 2-phase hw ops
> (phy_qcom_mipi_csi2_ops_3ph_1_0). The lane_regs_sc7280[] init
> sequence is the CSIPHY 5nm 2-phase 2.5Gbps 4-lane D-PHY register
> set ported from the legacy in-tree camss-csiphy-3ph-1-0.c table,
> with the entries that table left as do-not-program placeholders
> simply omitted here rather than carried as a new marker. The
> soc_cfg declares the core/timer clocks (matching x1e80100's and
> sa8775p's clock-names convention for this pair) and the
> vdda-phy/vdda-pll supplies.
> 
> Like x1e80100 and SA8775P, SC7280's CSIPHY core clock is OPP-scaled
> against the sensor's link frequency via the shared csiphy_opp_table
> in kodiak.dtsi, so opp_clk_name is set to "core" here too. SC7280's
> CSIPHY has a single power-domain, the Titan Top GDSC, matching
> camss.c's sc7280_resources.pd_name = "top" and kodiak.dtsi's
> existing camss node; it is not OPP-scaled, only kept enabled.
> 
> Reviewed-by: Jigarkumar Zala <jigarkumar.zala@oss.qualcomm.com>

Where/When? Please provide lore links and proper changelog.

...

> +
> +static const char * const sc7280_clks[] = {
> +	"core",
> +	"timer",
> +};

What is the point of this array for each variant if all devices have the
same names? IOW, what is the point of patch #2?

Best regards,
Krzysztof

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