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From: Jun Guo <jun.guo@cixtech.com>
To: Rodrigo Alencar <455.rodrigo.alencar@gmail.com>,
	Mark Brown <broonie@kernel.org>
Cc: peter.chen@cixtech.com, fugang.duan@cixtech.com, robh@kernel.org,
	krzk+dt@kernel.org, conor+dt@kernel.org,
	linux-spi@vger.kernel.org, michal.simek@amd.com,
	cix-kernel-upstream@cixtech.com,
	linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 2/3] spi: spi-cadence: supports transmission with bits_per_word of 16 and 32
Date: Thu, 15 Jan 2026 10:14:48 +0800	[thread overview]
Message-ID: <896a47be-20cc-405c-9a4a-c4112b30d4cb@cixtech.com> (raw)
In-Reply-To: <lbijvnnwsnddonmm5pveqzap6iibxhl4maneq43x4j6w64dev6@u75qhm5cwiob>

hi Rodrigo,

   I'm very sorry for introducing this issue. Thank you for your 
reminder. I will immediately submit a patch to add 
SPI_CONTROLLER_MUST_TX to the flags during probe to resolve this problem.

On 1/15/2026 12:09 AM, Rodrigo Alencar wrote:
> [You don't often get email from 455.rodrigo.alencar@gmail.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> 
> EXTERNAL EMAIL
> 
> On 26/01/14 02:16PM, Mark Brown wrote:
>> On Wed, Jan 14, 2026 at 02:14:35PM +0000, Rodrigo Alencar wrote:
>>> On 25/10/31 03:30PM, Jun Guo wrote:
>>
>>>> + if (xspi->txbuf) {
>>>> +         switch (xspi->n_bytes) {
>>>> +         case CDNS_SPI_N_BYTES_U8:
>>>> +                 txw = *(u8 *)xspi->txbuf;
>>>> +                 break;
>>
>>>> +         cdns_spi_write(xspi, CDNS_SPI_TXD, txw);
>>>> +         xspi->txbuf = (u8 *)xspi->txbuf + xspi->n_bytes;
>>>> + }
>>
>>> cdns_spi_write(xspi, CDNS_SPI_TXD, txw) needs to be called regardless of xspi->txbuf.
>>> Otherwise, there will be no clock for the read operation to work.
>>> This is a bug I am seeing on a Zedboard running on 6.19
>>
>> So the device needs to be flagged as SPI_CONTROLLER_MUST_TX?
> 
> yes, It works if
> 
> ctlr->flags = SPI_CONTROLLER_MUST_TX;
> 
> is added to the probe function. At least for my case handling with "xlnx,zynq-spi-r1p6"
> 
> kind regards,
> 
> Rodrigo Alencar
> 



  reply	other threads:[~2026-01-15  2:15 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-31  7:30 [PATCH v3 0/3] spi-cadence: support transmission with bits_per_word of 16 and 32 Jun Guo
2025-10-31  7:30 ` [PATCH v3 1/3] dt-bindings: spi: spi-cadence: update DT binding docs to support cix sky1 SoC Jun Guo
2025-10-31 15:10   ` Conor Dooley
2025-10-31  7:30 ` [PATCH v3 2/3] spi: spi-cadence: supports transmission with bits_per_word of 16 and 32 Jun Guo
2026-01-14 14:14   ` Rodrigo Alencar
2026-01-14 14:16     ` Mark Brown
2026-01-14 16:09       ` Rodrigo Alencar
2026-01-15  2:14         ` Jun Guo [this message]
2025-10-31  7:30 ` [PATCH v3 3/3] arm64: dts: cix: add a compatible string for the cix sky1 SoC Jun Guo
2025-11-17  9:32   ` Peter Chen
2025-11-14 17:07 ` (subset) [PATCH v3 0/3] spi-cadence: support transmission with bits_per_word of 16 and 32 Mark Brown

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