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From: Dave Hansen <dave.hansen@intel.com>
To: Paolo Bonzini <pbonzini@redhat.com>,
	linux-kernel@vger.kernel.org, kvm@vger.kernel.org
Cc: Zixi Chen <zixchen@redhat.com>, Adam Dunlap <acdunlap@google.com>,
	"Kirill A . Shutemov" <kirill.shutemov@linux.intel.com>,
	Xiaoyao Li <xiaoyao.li@intel.com>,
	Kai Huang <kai.huang@intel.com>,
	Dave Hansen <dave.hansen@linux.intel.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Ingo Molnar <mingo@kernel.org>,
	x86@kernel.org, stable@vger.kernel.org
Subject: Re: [PATCH v2 0/2] x86/cpu: fix invalid MTRR mask values for SEV or TME
Date: Thu, 1 Feb 2024 13:42:15 -0800	[thread overview]
Message-ID: <897a31a7-7ec3-41b7-867b-0229c0addf5f@intel.com> (raw)
In-Reply-To: <2b5e6d68-007e-48bd-be61-9a354be2ccbf@intel.com>

[-- Attachment #1: Type: text/plain, Size: 153 bytes --]

On 2/1/24 10:29, Dave Hansen wrote:
> Could we instead do something more like the (completely untested)
> attached patch?

... actually attaching it here

[-- Attachment #2: enc_phys_bits.patch --]
[-- Type: text/x-patch, Size: 2069 bytes --]

diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 26620d7642a9..415ae443ef79 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -119,6 +119,7 @@ struct cpuinfo_x86 {
 #endif
 	__u8			x86_virt_bits;
 	__u8			x86_phys_bits;
+	__u8			enc_phys_bits;
 	/* CPUID returned core id bits: */
 	__u8			x86_coreid_bits;
 	/* Max extended CPUID function supported: */
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index f3abca334199..40fc44dfa7a4 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -618,11 +618,13 @@ static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)
 			goto clear_all;
 
 		/*
-		 * Always adjust physical address bits. Even though this
-		 * will be a value above 32-bits this is still done for
-		 * CONFIG_X86_32 so that accurate values are reported.
+		 * Record the number of physical address bits that
+		 * have been repurposed for memory encryption.  Do
+		 * this even on CONFIG_X86_32 configs that do can
+		 * not support memory encryption so it is still
+		 * reported accurately.
 		 */
-		c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f;
+		c->enc_phys_bits = (cpuid_ebx(0x8000001f) >> 6) & 0x3f;
 
 		if (IS_ENABLED(CONFIG_X86_32))
 			goto clear_all;
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 0b97bcde70c6..b998ae7fbbfb 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1098,6 +1098,10 @@ void get_cpu_address_sizes(struct cpuinfo_x86 *c)
 	u32 eax, ebx, ecx, edx;
 	bool vp_bits_from_cpuid = true;
 
+	WARN_ON(c->x86_clflush_size ||
+		c->x86_phys_bits    ||
+		c->x86_virt_bits);
+
 	if (!cpu_has(c, X86_FEATURE_CPUID) ||
 	    (c->extended_cpuid_level < 0x80000008))
 		vp_bits_from_cpuid = false;
@@ -1122,6 +1126,8 @@ void get_cpu_address_sizes(struct cpuinfo_x86 *c)
 				c->x86_phys_bits = 36;
 		}
 	}
+	c->x86_phys_bits -= c->enc_phys_bits;
+
 	c->x86_cache_bits = c->x86_phys_bits;
 	c->x86_cache_alignment = c->x86_clflush_size;
 }

  reply	other threads:[~2024-02-01 21:42 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-31 23:09 [PATCH v2 0/2] x86/cpu: fix invalid MTRR mask values for SEV or TME Paolo Bonzini
2024-01-31 23:09 ` [PATCH v2 1/2] x86/cpu: allow reducing x86_phys_bits during early_identify_cpu() Paolo Bonzini
2024-02-01  8:33   ` Kirill A . Shutemov
2024-02-01 15:44   ` Huang, Kai
2024-01-31 23:09 ` [PATCH v2 2/2] x86/cpu/intel: Detect TME keyid bits before setting MTRR mask registers Paolo Bonzini
2024-02-01  8:34   ` Kirill A . Shutemov
2024-02-01 15:42   ` Huang, Kai
2024-02-01 18:29 ` [PATCH v2 0/2] x86/cpu: fix invalid MTRR mask values for SEV or TME Dave Hansen
2024-02-01 21:42   ` Dave Hansen [this message]
2024-02-01 23:08   ` Paolo Bonzini
2024-02-04 17:21     ` Paolo Bonzini
2024-02-13 15:45       ` Paolo Bonzini
2024-02-13 22:02         ` Dave Hansen
2024-02-13 22:25           ` Paolo Bonzini
2024-02-20 12:22           ` Paolo Bonzini
2024-02-22 18:06             ` Dave Hansen
2024-02-22 18:08               ` Paolo Bonzini
2024-02-26  1:57                 ` Yin Fengwei
2024-02-26 16:21                   ` Dave Hansen
2024-02-27  2:02                     ` Yin Fengwei
2024-02-27  6:08                     ` Yin Fengwei
2024-02-27 13:30                       ` Dave Hansen
2024-02-28  0:07                         ` Yin Fengwei
2024-02-13 17:07     ` Dave Hansen

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