From: Chris Wilson <chris@chris-wilson.co.uk>
To: Zhenyu Wang <zhenyuw@linux.intel.com>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: new blitter ring support from Sandybridge
Date: Tue, 12 Oct 2010 09:34:10 +0100 [thread overview]
Message-ID: <89k83a$9vg4mg@azsmga001.ch.intel.com> (raw)
In-Reply-To: <1286871232-1560-1-git-send-email-zhenyuw@linux.intel.com>
On Tue, 12 Oct 2010 16:13:51 +0800, Zhenyu Wang <zhenyuw@linux.intel.com> wrote:
> This adds new ring for blitter engine starting from Sandybridge.
Thanks, look fairly straightforward. The messy parts are a clear reminder
that I intended to clean up some areas for multiple rings.
* bikeshedding
s/HAS_BLIT_SPLIT/HAS_BLT/ -- the documentation has ingrained BLT engine
into my head (and I hope they haven't changed on a whim for snb)
After initialisation we should not need to care about HAS_BSD/HAS_BLT and
just test whether the ring is initialised or active (depending upon op).
That should dramatically reduce the number of tests in our code and
hopefully lead to further simplifications.
Unified request list (along with per-ring lists) will sort out the mess in
i915_gem_evict and also solve the wrap-around issue.
So no get/put irq again?
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
next prev parent reply other threads:[~2010-10-12 8:34 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-10-12 8:13 [PATCH] drm/i915: new blitter ring support from Sandybridge Zhenyu Wang
2010-10-12 8:13 ` [PATCH] intel: " Zhenyu Wang
2010-10-12 8:34 ` Chris Wilson [this message]
2010-10-12 8:55 ` [PATCH] drm/i915: " Zhenyu Wang
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