[PATCH] Documentation (arm64):Advanced SIMD and floating point support condition

[PATCH] Documentation (arm64):Advanced SIMD and floating point support condition

[Xiquan Zhang]

From: zhangyu <zhangyu550@huawei.com>

Because the kernel code cannot be started from el1
according to the booting.rst.
It is found that CPTR_EL2.FPEN is not configured.
After the configuration, the problem is solved.

Signed-off-by: zhangyu <zhangyu550@huawei.com>
Signed-off-by: zhangxiquan <zhangxiquan@hisilicon.com>
---
 Documentation/arch/arm64/booting.rst | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/arch/arm64/booting.rst b/Documentation/arch/arm64/booting.rst
index dee7b6de864f..ccefc42b51bc 100644
--- a/Documentation/arch/arm64/booting.rst
+++ b/Documentation/arch/arm64/booting.rst
@@ -309,6 +309,7 @@ Before jumping into the kernel, the following conditions must be met:
   - If EL2 is present and the kernel is entered at EL1:

     - CPTR_EL2.TFP (bit 10) must be initialised to 0b0.
+    - CPTR_EL2.FPEN (bit 21:20) must be initialised to 0b11.

   For CPUs with the Scalable Vector Extension (FEAT_SVE) present:

--
2.45.1.windows.1

Re: [PATCH] Documentation (arm64):Advanced SIMD and floating point support condition

[Will Deacon]

On Tue, Apr 08, 2025 at 11:13:09AM +0800, Xiquan Zhang wrote:
> From: zhangyu <zhangyu550@huawei.com>
> 
> Because the kernel code cannot be started from el1
> according to the booting.rst.
> It is found that CPTR_EL2.FPEN is not configured.
> After the configuration, the problem is solved.
> 
> Signed-off-by: zhangyu <zhangyu550@huawei.com>
> Signed-off-by: zhangxiquan <zhangxiquan@hisilicon.com>
> ---
>  Documentation/arch/arm64/booting.rst | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/arch/arm64/booting.rst b/Documentation/arch/arm64/booting.rst
> index dee7b6de864f..ccefc42b51bc 100644
> --- a/Documentation/arch/arm64/booting.rst
> +++ b/Documentation/arch/arm64/booting.rst
> @@ -309,6 +309,7 @@ Before jumping into the kernel, the following conditions must be met:
>    - If EL2 is present and the kernel is entered at EL1:
> 
>      - CPTR_EL2.TFP (bit 10) must be initialised to 0b0.
> +    - CPTR_EL2.FPEN (bit 21:20) must be initialised to 0b11.

Sorry, but I don't quite understand this. CPTR_EL2 has a different format
depending on HCR_EL2.E2H and the FPEN field only exists when that bit is
set to 1. In that case, however, why would the kernel be entered at EL1?

Will

答复: [PATCH] Documentation (arm64):Advanced SIMD and floating point support condition

[Zhangxiquan]

Hi Will,

Thanks for feedback !

After received your email, we discuss the situation , and align the story as :

To test the hardware, we randomly configured the register before entering Linux. 
One of  our  test cases is to set e2h to 1 and start Linux with el1. 
Later, it is found that this test scenario is not a typical application. 

Therefore, we decided :
we withdraw this patch application , it does not need to be submitted. 

Thank you for your reply again ！

Yu-Zhang 

-----邮件原件-----
发件人: Will Deacon [mailto:will@kernel.org]
发送时间: 2025年4月29日 21:11
收件人: Zhangxiquan <zhangxiquan@hisilicon.com>
抄送: catalin.marinas@arm.com; corbet@lwn.net; linux-arm-kernel@lists.infradead.org; linux-doc@vger.kernel.org; linux-kernel@vger.kernel.org; maz@kernel.org
主题: Re: [PATCH] Documentation (arm64):Advanced SIMD and floating point support condition

On Tue, Apr 08, 2025 at 11:13:09AM +0800, Xiquan Zhang wrote:
> From: zhangyu <zhangyu550@huawei.com>
> 
> Because the kernel code cannot be started from el1 according to the 
> booting.rst.
> It is found that CPTR_EL2.FPEN is not configured.
> After the configuration, the problem is solved.
> 
> Signed-off-by: zhangyu <zhangyu550@huawei.com>
> Signed-off-by: zhangxiquan <zhangxiquan@hisilicon.com>
> ---
>  Documentation/arch/arm64/booting.rst | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/arch/arm64/booting.rst
> b/Documentation/arch/arm64/booting.rst
> index dee7b6de864f..ccefc42b51bc 100644
> --- a/Documentation/arch/arm64/booting.rst
> +++ b/Documentation/arch/arm64/booting.rst
> @@ -309,6 +309,7 @@ Before jumping into the kernel, the following conditions must be met:
>    - If EL2 is present and the kernel is entered at EL1:
> 
>      - CPTR_EL2.TFP (bit 10) must be initialised to 0b0.
> +    - CPTR_EL2.FPEN (bit 21:20) must be initialised to 0b11.

Sorry, but I don't quite understand this. CPTR_EL2 has a different format depending on HCR_EL2.E2H and the FPEN field only exists when that bit is set to 1. In that case, however, why would the kernel be entered at EL1?

Will